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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \3; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \4; RUN: | FileCheck -check-prefixes=CHECKIF,RV32IF %s5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \6; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \7; RUN: | FileCheck -check-prefixes=CHECKIF,RV64IF %s8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \9; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32 \10; RUN: | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \12; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64 \13; RUN: | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \15; RUN: -verify-machineinstrs -disable-strictnode-mutation \16; RUN: | FileCheck -check-prefix=RV32I %s17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \18; RUN: -verify-machineinstrs -disable-strictnode-mutation \19; RUN: | FileCheck -check-prefix=RV64I %s20 21define float @sqrt_f32(float %a) nounwind strictfp {22; CHECKIF-LABEL: sqrt_f32:23; CHECKIF: # %bb.0:24; CHECKIF-NEXT: fsqrt.s fa0, fa025; CHECKIF-NEXT: ret26;27; CHECKIZFINX-LABEL: sqrt_f32:28; CHECKIZFINX: # %bb.0:29; CHECKIZFINX-NEXT: fsqrt.s a0, a030; CHECKIZFINX-NEXT: ret31;32; RV32I-LABEL: sqrt_f32:33; RV32I: # %bb.0:34; RV32I-NEXT: addi sp, sp, -1635; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill36; RV32I-NEXT: call sqrtf37; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload38; RV32I-NEXT: addi sp, sp, 1639; RV32I-NEXT: ret40;41; RV64I-LABEL: sqrt_f32:42; RV64I: # %bb.0:43; RV64I-NEXT: addi sp, sp, -1644; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill45; RV64I-NEXT: call sqrtf46; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload47; RV64I-NEXT: addi sp, sp, 1648; RV64I-NEXT: ret49 %1 = call float @llvm.experimental.constrained.sqrt.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp50 ret float %151}52 53define float @powi_f32(float %a, i32 %b) nounwind strictfp {54; RV32IF-LABEL: powi_f32:55; RV32IF: # %bb.0:56; RV32IF-NEXT: addi sp, sp, -1657; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill58; RV32IF-NEXT: call __powisf259; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload60; RV32IF-NEXT: addi sp, sp, 1661; RV32IF-NEXT: ret62;63; RV64IF-LABEL: powi_f32:64; RV64IF: # %bb.0:65; RV64IF-NEXT: addi sp, sp, -1666; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill67; RV64IF-NEXT: sext.w a0, a068; RV64IF-NEXT: call __powisf269; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload70; RV64IF-NEXT: addi sp, sp, 1671; RV64IF-NEXT: ret72;73; RV32IZFINX-LABEL: powi_f32:74; RV32IZFINX: # %bb.0:75; RV32IZFINX-NEXT: addi sp, sp, -1676; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill77; RV32IZFINX-NEXT: call __powisf278; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload79; RV32IZFINX-NEXT: addi sp, sp, 1680; RV32IZFINX-NEXT: ret81;82; RV64IZFINX-LABEL: powi_f32:83; RV64IZFINX: # %bb.0:84; RV64IZFINX-NEXT: addi sp, sp, -1685; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill86; RV64IZFINX-NEXT: sext.w a1, a187; RV64IZFINX-NEXT: call __powisf288; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload89; RV64IZFINX-NEXT: addi sp, sp, 1690; RV64IZFINX-NEXT: ret91;92; RV32I-LABEL: powi_f32:93; RV32I: # %bb.0:94; RV32I-NEXT: addi sp, sp, -1695; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill96; RV32I-NEXT: call __powisf297; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload98; RV32I-NEXT: addi sp, sp, 1699; RV32I-NEXT: ret100;101; RV64I-LABEL: powi_f32:102; RV64I: # %bb.0:103; RV64I-NEXT: addi sp, sp, -16104; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill105; RV64I-NEXT: sext.w a1, a1106; RV64I-NEXT: call __powisf2107; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload108; RV64I-NEXT: addi sp, sp, 16109; RV64I-NEXT: ret110 %1 = call float @llvm.experimental.constrained.powi.f32(float %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp111 ret float %1112}113 114define float @sin_f32(float %a) nounwind strictfp {115; RV32IF-LABEL: sin_f32:116; RV32IF: # %bb.0:117; RV32IF-NEXT: addi sp, sp, -16118; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill119; RV32IF-NEXT: call sinf120; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload121; RV32IF-NEXT: addi sp, sp, 16122; RV32IF-NEXT: ret123;124; RV64IF-LABEL: sin_f32:125; RV64IF: # %bb.0:126; RV64IF-NEXT: addi sp, sp, -16127; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill128; RV64IF-NEXT: call sinf129; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload130; RV64IF-NEXT: addi sp, sp, 16131; RV64IF-NEXT: ret132;133; RV32IZFINX-LABEL: sin_f32:134; RV32IZFINX: # %bb.0:135; RV32IZFINX-NEXT: addi sp, sp, -16136; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill137; RV32IZFINX-NEXT: call sinf138; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload139; RV32IZFINX-NEXT: addi sp, sp, 16140; RV32IZFINX-NEXT: ret141;142; RV64IZFINX-LABEL: sin_f32:143; RV64IZFINX: # %bb.0:144; RV64IZFINX-NEXT: addi sp, sp, -16145; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill146; RV64IZFINX-NEXT: call sinf147; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload148; RV64IZFINX-NEXT: addi sp, sp, 16149; RV64IZFINX-NEXT: ret150;151; RV32I-LABEL: sin_f32:152; RV32I: # %bb.0:153; RV32I-NEXT: addi sp, sp, -16154; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill155; RV32I-NEXT: call sinf156; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload157; RV32I-NEXT: addi sp, sp, 16158; RV32I-NEXT: ret159;160; RV64I-LABEL: sin_f32:161; RV64I: # %bb.0:162; RV64I-NEXT: addi sp, sp, -16163; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill164; RV64I-NEXT: call sinf165; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload166; RV64I-NEXT: addi sp, sp, 16167; RV64I-NEXT: ret168 %1 = call float @llvm.experimental.constrained.sin.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp169 ret float %1170}171 172define float @cos_f32(float %a) nounwind strictfp {173; RV32IF-LABEL: cos_f32:174; RV32IF: # %bb.0:175; RV32IF-NEXT: addi sp, sp, -16176; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill177; RV32IF-NEXT: call cosf178; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload179; RV32IF-NEXT: addi sp, sp, 16180; RV32IF-NEXT: ret181;182; RV64IF-LABEL: cos_f32:183; RV64IF: # %bb.0:184; RV64IF-NEXT: addi sp, sp, -16185; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill186; RV64IF-NEXT: call cosf187; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload188; RV64IF-NEXT: addi sp, sp, 16189; RV64IF-NEXT: ret190;191; RV32IZFINX-LABEL: cos_f32:192; RV32IZFINX: # %bb.0:193; RV32IZFINX-NEXT: addi sp, sp, -16194; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill195; RV32IZFINX-NEXT: call cosf196; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload197; RV32IZFINX-NEXT: addi sp, sp, 16198; RV32IZFINX-NEXT: ret199;200; RV64IZFINX-LABEL: cos_f32:201; RV64IZFINX: # %bb.0:202; RV64IZFINX-NEXT: addi sp, sp, -16203; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill204; RV64IZFINX-NEXT: call cosf205; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload206; RV64IZFINX-NEXT: addi sp, sp, 16207; RV64IZFINX-NEXT: ret208;209; RV32I-LABEL: cos_f32:210; RV32I: # %bb.0:211; RV32I-NEXT: addi sp, sp, -16212; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill213; RV32I-NEXT: call cosf214; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload215; RV32I-NEXT: addi sp, sp, 16216; RV32I-NEXT: ret217;218; RV64I-LABEL: cos_f32:219; RV64I: # %bb.0:220; RV64I-NEXT: addi sp, sp, -16221; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill222; RV64I-NEXT: call cosf223; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload224; RV64I-NEXT: addi sp, sp, 16225; RV64I-NEXT: ret226 %1 = call float @llvm.experimental.constrained.cos.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp227 ret float %1228}229 230; The sin+cos combination results in an FSINCOS SelectionDAG node.231define float @sincos_f32(float %a) nounwind strictfp {232; RV32IF-LABEL: sincos_f32:233; RV32IF: # %bb.0:234; RV32IF-NEXT: addi sp, sp, -16235; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill236; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill237; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill238; RV32IF-NEXT: fmv.s fs0, fa0239; RV32IF-NEXT: call sinf240; RV32IF-NEXT: fmv.s fs1, fa0241; RV32IF-NEXT: fmv.s fa0, fs0242; RV32IF-NEXT: call cosf243; RV32IF-NEXT: fadd.s fa0, fs1, fa0244; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload245; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload246; RV32IF-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload247; RV32IF-NEXT: addi sp, sp, 16248; RV32IF-NEXT: ret249;250; RV64IF-LABEL: sincos_f32:251; RV64IF: # %bb.0:252; RV64IF-NEXT: addi sp, sp, -16253; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill254; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill255; RV64IF-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill256; RV64IF-NEXT: fmv.s fs0, fa0257; RV64IF-NEXT: call sinf258; RV64IF-NEXT: fmv.s fs1, fa0259; RV64IF-NEXT: fmv.s fa0, fs0260; RV64IF-NEXT: call cosf261; RV64IF-NEXT: fadd.s fa0, fs1, fa0262; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload263; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload264; RV64IF-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload265; RV64IF-NEXT: addi sp, sp, 16266; RV64IF-NEXT: ret267;268; RV32IZFINX-LABEL: sincos_f32:269; RV32IZFINX: # %bb.0:270; RV32IZFINX-NEXT: addi sp, sp, -16271; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill272; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill273; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill274; RV32IZFINX-NEXT: mv s0, a0275; RV32IZFINX-NEXT: call sinf276; RV32IZFINX-NEXT: mv s1, a0277; RV32IZFINX-NEXT: mv a0, s0278; RV32IZFINX-NEXT: call cosf279; RV32IZFINX-NEXT: fadd.s a0, s1, a0280; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload281; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload282; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload283; RV32IZFINX-NEXT: addi sp, sp, 16284; RV32IZFINX-NEXT: ret285;286; RV64IZFINX-LABEL: sincos_f32:287; RV64IZFINX: # %bb.0:288; RV64IZFINX-NEXT: addi sp, sp, -32289; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill290; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill291; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill292; RV64IZFINX-NEXT: mv s0, a0293; RV64IZFINX-NEXT: call sinf294; RV64IZFINX-NEXT: mv s1, a0295; RV64IZFINX-NEXT: mv a0, s0296; RV64IZFINX-NEXT: call cosf297; RV64IZFINX-NEXT: fadd.s a0, s1, a0298; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload299; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload300; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload301; RV64IZFINX-NEXT: addi sp, sp, 32302; RV64IZFINX-NEXT: ret303;304; RV32I-LABEL: sincos_f32:305; RV32I: # %bb.0:306; RV32I-NEXT: addi sp, sp, -16307; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill308; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill309; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill310; RV32I-NEXT: mv s0, a0311; RV32I-NEXT: call sinf312; RV32I-NEXT: mv s1, a0313; RV32I-NEXT: mv a0, s0314; RV32I-NEXT: call cosf315; RV32I-NEXT: mv a1, a0316; RV32I-NEXT: mv a0, s1317; RV32I-NEXT: call __addsf3318; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload319; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload320; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload321; RV32I-NEXT: addi sp, sp, 16322; RV32I-NEXT: ret323;324; RV64I-LABEL: sincos_f32:325; RV64I: # %bb.0:326; RV64I-NEXT: addi sp, sp, -32327; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill328; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill329; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill330; RV64I-NEXT: mv s0, a0331; RV64I-NEXT: call sinf332; RV64I-NEXT: mv s1, a0333; RV64I-NEXT: mv a0, s0334; RV64I-NEXT: call cosf335; RV64I-NEXT: mv a1, a0336; RV64I-NEXT: mv a0, s1337; RV64I-NEXT: call __addsf3338; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload339; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload340; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload341; RV64I-NEXT: addi sp, sp, 32342; RV64I-NEXT: ret343 %1 = call float @llvm.experimental.constrained.sin.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp344 %2 = call float @llvm.experimental.constrained.cos.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp345 %3 = fadd float %1, %2346 ret float %3347}348 349define float @tan_f32(float %a) nounwind strictfp {350; RV32IF-LABEL: tan_f32:351; RV32IF: # %bb.0:352; RV32IF-NEXT: addi sp, sp, -16353; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill354; RV32IF-NEXT: call tanf355; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload356; RV32IF-NEXT: addi sp, sp, 16357; RV32IF-NEXT: ret358;359; RV64IF-LABEL: tan_f32:360; RV64IF: # %bb.0:361; RV64IF-NEXT: addi sp, sp, -16362; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill363; RV64IF-NEXT: call tanf364; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload365; RV64IF-NEXT: addi sp, sp, 16366; RV64IF-NEXT: ret367;368; RV32IZFINX-LABEL: tan_f32:369; RV32IZFINX: # %bb.0:370; RV32IZFINX-NEXT: addi sp, sp, -16371; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill372; RV32IZFINX-NEXT: call tanf373; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload374; RV32IZFINX-NEXT: addi sp, sp, 16375; RV32IZFINX-NEXT: ret376;377; RV64IZFINX-LABEL: tan_f32:378; RV64IZFINX: # %bb.0:379; RV64IZFINX-NEXT: addi sp, sp, -16380; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill381; RV64IZFINX-NEXT: call tanf382; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload383; RV64IZFINX-NEXT: addi sp, sp, 16384; RV64IZFINX-NEXT: ret385;386; RV32I-LABEL: tan_f32:387; RV32I: # %bb.0:388; RV32I-NEXT: addi sp, sp, -16389; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill390; RV32I-NEXT: call tanf391; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload392; RV32I-NEXT: addi sp, sp, 16393; RV32I-NEXT: ret394;395; RV64I-LABEL: tan_f32:396; RV64I: # %bb.0:397; RV64I-NEXT: addi sp, sp, -16398; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill399; RV64I-NEXT: call tanf400; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload401; RV64I-NEXT: addi sp, sp, 16402; RV64I-NEXT: ret403 %1 = call float @llvm.experimental.constrained.tan.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp404 ret float %1405}406 407define float @asin_f32(float %a) nounwind strictfp {408; RV32IF-LABEL: asin_f32:409; RV32IF: # %bb.0:410; RV32IF-NEXT: addi sp, sp, -16411; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill412; RV32IF-NEXT: call asinf413; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload414; RV32IF-NEXT: addi sp, sp, 16415; RV32IF-NEXT: ret416;417; RV64IF-LABEL: asin_f32:418; RV64IF: # %bb.0:419; RV64IF-NEXT: addi sp, sp, -16420; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill421; RV64IF-NEXT: call asinf422; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload423; RV64IF-NEXT: addi sp, sp, 16424; RV64IF-NEXT: ret425;426; RV32IZFINX-LABEL: asin_f32:427; RV32IZFINX: # %bb.0:428; RV32IZFINX-NEXT: addi sp, sp, -16429; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill430; RV32IZFINX-NEXT: call asinf431; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload432; RV32IZFINX-NEXT: addi sp, sp, 16433; RV32IZFINX-NEXT: ret434;435; RV64IZFINX-LABEL: asin_f32:436; RV64IZFINX: # %bb.0:437; RV64IZFINX-NEXT: addi sp, sp, -16438; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill439; RV64IZFINX-NEXT: call asinf440; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload441; RV64IZFINX-NEXT: addi sp, sp, 16442; RV64IZFINX-NEXT: ret443;444; RV32I-LABEL: asin_f32:445; RV32I: # %bb.0:446; RV32I-NEXT: addi sp, sp, -16447; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill448; RV32I-NEXT: call asinf449; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload450; RV32I-NEXT: addi sp, sp, 16451; RV32I-NEXT: ret452;453; RV64I-LABEL: asin_f32:454; RV64I: # %bb.0:455; RV64I-NEXT: addi sp, sp, -16456; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill457; RV64I-NEXT: call asinf458; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload459; RV64I-NEXT: addi sp, sp, 16460; RV64I-NEXT: ret461 %1 = call float @llvm.experimental.constrained.asin.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp462 ret float %1463}464 465define float @acos_f32(float %a) nounwind strictfp {466; RV32IF-LABEL: acos_f32:467; RV32IF: # %bb.0:468; RV32IF-NEXT: addi sp, sp, -16469; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill470; RV32IF-NEXT: call acosf471; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload472; RV32IF-NEXT: addi sp, sp, 16473; RV32IF-NEXT: ret474;475; RV64IF-LABEL: acos_f32:476; RV64IF: # %bb.0:477; RV64IF-NEXT: addi sp, sp, -16478; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill479; RV64IF-NEXT: call acosf480; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload481; RV64IF-NEXT: addi sp, sp, 16482; RV64IF-NEXT: ret483;484; RV32IZFINX-LABEL: acos_f32:485; RV32IZFINX: # %bb.0:486; RV32IZFINX-NEXT: addi sp, sp, -16487; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill488; RV32IZFINX-NEXT: call acosf489; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload490; RV32IZFINX-NEXT: addi sp, sp, 16491; RV32IZFINX-NEXT: ret492;493; RV64IZFINX-LABEL: acos_f32:494; RV64IZFINX: # %bb.0:495; RV64IZFINX-NEXT: addi sp, sp, -16496; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill497; RV64IZFINX-NEXT: call acosf498; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload499; RV64IZFINX-NEXT: addi sp, sp, 16500; RV64IZFINX-NEXT: ret501;502; RV32I-LABEL: acos_f32:503; RV32I: # %bb.0:504; RV32I-NEXT: addi sp, sp, -16505; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill506; RV32I-NEXT: call acosf507; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload508; RV32I-NEXT: addi sp, sp, 16509; RV32I-NEXT: ret510;511; RV64I-LABEL: acos_f32:512; RV64I: # %bb.0:513; RV64I-NEXT: addi sp, sp, -16514; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill515; RV64I-NEXT: call acosf516; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload517; RV64I-NEXT: addi sp, sp, 16518; RV64I-NEXT: ret519 %1 = call float @llvm.experimental.constrained.acos.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp520 ret float %1521}522 523define float @atan_f32(float %a) nounwind strictfp {524; RV32IF-LABEL: atan_f32:525; RV32IF: # %bb.0:526; RV32IF-NEXT: addi sp, sp, -16527; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill528; RV32IF-NEXT: call atanf529; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload530; RV32IF-NEXT: addi sp, sp, 16531; RV32IF-NEXT: ret532;533; RV64IF-LABEL: atan_f32:534; RV64IF: # %bb.0:535; RV64IF-NEXT: addi sp, sp, -16536; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill537; RV64IF-NEXT: call atanf538; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload539; RV64IF-NEXT: addi sp, sp, 16540; RV64IF-NEXT: ret541;542; RV32IZFINX-LABEL: atan_f32:543; RV32IZFINX: # %bb.0:544; RV32IZFINX-NEXT: addi sp, sp, -16545; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill546; RV32IZFINX-NEXT: call atanf547; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload548; RV32IZFINX-NEXT: addi sp, sp, 16549; RV32IZFINX-NEXT: ret550;551; RV64IZFINX-LABEL: atan_f32:552; RV64IZFINX: # %bb.0:553; RV64IZFINX-NEXT: addi sp, sp, -16554; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill555; RV64IZFINX-NEXT: call atanf556; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload557; RV64IZFINX-NEXT: addi sp, sp, 16558; RV64IZFINX-NEXT: ret559;560; RV32I-LABEL: atan_f32:561; RV32I: # %bb.0:562; RV32I-NEXT: addi sp, sp, -16563; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill564; RV32I-NEXT: call atanf565; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload566; RV32I-NEXT: addi sp, sp, 16567; RV32I-NEXT: ret568;569; RV64I-LABEL: atan_f32:570; RV64I: # %bb.0:571; RV64I-NEXT: addi sp, sp, -16572; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill573; RV64I-NEXT: call atanf574; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload575; RV64I-NEXT: addi sp, sp, 16576; RV64I-NEXT: ret577 %1 = call float @llvm.experimental.constrained.atan.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp578 ret float %1579}580 581define float @atan2_f32(float %a, float %b) nounwind strictfp {582; RV32IF-LABEL: atan2_f32:583; RV32IF: # %bb.0:584; RV32IF-NEXT: addi sp, sp, -16585; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill586; RV32IF-NEXT: call atan2f587; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload588; RV32IF-NEXT: addi sp, sp, 16589; RV32IF-NEXT: ret590;591; RV64IF-LABEL: atan2_f32:592; RV64IF: # %bb.0:593; RV64IF-NEXT: addi sp, sp, -16594; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill595; RV64IF-NEXT: call atan2f596; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload597; RV64IF-NEXT: addi sp, sp, 16598; RV64IF-NEXT: ret599;600; RV32IZFINX-LABEL: atan2_f32:601; RV32IZFINX: # %bb.0:602; RV32IZFINX-NEXT: addi sp, sp, -16603; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill604; RV32IZFINX-NEXT: call atan2f605; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload606; RV32IZFINX-NEXT: addi sp, sp, 16607; RV32IZFINX-NEXT: ret608;609; RV64IZFINX-LABEL: atan2_f32:610; RV64IZFINX: # %bb.0:611; RV64IZFINX-NEXT: addi sp, sp, -16612; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill613; RV64IZFINX-NEXT: call atan2f614; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload615; RV64IZFINX-NEXT: addi sp, sp, 16616; RV64IZFINX-NEXT: ret617;618; RV32I-LABEL: atan2_f32:619; RV32I: # %bb.0:620; RV32I-NEXT: addi sp, sp, -16621; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill622; RV32I-NEXT: call atan2f623; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload624; RV32I-NEXT: addi sp, sp, 16625; RV32I-NEXT: ret626;627; RV64I-LABEL: atan2_f32:628; RV64I: # %bb.0:629; RV64I-NEXT: addi sp, sp, -16630; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill631; RV64I-NEXT: call atan2f632; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload633; RV64I-NEXT: addi sp, sp, 16634; RV64I-NEXT: ret635 %1 = call float @llvm.experimental.constrained.atan2.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp636 ret float %1637}638 639define float @sinh_f32(float %a) nounwind strictfp {640; RV32IF-LABEL: sinh_f32:641; RV32IF: # %bb.0:642; RV32IF-NEXT: addi sp, sp, -16643; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill644; RV32IF-NEXT: call sinhf645; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload646; RV32IF-NEXT: addi sp, sp, 16647; RV32IF-NEXT: ret648;649; RV64IF-LABEL: sinh_f32:650; RV64IF: # %bb.0:651; RV64IF-NEXT: addi sp, sp, -16652; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill653; RV64IF-NEXT: call sinhf654; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload655; RV64IF-NEXT: addi sp, sp, 16656; RV64IF-NEXT: ret657;658; RV32IZFINX-LABEL: sinh_f32:659; RV32IZFINX: # %bb.0:660; RV32IZFINX-NEXT: addi sp, sp, -16661; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill662; RV32IZFINX-NEXT: call sinhf663; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload664; RV32IZFINX-NEXT: addi sp, sp, 16665; RV32IZFINX-NEXT: ret666;667; RV64IZFINX-LABEL: sinh_f32:668; RV64IZFINX: # %bb.0:669; RV64IZFINX-NEXT: addi sp, sp, -16670; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill671; RV64IZFINX-NEXT: call sinhf672; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload673; RV64IZFINX-NEXT: addi sp, sp, 16674; RV64IZFINX-NEXT: ret675;676; RV32I-LABEL: sinh_f32:677; RV32I: # %bb.0:678; RV32I-NEXT: addi sp, sp, -16679; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill680; RV32I-NEXT: call sinhf681; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload682; RV32I-NEXT: addi sp, sp, 16683; RV32I-NEXT: ret684;685; RV64I-LABEL: sinh_f32:686; RV64I: # %bb.0:687; RV64I-NEXT: addi sp, sp, -16688; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill689; RV64I-NEXT: call sinhf690; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload691; RV64I-NEXT: addi sp, sp, 16692; RV64I-NEXT: ret693 %1 = call float @llvm.experimental.constrained.sinh.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp694 ret float %1695}696 697define float @cosh_f32(float %a) nounwind strictfp {698; RV32IF-LABEL: cosh_f32:699; RV32IF: # %bb.0:700; RV32IF-NEXT: addi sp, sp, -16701; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill702; RV32IF-NEXT: call coshf703; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload704; RV32IF-NEXT: addi sp, sp, 16705; RV32IF-NEXT: ret706;707; RV64IF-LABEL: cosh_f32:708; RV64IF: # %bb.0:709; RV64IF-NEXT: addi sp, sp, -16710; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill711; RV64IF-NEXT: call coshf712; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload713; RV64IF-NEXT: addi sp, sp, 16714; RV64IF-NEXT: ret715;716; RV32IZFINX-LABEL: cosh_f32:717; RV32IZFINX: # %bb.0:718; RV32IZFINX-NEXT: addi sp, sp, -16719; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill720; RV32IZFINX-NEXT: call coshf721; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload722; RV32IZFINX-NEXT: addi sp, sp, 16723; RV32IZFINX-NEXT: ret724;725; RV64IZFINX-LABEL: cosh_f32:726; RV64IZFINX: # %bb.0:727; RV64IZFINX-NEXT: addi sp, sp, -16728; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill729; RV64IZFINX-NEXT: call coshf730; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload731; RV64IZFINX-NEXT: addi sp, sp, 16732; RV64IZFINX-NEXT: ret733;734; RV32I-LABEL: cosh_f32:735; RV32I: # %bb.0:736; RV32I-NEXT: addi sp, sp, -16737; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill738; RV32I-NEXT: call coshf739; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload740; RV32I-NEXT: addi sp, sp, 16741; RV32I-NEXT: ret742;743; RV64I-LABEL: cosh_f32:744; RV64I: # %bb.0:745; RV64I-NEXT: addi sp, sp, -16746; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill747; RV64I-NEXT: call coshf748; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload749; RV64I-NEXT: addi sp, sp, 16750; RV64I-NEXT: ret751 %1 = call float @llvm.experimental.constrained.cosh.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp752 ret float %1753}754 755define float @tanh_f32(float %a) nounwind strictfp {756; RV32IF-LABEL: tanh_f32:757; RV32IF: # %bb.0:758; RV32IF-NEXT: addi sp, sp, -16759; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill760; RV32IF-NEXT: call tanhf761; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload762; RV32IF-NEXT: addi sp, sp, 16763; RV32IF-NEXT: ret764;765; RV64IF-LABEL: tanh_f32:766; RV64IF: # %bb.0:767; RV64IF-NEXT: addi sp, sp, -16768; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill769; RV64IF-NEXT: call tanhf770; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload771; RV64IF-NEXT: addi sp, sp, 16772; RV64IF-NEXT: ret773;774; RV32IZFINX-LABEL: tanh_f32:775; RV32IZFINX: # %bb.0:776; RV32IZFINX-NEXT: addi sp, sp, -16777; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill778; RV32IZFINX-NEXT: call tanhf779; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload780; RV32IZFINX-NEXT: addi sp, sp, 16781; RV32IZFINX-NEXT: ret782;783; RV64IZFINX-LABEL: tanh_f32:784; RV64IZFINX: # %bb.0:785; RV64IZFINX-NEXT: addi sp, sp, -16786; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill787; RV64IZFINX-NEXT: call tanhf788; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload789; RV64IZFINX-NEXT: addi sp, sp, 16790; RV64IZFINX-NEXT: ret791;792; RV32I-LABEL: tanh_f32:793; RV32I: # %bb.0:794; RV32I-NEXT: addi sp, sp, -16795; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill796; RV32I-NEXT: call tanhf797; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload798; RV32I-NEXT: addi sp, sp, 16799; RV32I-NEXT: ret800;801; RV64I-LABEL: tanh_f32:802; RV64I: # %bb.0:803; RV64I-NEXT: addi sp, sp, -16804; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill805; RV64I-NEXT: call tanhf806; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload807; RV64I-NEXT: addi sp, sp, 16808; RV64I-NEXT: ret809 %1 = call float @llvm.experimental.constrained.tanh.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp810 ret float %1811}812 813define float @pow_f32(float %a, float %b) nounwind strictfp {814; RV32IF-LABEL: pow_f32:815; RV32IF: # %bb.0:816; RV32IF-NEXT: addi sp, sp, -16817; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill818; RV32IF-NEXT: call powf819; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload820; RV32IF-NEXT: addi sp, sp, 16821; RV32IF-NEXT: ret822;823; RV64IF-LABEL: pow_f32:824; RV64IF: # %bb.0:825; RV64IF-NEXT: addi sp, sp, -16826; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill827; RV64IF-NEXT: call powf828; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload829; RV64IF-NEXT: addi sp, sp, 16830; RV64IF-NEXT: ret831;832; RV32IZFINX-LABEL: pow_f32:833; RV32IZFINX: # %bb.0:834; RV32IZFINX-NEXT: addi sp, sp, -16835; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill836; RV32IZFINX-NEXT: call powf837; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload838; RV32IZFINX-NEXT: addi sp, sp, 16839; RV32IZFINX-NEXT: ret840;841; RV64IZFINX-LABEL: pow_f32:842; RV64IZFINX: # %bb.0:843; RV64IZFINX-NEXT: addi sp, sp, -16844; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill845; RV64IZFINX-NEXT: call powf846; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload847; RV64IZFINX-NEXT: addi sp, sp, 16848; RV64IZFINX-NEXT: ret849;850; RV32I-LABEL: pow_f32:851; RV32I: # %bb.0:852; RV32I-NEXT: addi sp, sp, -16853; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill854; RV32I-NEXT: call powf855; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload856; RV32I-NEXT: addi sp, sp, 16857; RV32I-NEXT: ret858;859; RV64I-LABEL: pow_f32:860; RV64I: # %bb.0:861; RV64I-NEXT: addi sp, sp, -16862; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill863; RV64I-NEXT: call powf864; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload865; RV64I-NEXT: addi sp, sp, 16866; RV64I-NEXT: ret867 %1 = call float @llvm.experimental.constrained.pow.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp868 ret float %1869}870 871define float @exp_f32(float %a) nounwind strictfp {872; RV32IF-LABEL: exp_f32:873; RV32IF: # %bb.0:874; RV32IF-NEXT: addi sp, sp, -16875; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill876; RV32IF-NEXT: call expf877; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload878; RV32IF-NEXT: addi sp, sp, 16879; RV32IF-NEXT: ret880;881; RV64IF-LABEL: exp_f32:882; RV64IF: # %bb.0:883; RV64IF-NEXT: addi sp, sp, -16884; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill885; RV64IF-NEXT: call expf886; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload887; RV64IF-NEXT: addi sp, sp, 16888; RV64IF-NEXT: ret889;890; RV32IZFINX-LABEL: exp_f32:891; RV32IZFINX: # %bb.0:892; RV32IZFINX-NEXT: addi sp, sp, -16893; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill894; RV32IZFINX-NEXT: call expf895; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload896; RV32IZFINX-NEXT: addi sp, sp, 16897; RV32IZFINX-NEXT: ret898;899; RV64IZFINX-LABEL: exp_f32:900; RV64IZFINX: # %bb.0:901; RV64IZFINX-NEXT: addi sp, sp, -16902; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill903; RV64IZFINX-NEXT: call expf904; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload905; RV64IZFINX-NEXT: addi sp, sp, 16906; RV64IZFINX-NEXT: ret907;908; RV32I-LABEL: exp_f32:909; RV32I: # %bb.0:910; RV32I-NEXT: addi sp, sp, -16911; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill912; RV32I-NEXT: call expf913; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload914; RV32I-NEXT: addi sp, sp, 16915; RV32I-NEXT: ret916;917; RV64I-LABEL: exp_f32:918; RV64I: # %bb.0:919; RV64I-NEXT: addi sp, sp, -16920; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill921; RV64I-NEXT: call expf922; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload923; RV64I-NEXT: addi sp, sp, 16924; RV64I-NEXT: ret925 %1 = call float @llvm.experimental.constrained.exp.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp926 ret float %1927}928 929define float @exp2_f32(float %a) nounwind strictfp {930; RV32IF-LABEL: exp2_f32:931; RV32IF: # %bb.0:932; RV32IF-NEXT: addi sp, sp, -16933; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill934; RV32IF-NEXT: call exp2f935; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload936; RV32IF-NEXT: addi sp, sp, 16937; RV32IF-NEXT: ret938;939; RV64IF-LABEL: exp2_f32:940; RV64IF: # %bb.0:941; RV64IF-NEXT: addi sp, sp, -16942; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill943; RV64IF-NEXT: call exp2f944; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload945; RV64IF-NEXT: addi sp, sp, 16946; RV64IF-NEXT: ret947;948; RV32IZFINX-LABEL: exp2_f32:949; RV32IZFINX: # %bb.0:950; RV32IZFINX-NEXT: addi sp, sp, -16951; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill952; RV32IZFINX-NEXT: call exp2f953; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload954; RV32IZFINX-NEXT: addi sp, sp, 16955; RV32IZFINX-NEXT: ret956;957; RV64IZFINX-LABEL: exp2_f32:958; RV64IZFINX: # %bb.0:959; RV64IZFINX-NEXT: addi sp, sp, -16960; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill961; RV64IZFINX-NEXT: call exp2f962; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload963; RV64IZFINX-NEXT: addi sp, sp, 16964; RV64IZFINX-NEXT: ret965;966; RV32I-LABEL: exp2_f32:967; RV32I: # %bb.0:968; RV32I-NEXT: addi sp, sp, -16969; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill970; RV32I-NEXT: call exp2f971; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload972; RV32I-NEXT: addi sp, sp, 16973; RV32I-NEXT: ret974;975; RV64I-LABEL: exp2_f32:976; RV64I: # %bb.0:977; RV64I-NEXT: addi sp, sp, -16978; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill979; RV64I-NEXT: call exp2f980; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload981; RV64I-NEXT: addi sp, sp, 16982; RV64I-NEXT: ret983 %1 = call float @llvm.experimental.constrained.exp2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp984 ret float %1985}986 987define float @log_f32(float %a) nounwind strictfp {988; RV32IF-LABEL: log_f32:989; RV32IF: # %bb.0:990; RV32IF-NEXT: addi sp, sp, -16991; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill992; RV32IF-NEXT: call logf993; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload994; RV32IF-NEXT: addi sp, sp, 16995; RV32IF-NEXT: ret996;997; RV64IF-LABEL: log_f32:998; RV64IF: # %bb.0:999; RV64IF-NEXT: addi sp, sp, -161000; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1001; RV64IF-NEXT: call logf1002; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1003; RV64IF-NEXT: addi sp, sp, 161004; RV64IF-NEXT: ret1005;1006; RV32IZFINX-LABEL: log_f32:1007; RV32IZFINX: # %bb.0:1008; RV32IZFINX-NEXT: addi sp, sp, -161009; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1010; RV32IZFINX-NEXT: call logf1011; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1012; RV32IZFINX-NEXT: addi sp, sp, 161013; RV32IZFINX-NEXT: ret1014;1015; RV64IZFINX-LABEL: log_f32:1016; RV64IZFINX: # %bb.0:1017; RV64IZFINX-NEXT: addi sp, sp, -161018; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1019; RV64IZFINX-NEXT: call logf1020; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1021; RV64IZFINX-NEXT: addi sp, sp, 161022; RV64IZFINX-NEXT: ret1023;1024; RV32I-LABEL: log_f32:1025; RV32I: # %bb.0:1026; RV32I-NEXT: addi sp, sp, -161027; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1028; RV32I-NEXT: call logf1029; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1030; RV32I-NEXT: addi sp, sp, 161031; RV32I-NEXT: ret1032;1033; RV64I-LABEL: log_f32:1034; RV64I: # %bb.0:1035; RV64I-NEXT: addi sp, sp, -161036; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1037; RV64I-NEXT: call logf1038; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1039; RV64I-NEXT: addi sp, sp, 161040; RV64I-NEXT: ret1041 %1 = call float @llvm.experimental.constrained.log.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1042 ret float %11043}1044 1045define float @log10_f32(float %a) nounwind strictfp {1046; RV32IF-LABEL: log10_f32:1047; RV32IF: # %bb.0:1048; RV32IF-NEXT: addi sp, sp, -161049; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1050; RV32IF-NEXT: call log10f1051; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1052; RV32IF-NEXT: addi sp, sp, 161053; RV32IF-NEXT: ret1054;1055; RV64IF-LABEL: log10_f32:1056; RV64IF: # %bb.0:1057; RV64IF-NEXT: addi sp, sp, -161058; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1059; RV64IF-NEXT: call log10f1060; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1061; RV64IF-NEXT: addi sp, sp, 161062; RV64IF-NEXT: ret1063;1064; RV32IZFINX-LABEL: log10_f32:1065; RV32IZFINX: # %bb.0:1066; RV32IZFINX-NEXT: addi sp, sp, -161067; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1068; RV32IZFINX-NEXT: call log10f1069; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1070; RV32IZFINX-NEXT: addi sp, sp, 161071; RV32IZFINX-NEXT: ret1072;1073; RV64IZFINX-LABEL: log10_f32:1074; RV64IZFINX: # %bb.0:1075; RV64IZFINX-NEXT: addi sp, sp, -161076; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1077; RV64IZFINX-NEXT: call log10f1078; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1079; RV64IZFINX-NEXT: addi sp, sp, 161080; RV64IZFINX-NEXT: ret1081;1082; RV32I-LABEL: log10_f32:1083; RV32I: # %bb.0:1084; RV32I-NEXT: addi sp, sp, -161085; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1086; RV32I-NEXT: call log10f1087; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1088; RV32I-NEXT: addi sp, sp, 161089; RV32I-NEXT: ret1090;1091; RV64I-LABEL: log10_f32:1092; RV64I: # %bb.0:1093; RV64I-NEXT: addi sp, sp, -161094; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1095; RV64I-NEXT: call log10f1096; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1097; RV64I-NEXT: addi sp, sp, 161098; RV64I-NEXT: ret1099 %1 = call float @llvm.experimental.constrained.log10.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1100 ret float %11101}1102 1103define float @log2_f32(float %a) nounwind strictfp {1104; RV32IF-LABEL: log2_f32:1105; RV32IF: # %bb.0:1106; RV32IF-NEXT: addi sp, sp, -161107; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1108; RV32IF-NEXT: call log2f1109; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1110; RV32IF-NEXT: addi sp, sp, 161111; RV32IF-NEXT: ret1112;1113; RV64IF-LABEL: log2_f32:1114; RV64IF: # %bb.0:1115; RV64IF-NEXT: addi sp, sp, -161116; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1117; RV64IF-NEXT: call log2f1118; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1119; RV64IF-NEXT: addi sp, sp, 161120; RV64IF-NEXT: ret1121;1122; RV32IZFINX-LABEL: log2_f32:1123; RV32IZFINX: # %bb.0:1124; RV32IZFINX-NEXT: addi sp, sp, -161125; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1126; RV32IZFINX-NEXT: call log2f1127; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1128; RV32IZFINX-NEXT: addi sp, sp, 161129; RV32IZFINX-NEXT: ret1130;1131; RV64IZFINX-LABEL: log2_f32:1132; RV64IZFINX: # %bb.0:1133; RV64IZFINX-NEXT: addi sp, sp, -161134; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1135; RV64IZFINX-NEXT: call log2f1136; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1137; RV64IZFINX-NEXT: addi sp, sp, 161138; RV64IZFINX-NEXT: ret1139;1140; RV32I-LABEL: log2_f32:1141; RV32I: # %bb.0:1142; RV32I-NEXT: addi sp, sp, -161143; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1144; RV32I-NEXT: call log2f1145; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1146; RV32I-NEXT: addi sp, sp, 161147; RV32I-NEXT: ret1148;1149; RV64I-LABEL: log2_f32:1150; RV64I: # %bb.0:1151; RV64I-NEXT: addi sp, sp, -161152; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1153; RV64I-NEXT: call log2f1154; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1155; RV64I-NEXT: addi sp, sp, 161156; RV64I-NEXT: ret1157 %1 = call float @llvm.experimental.constrained.log2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1158 ret float %11159}1160 1161define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {1162; CHECKIF-LABEL: fma_f32:1163; CHECKIF: # %bb.0:1164; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa21165; CHECKIF-NEXT: ret1166;1167; CHECKIZFINX-LABEL: fma_f32:1168; CHECKIZFINX: # %bb.0:1169; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a21170; CHECKIZFINX-NEXT: ret1171;1172; RV32I-LABEL: fma_f32:1173; RV32I: # %bb.0:1174; RV32I-NEXT: addi sp, sp, -161175; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1176; RV32I-NEXT: call fmaf1177; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1178; RV32I-NEXT: addi sp, sp, 161179; RV32I-NEXT: ret1180;1181; RV64I-LABEL: fma_f32:1182; RV64I: # %bb.0:1183; RV64I-NEXT: addi sp, sp, -161184; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1185; RV64I-NEXT: call fmaf1186; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1187; RV64I-NEXT: addi sp, sp, 161188; RV64I-NEXT: ret1189 %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1190 ret float %11191}1192 1193define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp {1194; CHECKIF-LABEL: fmuladd_f32:1195; CHECKIF: # %bb.0:1196; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa21197; CHECKIF-NEXT: ret1198;1199; CHECKIZFINX-LABEL: fmuladd_f32:1200; CHECKIZFINX: # %bb.0:1201; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a21202; CHECKIZFINX-NEXT: ret1203;1204; RV32I-LABEL: fmuladd_f32:1205; RV32I: # %bb.0:1206; RV32I-NEXT: addi sp, sp, -161207; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1208; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill1209; RV32I-NEXT: mv s0, a21210; RV32I-NEXT: call __mulsf31211; RV32I-NEXT: mv a1, s01212; RV32I-NEXT: call __addsf31213; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1214; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload1215; RV32I-NEXT: addi sp, sp, 161216; RV32I-NEXT: ret1217;1218; RV64I-LABEL: fmuladd_f32:1219; RV64I: # %bb.0:1220; RV64I-NEXT: addi sp, sp, -161221; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1222; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill1223; RV64I-NEXT: mv s0, a21224; RV64I-NEXT: call __mulsf31225; RV64I-NEXT: mv a1, s01226; RV64I-NEXT: call __addsf31227; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1228; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload1229; RV64I-NEXT: addi sp, sp, 161230; RV64I-NEXT: ret1231 %1 = call float @llvm.experimental.constrained.fmuladd.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1232 ret float %11233}1234 1235define float @minnum_f32(float %a, float %b) nounwind strictfp {1236; RV32IF-LABEL: minnum_f32:1237; RV32IF: # %bb.0:1238; RV32IF-NEXT: addi sp, sp, -161239; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1240; RV32IF-NEXT: call fminf1241; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1242; RV32IF-NEXT: addi sp, sp, 161243; RV32IF-NEXT: ret1244;1245; RV64IF-LABEL: minnum_f32:1246; RV64IF: # %bb.0:1247; RV64IF-NEXT: addi sp, sp, -161248; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1249; RV64IF-NEXT: call fminf1250; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1251; RV64IF-NEXT: addi sp, sp, 161252; RV64IF-NEXT: ret1253;1254; RV32IZFINX-LABEL: minnum_f32:1255; RV32IZFINX: # %bb.0:1256; RV32IZFINX-NEXT: addi sp, sp, -161257; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1258; RV32IZFINX-NEXT: call fminf1259; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1260; RV32IZFINX-NEXT: addi sp, sp, 161261; RV32IZFINX-NEXT: ret1262;1263; RV64IZFINX-LABEL: minnum_f32:1264; RV64IZFINX: # %bb.0:1265; RV64IZFINX-NEXT: addi sp, sp, -161266; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1267; RV64IZFINX-NEXT: call fminf1268; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1269; RV64IZFINX-NEXT: addi sp, sp, 161270; RV64IZFINX-NEXT: ret1271;1272; RV32I-LABEL: minnum_f32:1273; RV32I: # %bb.0:1274; RV32I-NEXT: addi sp, sp, -161275; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1276; RV32I-NEXT: call fminf1277; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1278; RV32I-NEXT: addi sp, sp, 161279; RV32I-NEXT: ret1280;1281; RV64I-LABEL: minnum_f32:1282; RV64I: # %bb.0:1283; RV64I-NEXT: addi sp, sp, -161284; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1285; RV64I-NEXT: call fminf1286; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1287; RV64I-NEXT: addi sp, sp, 161288; RV64I-NEXT: ret1289 %1 = call float @llvm.experimental.constrained.minnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp1290 ret float %11291}1292 1293define float @maxnum_f32(float %a, float %b) nounwind strictfp {1294; RV32IF-LABEL: maxnum_f32:1295; RV32IF: # %bb.0:1296; RV32IF-NEXT: addi sp, sp, -161297; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1298; RV32IF-NEXT: call fmaxf1299; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1300; RV32IF-NEXT: addi sp, sp, 161301; RV32IF-NEXT: ret1302;1303; RV64IF-LABEL: maxnum_f32:1304; RV64IF: # %bb.0:1305; RV64IF-NEXT: addi sp, sp, -161306; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1307; RV64IF-NEXT: call fmaxf1308; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1309; RV64IF-NEXT: addi sp, sp, 161310; RV64IF-NEXT: ret1311;1312; RV32IZFINX-LABEL: maxnum_f32:1313; RV32IZFINX: # %bb.0:1314; RV32IZFINX-NEXT: addi sp, sp, -161315; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1316; RV32IZFINX-NEXT: call fmaxf1317; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1318; RV32IZFINX-NEXT: addi sp, sp, 161319; RV32IZFINX-NEXT: ret1320;1321; RV64IZFINX-LABEL: maxnum_f32:1322; RV64IZFINX: # %bb.0:1323; RV64IZFINX-NEXT: addi sp, sp, -161324; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1325; RV64IZFINX-NEXT: call fmaxf1326; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1327; RV64IZFINX-NEXT: addi sp, sp, 161328; RV64IZFINX-NEXT: ret1329;1330; RV32I-LABEL: maxnum_f32:1331; RV32I: # %bb.0:1332; RV32I-NEXT: addi sp, sp, -161333; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1334; RV32I-NEXT: call fmaxf1335; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1336; RV32I-NEXT: addi sp, sp, 161337; RV32I-NEXT: ret1338;1339; RV64I-LABEL: maxnum_f32:1340; RV64I: # %bb.0:1341; RV64I-NEXT: addi sp, sp, -161342; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1343; RV64I-NEXT: call fmaxf1344; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1345; RV64I-NEXT: addi sp, sp, 161346; RV64I-NEXT: ret1347 %1 = call float @llvm.experimental.constrained.maxnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp1348 ret float %11349}1350 1351; TODO: FMINNAN and FMAXNAN aren't handled in1352; SelectionDAGLegalize::ExpandNode.1353 1354; declare float @llvm.experimental.constrained.minimum.f32(float, float, metadata)1355 1356; define float @fminimum_f32(float %a, float %b) nounwind strictfp {1357; %1 = call float @llvm.experimental.constrained.minimum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp1358; ret float %11359; }1360 1361; declare float @llvm.experimental.constrained.maximum.f32(float, float, metadata)1362 1363; define float @fmaximum_f32(float %a, float %b) nounwind strictfp {1364; %1 = call float @llvm.experimental.constrained.maximum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp1365; ret float %11366; }1367 1368define float @floor_f32(float %a) nounwind strictfp {1369; RV32IF-LABEL: floor_f32:1370; RV32IF: # %bb.0:1371; RV32IF-NEXT: addi sp, sp, -161372; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1373; RV32IF-NEXT: call floorf1374; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1375; RV32IF-NEXT: addi sp, sp, 161376; RV32IF-NEXT: ret1377;1378; RV64IF-LABEL: floor_f32:1379; RV64IF: # %bb.0:1380; RV64IF-NEXT: addi sp, sp, -161381; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1382; RV64IF-NEXT: call floorf1383; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1384; RV64IF-NEXT: addi sp, sp, 161385; RV64IF-NEXT: ret1386;1387; RV32IZFINX-LABEL: floor_f32:1388; RV32IZFINX: # %bb.0:1389; RV32IZFINX-NEXT: addi sp, sp, -161390; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1391; RV32IZFINX-NEXT: call floorf1392; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1393; RV32IZFINX-NEXT: addi sp, sp, 161394; RV32IZFINX-NEXT: ret1395;1396; RV64IZFINX-LABEL: floor_f32:1397; RV64IZFINX: # %bb.0:1398; RV64IZFINX-NEXT: addi sp, sp, -161399; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1400; RV64IZFINX-NEXT: call floorf1401; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1402; RV64IZFINX-NEXT: addi sp, sp, 161403; RV64IZFINX-NEXT: ret1404;1405; RV32I-LABEL: floor_f32:1406; RV32I: # %bb.0:1407; RV32I-NEXT: addi sp, sp, -161408; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1409; RV32I-NEXT: call floorf1410; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1411; RV32I-NEXT: addi sp, sp, 161412; RV32I-NEXT: ret1413;1414; RV64I-LABEL: floor_f32:1415; RV64I: # %bb.0:1416; RV64I-NEXT: addi sp, sp, -161417; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1418; RV64I-NEXT: call floorf1419; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1420; RV64I-NEXT: addi sp, sp, 161421; RV64I-NEXT: ret1422 %1 = call float @llvm.experimental.constrained.floor.f32(float %a, metadata !"fpexcept.strict") strictfp1423 ret float %11424}1425 1426define float @ceil_f32(float %a) nounwind strictfp {1427; RV32IF-LABEL: ceil_f32:1428; RV32IF: # %bb.0:1429; RV32IF-NEXT: addi sp, sp, -161430; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1431; RV32IF-NEXT: call ceilf1432; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1433; RV32IF-NEXT: addi sp, sp, 161434; RV32IF-NEXT: ret1435;1436; RV64IF-LABEL: ceil_f32:1437; RV64IF: # %bb.0:1438; RV64IF-NEXT: addi sp, sp, -161439; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1440; RV64IF-NEXT: call ceilf1441; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1442; RV64IF-NEXT: addi sp, sp, 161443; RV64IF-NEXT: ret1444;1445; RV32IZFINX-LABEL: ceil_f32:1446; RV32IZFINX: # %bb.0:1447; RV32IZFINX-NEXT: addi sp, sp, -161448; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1449; RV32IZFINX-NEXT: call ceilf1450; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1451; RV32IZFINX-NEXT: addi sp, sp, 161452; RV32IZFINX-NEXT: ret1453;1454; RV64IZFINX-LABEL: ceil_f32:1455; RV64IZFINX: # %bb.0:1456; RV64IZFINX-NEXT: addi sp, sp, -161457; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1458; RV64IZFINX-NEXT: call ceilf1459; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1460; RV64IZFINX-NEXT: addi sp, sp, 161461; RV64IZFINX-NEXT: ret1462;1463; RV32I-LABEL: ceil_f32:1464; RV32I: # %bb.0:1465; RV32I-NEXT: addi sp, sp, -161466; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1467; RV32I-NEXT: call ceilf1468; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1469; RV32I-NEXT: addi sp, sp, 161470; RV32I-NEXT: ret1471;1472; RV64I-LABEL: ceil_f32:1473; RV64I: # %bb.0:1474; RV64I-NEXT: addi sp, sp, -161475; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1476; RV64I-NEXT: call ceilf1477; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1478; RV64I-NEXT: addi sp, sp, 161479; RV64I-NEXT: ret1480 %1 = call float @llvm.experimental.constrained.ceil.f32(float %a, metadata !"fpexcept.strict") strictfp1481 ret float %11482}1483 1484define float @trunc_f32(float %a) nounwind strictfp {1485; RV32IF-LABEL: trunc_f32:1486; RV32IF: # %bb.0:1487; RV32IF-NEXT: addi sp, sp, -161488; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1489; RV32IF-NEXT: call truncf1490; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1491; RV32IF-NEXT: addi sp, sp, 161492; RV32IF-NEXT: ret1493;1494; RV64IF-LABEL: trunc_f32:1495; RV64IF: # %bb.0:1496; RV64IF-NEXT: addi sp, sp, -161497; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1498; RV64IF-NEXT: call truncf1499; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1500; RV64IF-NEXT: addi sp, sp, 161501; RV64IF-NEXT: ret1502;1503; RV32IZFINX-LABEL: trunc_f32:1504; RV32IZFINX: # %bb.0:1505; RV32IZFINX-NEXT: addi sp, sp, -161506; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1507; RV32IZFINX-NEXT: call truncf1508; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1509; RV32IZFINX-NEXT: addi sp, sp, 161510; RV32IZFINX-NEXT: ret1511;1512; RV64IZFINX-LABEL: trunc_f32:1513; RV64IZFINX: # %bb.0:1514; RV64IZFINX-NEXT: addi sp, sp, -161515; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1516; RV64IZFINX-NEXT: call truncf1517; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1518; RV64IZFINX-NEXT: addi sp, sp, 161519; RV64IZFINX-NEXT: ret1520;1521; RV32I-LABEL: trunc_f32:1522; RV32I: # %bb.0:1523; RV32I-NEXT: addi sp, sp, -161524; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1525; RV32I-NEXT: call truncf1526; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1527; RV32I-NEXT: addi sp, sp, 161528; RV32I-NEXT: ret1529;1530; RV64I-LABEL: trunc_f32:1531; RV64I: # %bb.0:1532; RV64I-NEXT: addi sp, sp, -161533; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1534; RV64I-NEXT: call truncf1535; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1536; RV64I-NEXT: addi sp, sp, 161537; RV64I-NEXT: ret1538 %1 = call float @llvm.experimental.constrained.trunc.f32(float %a, metadata !"fpexcept.strict") strictfp1539 ret float %11540}1541 1542define float @rint_f32(float %a) nounwind strictfp {1543; RV32IF-LABEL: rint_f32:1544; RV32IF: # %bb.0:1545; RV32IF-NEXT: addi sp, sp, -161546; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1547; RV32IF-NEXT: call rintf1548; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1549; RV32IF-NEXT: addi sp, sp, 161550; RV32IF-NEXT: ret1551;1552; RV64IF-LABEL: rint_f32:1553; RV64IF: # %bb.0:1554; RV64IF-NEXT: addi sp, sp, -161555; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1556; RV64IF-NEXT: call rintf1557; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1558; RV64IF-NEXT: addi sp, sp, 161559; RV64IF-NEXT: ret1560;1561; RV32IZFINX-LABEL: rint_f32:1562; RV32IZFINX: # %bb.0:1563; RV32IZFINX-NEXT: addi sp, sp, -161564; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1565; RV32IZFINX-NEXT: call rintf1566; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1567; RV32IZFINX-NEXT: addi sp, sp, 161568; RV32IZFINX-NEXT: ret1569;1570; RV64IZFINX-LABEL: rint_f32:1571; RV64IZFINX: # %bb.0:1572; RV64IZFINX-NEXT: addi sp, sp, -161573; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1574; RV64IZFINX-NEXT: call rintf1575; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1576; RV64IZFINX-NEXT: addi sp, sp, 161577; RV64IZFINX-NEXT: ret1578;1579; RV32I-LABEL: rint_f32:1580; RV32I: # %bb.0:1581; RV32I-NEXT: addi sp, sp, -161582; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1583; RV32I-NEXT: call rintf1584; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1585; RV32I-NEXT: addi sp, sp, 161586; RV32I-NEXT: ret1587;1588; RV64I-LABEL: rint_f32:1589; RV64I: # %bb.0:1590; RV64I-NEXT: addi sp, sp, -161591; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1592; RV64I-NEXT: call rintf1593; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1594; RV64I-NEXT: addi sp, sp, 161595; RV64I-NEXT: ret1596 %1 = call float @llvm.experimental.constrained.rint.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1597 ret float %11598}1599 1600define float @nearbyint_f32(float %a) nounwind strictfp {1601; RV32IF-LABEL: nearbyint_f32:1602; RV32IF: # %bb.0:1603; RV32IF-NEXT: addi sp, sp, -161604; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1605; RV32IF-NEXT: call nearbyintf1606; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1607; RV32IF-NEXT: addi sp, sp, 161608; RV32IF-NEXT: ret1609;1610; RV64IF-LABEL: nearbyint_f32:1611; RV64IF: # %bb.0:1612; RV64IF-NEXT: addi sp, sp, -161613; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1614; RV64IF-NEXT: call nearbyintf1615; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1616; RV64IF-NEXT: addi sp, sp, 161617; RV64IF-NEXT: ret1618;1619; RV32IZFINX-LABEL: nearbyint_f32:1620; RV32IZFINX: # %bb.0:1621; RV32IZFINX-NEXT: addi sp, sp, -161622; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1623; RV32IZFINX-NEXT: call nearbyintf1624; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1625; RV32IZFINX-NEXT: addi sp, sp, 161626; RV32IZFINX-NEXT: ret1627;1628; RV64IZFINX-LABEL: nearbyint_f32:1629; RV64IZFINX: # %bb.0:1630; RV64IZFINX-NEXT: addi sp, sp, -161631; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1632; RV64IZFINX-NEXT: call nearbyintf1633; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1634; RV64IZFINX-NEXT: addi sp, sp, 161635; RV64IZFINX-NEXT: ret1636;1637; RV32I-LABEL: nearbyint_f32:1638; RV32I: # %bb.0:1639; RV32I-NEXT: addi sp, sp, -161640; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1641; RV32I-NEXT: call nearbyintf1642; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1643; RV32I-NEXT: addi sp, sp, 161644; RV32I-NEXT: ret1645;1646; RV64I-LABEL: nearbyint_f32:1647; RV64I: # %bb.0:1648; RV64I-NEXT: addi sp, sp, -161649; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1650; RV64I-NEXT: call nearbyintf1651; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1652; RV64I-NEXT: addi sp, sp, 161653; RV64I-NEXT: ret1654 %1 = call float @llvm.experimental.constrained.nearbyint.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1655 ret float %11656}1657 1658define float @round_f32(float %a) nounwind strictfp {1659; RV32IF-LABEL: round_f32:1660; RV32IF: # %bb.0:1661; RV32IF-NEXT: addi sp, sp, -161662; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1663; RV32IF-NEXT: call roundf1664; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1665; RV32IF-NEXT: addi sp, sp, 161666; RV32IF-NEXT: ret1667;1668; RV64IF-LABEL: round_f32:1669; RV64IF: # %bb.0:1670; RV64IF-NEXT: addi sp, sp, -161671; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1672; RV64IF-NEXT: call roundf1673; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1674; RV64IF-NEXT: addi sp, sp, 161675; RV64IF-NEXT: ret1676;1677; RV32IZFINX-LABEL: round_f32:1678; RV32IZFINX: # %bb.0:1679; RV32IZFINX-NEXT: addi sp, sp, -161680; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1681; RV32IZFINX-NEXT: call roundf1682; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1683; RV32IZFINX-NEXT: addi sp, sp, 161684; RV32IZFINX-NEXT: ret1685;1686; RV64IZFINX-LABEL: round_f32:1687; RV64IZFINX: # %bb.0:1688; RV64IZFINX-NEXT: addi sp, sp, -161689; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1690; RV64IZFINX-NEXT: call roundf1691; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1692; RV64IZFINX-NEXT: addi sp, sp, 161693; RV64IZFINX-NEXT: ret1694;1695; RV32I-LABEL: round_f32:1696; RV32I: # %bb.0:1697; RV32I-NEXT: addi sp, sp, -161698; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1699; RV32I-NEXT: call roundf1700; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1701; RV32I-NEXT: addi sp, sp, 161702; RV32I-NEXT: ret1703;1704; RV64I-LABEL: round_f32:1705; RV64I: # %bb.0:1706; RV64I-NEXT: addi sp, sp, -161707; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1708; RV64I-NEXT: call roundf1709; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1710; RV64I-NEXT: addi sp, sp, 161711; RV64I-NEXT: ret1712 %1 = call float @llvm.experimental.constrained.round.f32(float %a, metadata !"fpexcept.strict") strictfp1713 ret float %11714}1715 1716define float @roundeven_f32(float %a) nounwind strictfp {1717; RV32IF-LABEL: roundeven_f32:1718; RV32IF: # %bb.0:1719; RV32IF-NEXT: addi sp, sp, -161720; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1721; RV32IF-NEXT: call roundevenf1722; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1723; RV32IF-NEXT: addi sp, sp, 161724; RV32IF-NEXT: ret1725;1726; RV64IF-LABEL: roundeven_f32:1727; RV64IF: # %bb.0:1728; RV64IF-NEXT: addi sp, sp, -161729; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1730; RV64IF-NEXT: call roundevenf1731; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1732; RV64IF-NEXT: addi sp, sp, 161733; RV64IF-NEXT: ret1734;1735; RV32IZFINX-LABEL: roundeven_f32:1736; RV32IZFINX: # %bb.0:1737; RV32IZFINX-NEXT: addi sp, sp, -161738; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1739; RV32IZFINX-NEXT: call roundevenf1740; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1741; RV32IZFINX-NEXT: addi sp, sp, 161742; RV32IZFINX-NEXT: ret1743;1744; RV64IZFINX-LABEL: roundeven_f32:1745; RV64IZFINX: # %bb.0:1746; RV64IZFINX-NEXT: addi sp, sp, -161747; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1748; RV64IZFINX-NEXT: call roundevenf1749; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1750; RV64IZFINX-NEXT: addi sp, sp, 161751; RV64IZFINX-NEXT: ret1752;1753; RV32I-LABEL: roundeven_f32:1754; RV32I: # %bb.0:1755; RV32I-NEXT: addi sp, sp, -161756; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1757; RV32I-NEXT: call roundevenf1758; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1759; RV32I-NEXT: addi sp, sp, 161760; RV32I-NEXT: ret1761;1762; RV64I-LABEL: roundeven_f32:1763; RV64I: # %bb.0:1764; RV64I-NEXT: addi sp, sp, -161765; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1766; RV64I-NEXT: call roundevenf1767; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1768; RV64I-NEXT: addi sp, sp, 161769; RV64I-NEXT: ret1770 %1 = call float @llvm.experimental.constrained.roundeven.f32(float %a, metadata !"fpexcept.strict") strictfp1771 ret float %11772}1773 1774define iXLen @lrint_f32(float %a) nounwind strictfp {1775; RV32IF-LABEL: lrint_f32:1776; RV32IF: # %bb.0:1777; RV32IF-NEXT: fcvt.w.s a0, fa01778; RV32IF-NEXT: ret1779;1780; RV64IF-LABEL: lrint_f32:1781; RV64IF: # %bb.0:1782; RV64IF-NEXT: fcvt.l.s a0, fa01783; RV64IF-NEXT: ret1784;1785; RV32IZFINX-LABEL: lrint_f32:1786; RV32IZFINX: # %bb.0:1787; RV32IZFINX-NEXT: fcvt.w.s a0, a01788; RV32IZFINX-NEXT: ret1789;1790; RV64IZFINX-LABEL: lrint_f32:1791; RV64IZFINX: # %bb.0:1792; RV64IZFINX-NEXT: fcvt.l.s a0, a01793; RV64IZFINX-NEXT: ret1794;1795; RV32I-LABEL: lrint_f32:1796; RV32I: # %bb.0:1797; RV32I-NEXT: addi sp, sp, -161798; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1799; RV32I-NEXT: call lrintf1800; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1801; RV32I-NEXT: addi sp, sp, 161802; RV32I-NEXT: ret1803;1804; RV64I-LABEL: lrint_f32:1805; RV64I: # %bb.0:1806; RV64I-NEXT: addi sp, sp, -161807; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1808; RV64I-NEXT: call lrintf1809; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1810; RV64I-NEXT: addi sp, sp, 161811; RV64I-NEXT: ret1812 %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1813 ret iXLen %11814}1815 1816define iXLen @lround_f32(float %a) nounwind strictfp {1817; RV32IF-LABEL: lround_f32:1818; RV32IF: # %bb.0:1819; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm1820; RV32IF-NEXT: ret1821;1822; RV64IF-LABEL: lround_f32:1823; RV64IF: # %bb.0:1824; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm1825; RV64IF-NEXT: ret1826;1827; RV32IZFINX-LABEL: lround_f32:1828; RV32IZFINX: # %bb.0:1829; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm1830; RV32IZFINX-NEXT: ret1831;1832; RV64IZFINX-LABEL: lround_f32:1833; RV64IZFINX: # %bb.0:1834; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm1835; RV64IZFINX-NEXT: ret1836;1837; RV32I-LABEL: lround_f32:1838; RV32I: # %bb.0:1839; RV32I-NEXT: addi sp, sp, -161840; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1841; RV32I-NEXT: call lroundf1842; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1843; RV32I-NEXT: addi sp, sp, 161844; RV32I-NEXT: ret1845;1846; RV64I-LABEL: lround_f32:1847; RV64I: # %bb.0:1848; RV64I-NEXT: addi sp, sp, -161849; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1850; RV64I-NEXT: call lroundf1851; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1852; RV64I-NEXT: addi sp, sp, 161853; RV64I-NEXT: ret1854 %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f32(float %a, metadata !"fpexcept.strict") strictfp1855 ret iXLen %11856}1857 1858define i64 @llrint_f32(float %a) nounwind strictfp {1859; RV32IF-LABEL: llrint_f32:1860; RV32IF: # %bb.0:1861; RV32IF-NEXT: addi sp, sp, -161862; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1863; RV32IF-NEXT: call llrintf1864; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1865; RV32IF-NEXT: addi sp, sp, 161866; RV32IF-NEXT: ret1867;1868; RV64IF-LABEL: llrint_f32:1869; RV64IF: # %bb.0:1870; RV64IF-NEXT: fcvt.l.s a0, fa01871; RV64IF-NEXT: ret1872;1873; RV32IZFINX-LABEL: llrint_f32:1874; RV32IZFINX: # %bb.0:1875; RV32IZFINX-NEXT: addi sp, sp, -161876; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1877; RV32IZFINX-NEXT: call llrintf1878; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1879; RV32IZFINX-NEXT: addi sp, sp, 161880; RV32IZFINX-NEXT: ret1881;1882; RV64IZFINX-LABEL: llrint_f32:1883; RV64IZFINX: # %bb.0:1884; RV64IZFINX-NEXT: fcvt.l.s a0, a01885; RV64IZFINX-NEXT: ret1886;1887; RV32I-LABEL: llrint_f32:1888; RV32I: # %bb.0:1889; RV32I-NEXT: addi sp, sp, -161890; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1891; RV32I-NEXT: call llrintf1892; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1893; RV32I-NEXT: addi sp, sp, 161894; RV32I-NEXT: ret1895;1896; RV64I-LABEL: llrint_f32:1897; RV64I: # %bb.0:1898; RV64I-NEXT: addi sp, sp, -161899; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1900; RV64I-NEXT: call llrintf1901; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1902; RV64I-NEXT: addi sp, sp, 161903; RV64I-NEXT: ret1904 %1 = call i64 @llvm.experimental.constrained.llrint.i64.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp1905 ret i64 %11906}1907 1908define i64 @llround_f32(float %a) nounwind strictfp {1909; RV32IF-LABEL: llround_f32:1910; RV32IF: # %bb.0:1911; RV32IF-NEXT: addi sp, sp, -161912; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1913; RV32IF-NEXT: call llroundf1914; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1915; RV32IF-NEXT: addi sp, sp, 161916; RV32IF-NEXT: ret1917;1918; RV64IF-LABEL: llround_f32:1919; RV64IF: # %bb.0:1920; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm1921; RV64IF-NEXT: ret1922;1923; RV32IZFINX-LABEL: llround_f32:1924; RV32IZFINX: # %bb.0:1925; RV32IZFINX-NEXT: addi sp, sp, -161926; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1927; RV32IZFINX-NEXT: call llroundf1928; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1929; RV32IZFINX-NEXT: addi sp, sp, 161930; RV32IZFINX-NEXT: ret1931;1932; RV64IZFINX-LABEL: llround_f32:1933; RV64IZFINX: # %bb.0:1934; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm1935; RV64IZFINX-NEXT: ret1936;1937; RV32I-LABEL: llround_f32:1938; RV32I: # %bb.0:1939; RV32I-NEXT: addi sp, sp, -161940; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1941; RV32I-NEXT: call llroundf1942; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1943; RV32I-NEXT: addi sp, sp, 161944; RV32I-NEXT: ret1945;1946; RV64I-LABEL: llround_f32:1947; RV64I: # %bb.0:1948; RV64I-NEXT: addi sp, sp, -161949; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1950; RV64I-NEXT: call llroundf1951; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1952; RV64I-NEXT: addi sp, sp, 161953; RV64I-NEXT: ret1954 %1 = call i64 @llvm.experimental.constrained.llround.i64.f32(float %a, metadata !"fpexcept.strict") strictfp1955 ret i64 %11956}1957 1958define float @ldexp_f32(float %x, i32 signext %y) nounwind {1959; RV32IF-LABEL: ldexp_f32:1960; RV32IF: # %bb.0:1961; RV32IF-NEXT: addi sp, sp, -161962; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1963; RV32IF-NEXT: call ldexpf1964; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1965; RV32IF-NEXT: addi sp, sp, 161966; RV32IF-NEXT: ret1967;1968; RV64IF-LABEL: ldexp_f32:1969; RV64IF: # %bb.0:1970; RV64IF-NEXT: addi sp, sp, -161971; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1972; RV64IF-NEXT: call ldexpf1973; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1974; RV64IF-NEXT: addi sp, sp, 161975; RV64IF-NEXT: ret1976;1977; RV32IZFINX-LABEL: ldexp_f32:1978; RV32IZFINX: # %bb.0:1979; RV32IZFINX-NEXT: addi sp, sp, -161980; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1981; RV32IZFINX-NEXT: call ldexpf1982; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1983; RV32IZFINX-NEXT: addi sp, sp, 161984; RV32IZFINX-NEXT: ret1985;1986; RV64IZFINX-LABEL: ldexp_f32:1987; RV64IZFINX: # %bb.0:1988; RV64IZFINX-NEXT: addi sp, sp, -161989; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1990; RV64IZFINX-NEXT: call ldexpf1991; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1992; RV64IZFINX-NEXT: addi sp, sp, 161993; RV64IZFINX-NEXT: ret1994;1995; RV32I-LABEL: ldexp_f32:1996; RV32I: # %bb.0:1997; RV32I-NEXT: addi sp, sp, -161998; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1999; RV32I-NEXT: call ldexpf2000; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2001; RV32I-NEXT: addi sp, sp, 162002; RV32I-NEXT: ret2003;2004; RV64I-LABEL: ldexp_f32:2005; RV64I: # %bb.0:2006; RV64I-NEXT: addi sp, sp, -162007; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2008; RV64I-NEXT: call ldexpf2009; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2010; RV64I-NEXT: addi sp, sp, 162011; RV64I-NEXT: ret2012 %z = call float @llvm.experimental.constrained.ldexp.f32.i32(float %x, i32 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp2013 ret float %z2014}2015