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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \3; RUN: -verify-machineinstrs -target-abi=ilp32f \4; RUN: | FileCheck -check-prefix=RV32IF %s5; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \6; RUN: -verify-machineinstrs -target-abi=ilp32 \7; RUN: | FileCheck -check-prefix=RV32IZFINX %s8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \9; RUN: -verify-machineinstrs -target-abi=ilp32f \10; RUN: | FileCheck -check-prefix=RV32IF %s11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \12; RUN: -verify-machineinstrs -target-abi=lp64f \13; RUN: | FileCheck -check-prefix=RV64IF %s14; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \15; RUN: -verify-machineinstrs -target-abi=lp64 \16; RUN: | FileCheck -check-prefix=RV64IZFINX %s17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \18; RUN: -verify-machineinstrs -target-abi=lp64d \19; RUN: | FileCheck -check-prefixes=RV64IFD %s20; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \21; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s22; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \23; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s24 25define float @sqrt_f32(float %a) nounwind {26; RV32IF-LABEL: sqrt_f32:27; RV32IF: # %bb.0:28; RV32IF-NEXT: fsqrt.s fa0, fa029; RV32IF-NEXT: ret30;31; RV32IZFINX-LABEL: sqrt_f32:32; RV32IZFINX: # %bb.0:33; RV32IZFINX-NEXT: fsqrt.s a0, a034; RV32IZFINX-NEXT: ret35;36; RV64IF-LABEL: sqrt_f32:37; RV64IF: # %bb.0:38; RV64IF-NEXT: fsqrt.s fa0, fa039; RV64IF-NEXT: ret40;41; RV64IZFINX-LABEL: sqrt_f32:42; RV64IZFINX: # %bb.0:43; RV64IZFINX-NEXT: fsqrt.s a0, a044; RV64IZFINX-NEXT: ret45;46; RV64IFD-LABEL: sqrt_f32:47; RV64IFD: # %bb.0:48; RV64IFD-NEXT: fsqrt.s fa0, fa049; RV64IFD-NEXT: ret50;51; RV32I-LABEL: sqrt_f32:52; RV32I: # %bb.0:53; RV32I-NEXT: addi sp, sp, -1654; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill55; RV32I-NEXT: call sqrtf56; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload57; RV32I-NEXT: addi sp, sp, 1658; RV32I-NEXT: ret59;60; RV64I-LABEL: sqrt_f32:61; RV64I: # %bb.0:62; RV64I-NEXT: addi sp, sp, -1663; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill64; RV64I-NEXT: call sqrtf65; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload66; RV64I-NEXT: addi sp, sp, 1667; RV64I-NEXT: ret68 %1 = call float @llvm.sqrt.f32(float %a)69 ret float %170}71 72define float @powi_f32(float %a, i32 %b) nounwind {73; RV32IF-LABEL: powi_f32:74; RV32IF: # %bb.0:75; RV32IF-NEXT: tail __powisf276;77; RV32IZFINX-LABEL: powi_f32:78; RV32IZFINX: # %bb.0:79; RV32IZFINX-NEXT: tail __powisf280;81; RV64IF-LABEL: powi_f32:82; RV64IF: # %bb.0:83; RV64IF-NEXT: addi sp, sp, -1684; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill85; RV64IF-NEXT: sext.w a0, a086; RV64IF-NEXT: call __powisf287; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload88; RV64IF-NEXT: addi sp, sp, 1689; RV64IF-NEXT: ret90;91; RV64IZFINX-LABEL: powi_f32:92; RV64IZFINX: # %bb.0:93; RV64IZFINX-NEXT: addi sp, sp, -1694; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill95; RV64IZFINX-NEXT: sext.w a1, a196; RV64IZFINX-NEXT: call __powisf297; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload98; RV64IZFINX-NEXT: addi sp, sp, 1699; RV64IZFINX-NEXT: ret100;101; RV64IFD-LABEL: powi_f32:102; RV64IFD: # %bb.0:103; RV64IFD-NEXT: addi sp, sp, -16104; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill105; RV64IFD-NEXT: sext.w a0, a0106; RV64IFD-NEXT: call __powisf2107; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload108; RV64IFD-NEXT: addi sp, sp, 16109; RV64IFD-NEXT: ret110;111; RV32I-LABEL: powi_f32:112; RV32I: # %bb.0:113; RV32I-NEXT: addi sp, sp, -16114; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill115; RV32I-NEXT: call __powisf2116; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload117; RV32I-NEXT: addi sp, sp, 16118; RV32I-NEXT: ret119;120; RV64I-LABEL: powi_f32:121; RV64I: # %bb.0:122; RV64I-NEXT: addi sp, sp, -16123; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill124; RV64I-NEXT: sext.w a1, a1125; RV64I-NEXT: call __powisf2126; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload127; RV64I-NEXT: addi sp, sp, 16128; RV64I-NEXT: ret129 %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)130 ret float %1131}132 133define float @sin_f32(float %a) nounwind {134; RV32IF-LABEL: sin_f32:135; RV32IF: # %bb.0:136; RV32IF-NEXT: tail sinf137;138; RV32IZFINX-LABEL: sin_f32:139; RV32IZFINX: # %bb.0:140; RV32IZFINX-NEXT: tail sinf141;142; RV64IF-LABEL: sin_f32:143; RV64IF: # %bb.0:144; RV64IF-NEXT: tail sinf145;146; RV64IZFINX-LABEL: sin_f32:147; RV64IZFINX: # %bb.0:148; RV64IZFINX-NEXT: tail sinf149;150; RV64IFD-LABEL: sin_f32:151; RV64IFD: # %bb.0:152; RV64IFD-NEXT: tail sinf153;154; RV32I-LABEL: sin_f32:155; RV32I: # %bb.0:156; RV32I-NEXT: addi sp, sp, -16157; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill158; RV32I-NEXT: call sinf159; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload160; RV32I-NEXT: addi sp, sp, 16161; RV32I-NEXT: ret162;163; RV64I-LABEL: sin_f32:164; RV64I: # %bb.0:165; RV64I-NEXT: addi sp, sp, -16166; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill167; RV64I-NEXT: call sinf168; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload169; RV64I-NEXT: addi sp, sp, 16170; RV64I-NEXT: ret171 %1 = call float @llvm.sin.f32(float %a)172 ret float %1173}174 175define float @cos_f32(float %a) nounwind {176; RV32IF-LABEL: cos_f32:177; RV32IF: # %bb.0:178; RV32IF-NEXT: tail cosf179;180; RV32IZFINX-LABEL: cos_f32:181; RV32IZFINX: # %bb.0:182; RV32IZFINX-NEXT: tail cosf183;184; RV64IF-LABEL: cos_f32:185; RV64IF: # %bb.0:186; RV64IF-NEXT: tail cosf187;188; RV64IZFINX-LABEL: cos_f32:189; RV64IZFINX: # %bb.0:190; RV64IZFINX-NEXT: tail cosf191;192; RV64IFD-LABEL: cos_f32:193; RV64IFD: # %bb.0:194; RV64IFD-NEXT: tail cosf195;196; RV32I-LABEL: cos_f32:197; RV32I: # %bb.0:198; RV32I-NEXT: addi sp, sp, -16199; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill200; RV32I-NEXT: call cosf201; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload202; RV32I-NEXT: addi sp, sp, 16203; RV32I-NEXT: ret204;205; RV64I-LABEL: cos_f32:206; RV64I: # %bb.0:207; RV64I-NEXT: addi sp, sp, -16208; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill209; RV64I-NEXT: call cosf210; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload211; RV64I-NEXT: addi sp, sp, 16212; RV64I-NEXT: ret213 %1 = call float @llvm.cos.f32(float %a)214 ret float %1215}216 217; The sin+cos combination results in an FSINCOS SelectionDAG node.218define float @sincos_f32(float %a) nounwind {219; RV32IF-LABEL: sincos_f32:220; RV32IF: # %bb.0:221; RV32IF-NEXT: addi sp, sp, -16222; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill223; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill224; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill225; RV32IF-NEXT: fmv.s fs0, fa0226; RV32IF-NEXT: call sinf227; RV32IF-NEXT: fmv.s fs1, fa0228; RV32IF-NEXT: fmv.s fa0, fs0229; RV32IF-NEXT: call cosf230; RV32IF-NEXT: fadd.s fa0, fs1, fa0231; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload232; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload233; RV32IF-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload234; RV32IF-NEXT: addi sp, sp, 16235; RV32IF-NEXT: ret236;237; RV32IZFINX-LABEL: sincos_f32:238; RV32IZFINX: # %bb.0:239; RV32IZFINX-NEXT: addi sp, sp, -16240; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill241; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill242; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill243; RV32IZFINX-NEXT: mv s0, a0244; RV32IZFINX-NEXT: call sinf245; RV32IZFINX-NEXT: mv s1, a0246; RV32IZFINX-NEXT: mv a0, s0247; RV32IZFINX-NEXT: call cosf248; RV32IZFINX-NEXT: fadd.s a0, s1, a0249; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload250; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload251; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload252; RV32IZFINX-NEXT: addi sp, sp, 16253; RV32IZFINX-NEXT: ret254;255; RV64IF-LABEL: sincos_f32:256; RV64IF: # %bb.0:257; RV64IF-NEXT: addi sp, sp, -16258; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill259; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill260; RV64IF-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill261; RV64IF-NEXT: fmv.s fs0, fa0262; RV64IF-NEXT: call sinf263; RV64IF-NEXT: fmv.s fs1, fa0264; RV64IF-NEXT: fmv.s fa0, fs0265; RV64IF-NEXT: call cosf266; RV64IF-NEXT: fadd.s fa0, fs1, fa0267; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload268; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload269; RV64IF-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload270; RV64IF-NEXT: addi sp, sp, 16271; RV64IF-NEXT: ret272;273; RV64IZFINX-LABEL: sincos_f32:274; RV64IZFINX: # %bb.0:275; RV64IZFINX-NEXT: addi sp, sp, -32276; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill277; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill278; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill279; RV64IZFINX-NEXT: mv s0, a0280; RV64IZFINX-NEXT: call sinf281; RV64IZFINX-NEXT: mv s1, a0282; RV64IZFINX-NEXT: mv a0, s0283; RV64IZFINX-NEXT: call cosf284; RV64IZFINX-NEXT: fadd.s a0, s1, a0285; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload286; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload287; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload288; RV64IZFINX-NEXT: addi sp, sp, 32289; RV64IZFINX-NEXT: ret290;291; RV64IFD-LABEL: sincos_f32:292; RV64IFD: # %bb.0:293; RV64IFD-NEXT: addi sp, sp, -32294; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill295; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill296; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill297; RV64IFD-NEXT: fmv.s fs0, fa0298; RV64IFD-NEXT: call sinf299; RV64IFD-NEXT: fmv.s fs1, fa0300; RV64IFD-NEXT: fmv.s fa0, fs0301; RV64IFD-NEXT: call cosf302; RV64IFD-NEXT: fadd.s fa0, fs1, fa0303; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload304; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload305; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload306; RV64IFD-NEXT: addi sp, sp, 32307; RV64IFD-NEXT: ret308;309; RV32I-LABEL: sincos_f32:310; RV32I: # %bb.0:311; RV32I-NEXT: addi sp, sp, -16312; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill313; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill314; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill315; RV32I-NEXT: mv s0, a0316; RV32I-NEXT: call sinf317; RV32I-NEXT: mv s1, a0318; RV32I-NEXT: mv a0, s0319; RV32I-NEXT: call cosf320; RV32I-NEXT: mv a1, a0321; RV32I-NEXT: mv a0, s1322; RV32I-NEXT: call __addsf3323; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload324; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload325; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload326; RV32I-NEXT: addi sp, sp, 16327; RV32I-NEXT: ret328;329; RV64I-LABEL: sincos_f32:330; RV64I: # %bb.0:331; RV64I-NEXT: addi sp, sp, -32332; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill333; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill334; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill335; RV64I-NEXT: mv s0, a0336; RV64I-NEXT: call sinf337; RV64I-NEXT: mv s1, a0338; RV64I-NEXT: mv a0, s0339; RV64I-NEXT: call cosf340; RV64I-NEXT: mv a1, a0341; RV64I-NEXT: mv a0, s1342; RV64I-NEXT: call __addsf3343; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload344; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload345; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload346; RV64I-NEXT: addi sp, sp, 32347; RV64I-NEXT: ret348 %1 = call float @llvm.sin.f32(float %a)349 %2 = call float @llvm.cos.f32(float %a)350 %3 = fadd float %1, %2351 ret float %3352}353 354define float @pow_f32(float %a, float %b) nounwind {355; RV32IF-LABEL: pow_f32:356; RV32IF: # %bb.0:357; RV32IF-NEXT: tail powf358;359; RV32IZFINX-LABEL: pow_f32:360; RV32IZFINX: # %bb.0:361; RV32IZFINX-NEXT: tail powf362;363; RV64IF-LABEL: pow_f32:364; RV64IF: # %bb.0:365; RV64IF-NEXT: tail powf366;367; RV64IZFINX-LABEL: pow_f32:368; RV64IZFINX: # %bb.0:369; RV64IZFINX-NEXT: tail powf370;371; RV64IFD-LABEL: pow_f32:372; RV64IFD: # %bb.0:373; RV64IFD-NEXT: tail powf374;375; RV32I-LABEL: pow_f32:376; RV32I: # %bb.0:377; RV32I-NEXT: addi sp, sp, -16378; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill379; RV32I-NEXT: call powf380; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload381; RV32I-NEXT: addi sp, sp, 16382; RV32I-NEXT: ret383;384; RV64I-LABEL: pow_f32:385; RV64I: # %bb.0:386; RV64I-NEXT: addi sp, sp, -16387; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill388; RV64I-NEXT: call powf389; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload390; RV64I-NEXT: addi sp, sp, 16391; RV64I-NEXT: ret392 %1 = call float @llvm.pow.f32(float %a, float %b)393 ret float %1394}395 396define float @exp_f32(float %a) nounwind {397; RV32IF-LABEL: exp_f32:398; RV32IF: # %bb.0:399; RV32IF-NEXT: tail expf400;401; RV32IZFINX-LABEL: exp_f32:402; RV32IZFINX: # %bb.0:403; RV32IZFINX-NEXT: tail expf404;405; RV64IF-LABEL: exp_f32:406; RV64IF: # %bb.0:407; RV64IF-NEXT: tail expf408;409; RV64IZFINX-LABEL: exp_f32:410; RV64IZFINX: # %bb.0:411; RV64IZFINX-NEXT: tail expf412;413; RV64IFD-LABEL: exp_f32:414; RV64IFD: # %bb.0:415; RV64IFD-NEXT: tail expf416;417; RV32I-LABEL: exp_f32:418; RV32I: # %bb.0:419; RV32I-NEXT: addi sp, sp, -16420; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill421; RV32I-NEXT: call expf422; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload423; RV32I-NEXT: addi sp, sp, 16424; RV32I-NEXT: ret425;426; RV64I-LABEL: exp_f32:427; RV64I: # %bb.0:428; RV64I-NEXT: addi sp, sp, -16429; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill430; RV64I-NEXT: call expf431; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload432; RV64I-NEXT: addi sp, sp, 16433; RV64I-NEXT: ret434 %1 = call float @llvm.exp.f32(float %a)435 ret float %1436}437 438define float @exp2_f32(float %a) nounwind {439; RV32IF-LABEL: exp2_f32:440; RV32IF: # %bb.0:441; RV32IF-NEXT: tail exp2f442;443; RV32IZFINX-LABEL: exp2_f32:444; RV32IZFINX: # %bb.0:445; RV32IZFINX-NEXT: tail exp2f446;447; RV64IF-LABEL: exp2_f32:448; RV64IF: # %bb.0:449; RV64IF-NEXT: tail exp2f450;451; RV64IZFINX-LABEL: exp2_f32:452; RV64IZFINX: # %bb.0:453; RV64IZFINX-NEXT: tail exp2f454;455; RV64IFD-LABEL: exp2_f32:456; RV64IFD: # %bb.0:457; RV64IFD-NEXT: tail exp2f458;459; RV32I-LABEL: exp2_f32:460; RV32I: # %bb.0:461; RV32I-NEXT: addi sp, sp, -16462; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill463; RV32I-NEXT: call exp2f464; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload465; RV32I-NEXT: addi sp, sp, 16466; RV32I-NEXT: ret467;468; RV64I-LABEL: exp2_f32:469; RV64I: # %bb.0:470; RV64I-NEXT: addi sp, sp, -16471; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill472; RV64I-NEXT: call exp2f473; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload474; RV64I-NEXT: addi sp, sp, 16475; RV64I-NEXT: ret476 %1 = call float @llvm.exp2.f32(float %a)477 ret float %1478}479 480define float @exp10_f32(float %a) nounwind {481; RV32IF-LABEL: exp10_f32:482; RV32IF: # %bb.0:483; RV32IF-NEXT: tail exp10f484;485; RV32IZFINX-LABEL: exp10_f32:486; RV32IZFINX: # %bb.0:487; RV32IZFINX-NEXT: tail exp10f488;489; RV64IF-LABEL: exp10_f32:490; RV64IF: # %bb.0:491; RV64IF-NEXT: tail exp10f492;493; RV64IZFINX-LABEL: exp10_f32:494; RV64IZFINX: # %bb.0:495; RV64IZFINX-NEXT: tail exp10f496;497; RV64IFD-LABEL: exp10_f32:498; RV64IFD: # %bb.0:499; RV64IFD-NEXT: tail exp10f500;501; RV32I-LABEL: exp10_f32:502; RV32I: # %bb.0:503; RV32I-NEXT: addi sp, sp, -16504; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill505; RV32I-NEXT: call exp10f506; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload507; RV32I-NEXT: addi sp, sp, 16508; RV32I-NEXT: ret509;510; RV64I-LABEL: exp10_f32:511; RV64I: # %bb.0:512; RV64I-NEXT: addi sp, sp, -16513; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill514; RV64I-NEXT: call exp10f515; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload516; RV64I-NEXT: addi sp, sp, 16517; RV64I-NEXT: ret518 %1 = call float @llvm.exp10.f32(float %a)519 ret float %1520}521 522define float @log_f32(float %a) nounwind {523; RV32IF-LABEL: log_f32:524; RV32IF: # %bb.0:525; RV32IF-NEXT: tail logf526;527; RV32IZFINX-LABEL: log_f32:528; RV32IZFINX: # %bb.0:529; RV32IZFINX-NEXT: tail logf530;531; RV64IF-LABEL: log_f32:532; RV64IF: # %bb.0:533; RV64IF-NEXT: tail logf534;535; RV64IZFINX-LABEL: log_f32:536; RV64IZFINX: # %bb.0:537; RV64IZFINX-NEXT: tail logf538;539; RV64IFD-LABEL: log_f32:540; RV64IFD: # %bb.0:541; RV64IFD-NEXT: tail logf542;543; RV32I-LABEL: log_f32:544; RV32I: # %bb.0:545; RV32I-NEXT: addi sp, sp, -16546; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill547; RV32I-NEXT: call logf548; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload549; RV32I-NEXT: addi sp, sp, 16550; RV32I-NEXT: ret551;552; RV64I-LABEL: log_f32:553; RV64I: # %bb.0:554; RV64I-NEXT: addi sp, sp, -16555; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill556; RV64I-NEXT: call logf557; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload558; RV64I-NEXT: addi sp, sp, 16559; RV64I-NEXT: ret560 %1 = call float @llvm.log.f32(float %a)561 ret float %1562}563 564define float @log10_f32(float %a) nounwind {565; RV32IF-LABEL: log10_f32:566; RV32IF: # %bb.0:567; RV32IF-NEXT: tail log10f568;569; RV32IZFINX-LABEL: log10_f32:570; RV32IZFINX: # %bb.0:571; RV32IZFINX-NEXT: tail log10f572;573; RV64IF-LABEL: log10_f32:574; RV64IF: # %bb.0:575; RV64IF-NEXT: tail log10f576;577; RV64IZFINX-LABEL: log10_f32:578; RV64IZFINX: # %bb.0:579; RV64IZFINX-NEXT: tail log10f580;581; RV64IFD-LABEL: log10_f32:582; RV64IFD: # %bb.0:583; RV64IFD-NEXT: tail log10f584;585; RV32I-LABEL: log10_f32:586; RV32I: # %bb.0:587; RV32I-NEXT: addi sp, sp, -16588; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill589; RV32I-NEXT: call log10f590; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload591; RV32I-NEXT: addi sp, sp, 16592; RV32I-NEXT: ret593;594; RV64I-LABEL: log10_f32:595; RV64I: # %bb.0:596; RV64I-NEXT: addi sp, sp, -16597; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill598; RV64I-NEXT: call log10f599; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload600; RV64I-NEXT: addi sp, sp, 16601; RV64I-NEXT: ret602 %1 = call float @llvm.log10.f32(float %a)603 ret float %1604}605 606define float @log2_f32(float %a) nounwind {607; RV32IF-LABEL: log2_f32:608; RV32IF: # %bb.0:609; RV32IF-NEXT: tail log2f610;611; RV32IZFINX-LABEL: log2_f32:612; RV32IZFINX: # %bb.0:613; RV32IZFINX-NEXT: tail log2f614;615; RV64IF-LABEL: log2_f32:616; RV64IF: # %bb.0:617; RV64IF-NEXT: tail log2f618;619; RV64IZFINX-LABEL: log2_f32:620; RV64IZFINX: # %bb.0:621; RV64IZFINX-NEXT: tail log2f622;623; RV64IFD-LABEL: log2_f32:624; RV64IFD: # %bb.0:625; RV64IFD-NEXT: tail log2f626;627; RV32I-LABEL: log2_f32:628; RV32I: # %bb.0:629; RV32I-NEXT: addi sp, sp, -16630; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill631; RV32I-NEXT: call log2f632; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload633; RV32I-NEXT: addi sp, sp, 16634; RV32I-NEXT: ret635;636; RV64I-LABEL: log2_f32:637; RV64I: # %bb.0:638; RV64I-NEXT: addi sp, sp, -16639; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill640; RV64I-NEXT: call log2f641; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload642; RV64I-NEXT: addi sp, sp, 16643; RV64I-NEXT: ret644 %1 = call float @llvm.log2.f32(float %a)645 ret float %1646}647 648define float @fma_f32(float %a, float %b, float %c) nounwind {649; RV32IF-LABEL: fma_f32:650; RV32IF: # %bb.0:651; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2652; RV32IF-NEXT: ret653;654; RV32IZFINX-LABEL: fma_f32:655; RV32IZFINX: # %bb.0:656; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2657; RV32IZFINX-NEXT: ret658;659; RV64IF-LABEL: fma_f32:660; RV64IF: # %bb.0:661; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2662; RV64IF-NEXT: ret663;664; RV64IZFINX-LABEL: fma_f32:665; RV64IZFINX: # %bb.0:666; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2667; RV64IZFINX-NEXT: ret668;669; RV64IFD-LABEL: fma_f32:670; RV64IFD: # %bb.0:671; RV64IFD-NEXT: fmadd.s fa0, fa0, fa1, fa2672; RV64IFD-NEXT: ret673;674; RV32I-LABEL: fma_f32:675; RV32I: # %bb.0:676; RV32I-NEXT: addi sp, sp, -16677; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill678; RV32I-NEXT: call fmaf679; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload680; RV32I-NEXT: addi sp, sp, 16681; RV32I-NEXT: ret682;683; RV64I-LABEL: fma_f32:684; RV64I: # %bb.0:685; RV64I-NEXT: addi sp, sp, -16686; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill687; RV64I-NEXT: call fmaf688; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload689; RV64I-NEXT: addi sp, sp, 16690; RV64I-NEXT: ret691 %1 = call float @llvm.fma.f32(float %a, float %b, float %c)692 ret float %1693}694 695define float @fmuladd_f32(float %a, float %b, float %c) nounwind {696; RV32IF-LABEL: fmuladd_f32:697; RV32IF: # %bb.0:698; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2699; RV32IF-NEXT: ret700;701; RV32IZFINX-LABEL: fmuladd_f32:702; RV32IZFINX: # %bb.0:703; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2704; RV32IZFINX-NEXT: ret705;706; RV64IF-LABEL: fmuladd_f32:707; RV64IF: # %bb.0:708; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2709; RV64IF-NEXT: ret710;711; RV64IZFINX-LABEL: fmuladd_f32:712; RV64IZFINX: # %bb.0:713; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2714; RV64IZFINX-NEXT: ret715;716; RV64IFD-LABEL: fmuladd_f32:717; RV64IFD: # %bb.0:718; RV64IFD-NEXT: fmadd.s fa0, fa0, fa1, fa2719; RV64IFD-NEXT: ret720;721; RV32I-LABEL: fmuladd_f32:722; RV32I: # %bb.0:723; RV32I-NEXT: addi sp, sp, -16724; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill725; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill726; RV32I-NEXT: mv s0, a2727; RV32I-NEXT: call __mulsf3728; RV32I-NEXT: mv a1, s0729; RV32I-NEXT: call __addsf3730; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload731; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload732; RV32I-NEXT: addi sp, sp, 16733; RV32I-NEXT: ret734;735; RV64I-LABEL: fmuladd_f32:736; RV64I: # %bb.0:737; RV64I-NEXT: addi sp, sp, -16738; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill739; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill740; RV64I-NEXT: mv s0, a2741; RV64I-NEXT: call __mulsf3742; RV64I-NEXT: mv a1, s0743; RV64I-NEXT: call __addsf3744; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload745; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload746; RV64I-NEXT: addi sp, sp, 16747; RV64I-NEXT: ret748 %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)749 ret float %1750}751 752define float @fabs_f32(float %a) nounwind {753; RV32IF-LABEL: fabs_f32:754; RV32IF: # %bb.0:755; RV32IF-NEXT: fabs.s fa0, fa0756; RV32IF-NEXT: ret757;758; RV32IZFINX-LABEL: fabs_f32:759; RV32IZFINX: # %bb.0:760; RV32IZFINX-NEXT: fabs.s a0, a0761; RV32IZFINX-NEXT: ret762;763; RV64IF-LABEL: fabs_f32:764; RV64IF: # %bb.0:765; RV64IF-NEXT: fabs.s fa0, fa0766; RV64IF-NEXT: ret767;768; RV64IZFINX-LABEL: fabs_f32:769; RV64IZFINX: # %bb.0:770; RV64IZFINX-NEXT: fabs.s a0, a0771; RV64IZFINX-NEXT: ret772;773; RV64IFD-LABEL: fabs_f32:774; RV64IFD: # %bb.0:775; RV64IFD-NEXT: fabs.s fa0, fa0776; RV64IFD-NEXT: ret777;778; RV32I-LABEL: fabs_f32:779; RV32I: # %bb.0:780; RV32I-NEXT: slli a0, a0, 1781; RV32I-NEXT: srli a0, a0, 1782; RV32I-NEXT: ret783;784; RV64I-LABEL: fabs_f32:785; RV64I: # %bb.0:786; RV64I-NEXT: slli a0, a0, 33787; RV64I-NEXT: srli a0, a0, 33788; RV64I-NEXT: ret789 %1 = call float @llvm.fabs.f32(float %a)790 ret float %1791}792 793define float @minnum_f32(float %a, float %b) nounwind {794; RV32IF-LABEL: minnum_f32:795; RV32IF: # %bb.0:796; RV32IF-NEXT: fmin.s fa0, fa0, fa1797; RV32IF-NEXT: ret798;799; RV32IZFINX-LABEL: minnum_f32:800; RV32IZFINX: # %bb.0:801; RV32IZFINX-NEXT: fmin.s a0, a0, a1802; RV32IZFINX-NEXT: ret803;804; RV64IF-LABEL: minnum_f32:805; RV64IF: # %bb.0:806; RV64IF-NEXT: fmin.s fa0, fa0, fa1807; RV64IF-NEXT: ret808;809; RV64IZFINX-LABEL: minnum_f32:810; RV64IZFINX: # %bb.0:811; RV64IZFINX-NEXT: fmin.s a0, a0, a1812; RV64IZFINX-NEXT: ret813;814; RV64IFD-LABEL: minnum_f32:815; RV64IFD: # %bb.0:816; RV64IFD-NEXT: fmin.s fa0, fa0, fa1817; RV64IFD-NEXT: ret818;819; RV32I-LABEL: minnum_f32:820; RV32I: # %bb.0:821; RV32I-NEXT: addi sp, sp, -16822; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill823; RV32I-NEXT: call fminf824; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload825; RV32I-NEXT: addi sp, sp, 16826; RV32I-NEXT: ret827;828; RV64I-LABEL: minnum_f32:829; RV64I: # %bb.0:830; RV64I-NEXT: addi sp, sp, -16831; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill832; RV64I-NEXT: call fminf833; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload834; RV64I-NEXT: addi sp, sp, 16835; RV64I-NEXT: ret836 %1 = call float @llvm.minnum.f32(float %a, float %b)837 ret float %1838}839 840define float @maxnum_f32(float %a, float %b) nounwind {841; RV32IF-LABEL: maxnum_f32:842; RV32IF: # %bb.0:843; RV32IF-NEXT: fmax.s fa0, fa0, fa1844; RV32IF-NEXT: ret845;846; RV32IZFINX-LABEL: maxnum_f32:847; RV32IZFINX: # %bb.0:848; RV32IZFINX-NEXT: fmax.s a0, a0, a1849; RV32IZFINX-NEXT: ret850;851; RV64IF-LABEL: maxnum_f32:852; RV64IF: # %bb.0:853; RV64IF-NEXT: fmax.s fa0, fa0, fa1854; RV64IF-NEXT: ret855;856; RV64IZFINX-LABEL: maxnum_f32:857; RV64IZFINX: # %bb.0:858; RV64IZFINX-NEXT: fmax.s a0, a0, a1859; RV64IZFINX-NEXT: ret860;861; RV64IFD-LABEL: maxnum_f32:862; RV64IFD: # %bb.0:863; RV64IFD-NEXT: fmax.s fa0, fa0, fa1864; RV64IFD-NEXT: ret865;866; RV32I-LABEL: maxnum_f32:867; RV32I: # %bb.0:868; RV32I-NEXT: addi sp, sp, -16869; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill870; RV32I-NEXT: call fmaxf871; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload872; RV32I-NEXT: addi sp, sp, 16873; RV32I-NEXT: ret874;875; RV64I-LABEL: maxnum_f32:876; RV64I: # %bb.0:877; RV64I-NEXT: addi sp, sp, -16878; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill879; RV64I-NEXT: call fmaxf880; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload881; RV64I-NEXT: addi sp, sp, 16882; RV64I-NEXT: ret883 %1 = call float @llvm.maxnum.f32(float %a, float %b)884 ret float %1885}886 887define float @copysign_f32(float %a, float %b) nounwind {888; RV32IF-LABEL: copysign_f32:889; RV32IF: # %bb.0:890; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1891; RV32IF-NEXT: ret892;893; RV32IZFINX-LABEL: copysign_f32:894; RV32IZFINX: # %bb.0:895; RV32IZFINX-NEXT: fsgnj.s a0, a0, a1896; RV32IZFINX-NEXT: ret897;898; RV64IF-LABEL: copysign_f32:899; RV64IF: # %bb.0:900; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1901; RV64IF-NEXT: ret902;903; RV64IZFINX-LABEL: copysign_f32:904; RV64IZFINX: # %bb.0:905; RV64IZFINX-NEXT: fsgnj.s a0, a0, a1906; RV64IZFINX-NEXT: ret907;908; RV64IFD-LABEL: copysign_f32:909; RV64IFD: # %bb.0:910; RV64IFD-NEXT: fsgnj.s fa0, fa0, fa1911; RV64IFD-NEXT: ret912;913; RV32I-LABEL: copysign_f32:914; RV32I: # %bb.0:915; RV32I-NEXT: lui a2, 524288916; RV32I-NEXT: slli a0, a0, 1917; RV32I-NEXT: and a1, a1, a2918; RV32I-NEXT: srli a0, a0, 1919; RV32I-NEXT: or a0, a0, a1920; RV32I-NEXT: ret921;922; RV64I-LABEL: copysign_f32:923; RV64I: # %bb.0:924; RV64I-NEXT: lui a2, 524288925; RV64I-NEXT: slli a0, a0, 33926; RV64I-NEXT: and a1, a1, a2927; RV64I-NEXT: srli a0, a0, 33928; RV64I-NEXT: or a0, a0, a1929; RV64I-NEXT: ret930 %1 = call float @llvm.copysign.f32(float %a, float %b)931 ret float %1932}933 934define float @floor_f32(float %a) nounwind {935; RV32IF-LABEL: floor_f32:936; RV32IF: # %bb.0:937; RV32IF-NEXT: lui a0, 307200938; RV32IF-NEXT: fmv.w.x fa5, a0939; RV32IF-NEXT: fabs.s fa4, fa0940; RV32IF-NEXT: flt.s a0, fa4, fa5941; RV32IF-NEXT: beqz a0, .LBB18_2942; RV32IF-NEXT: # %bb.1:943; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn944; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn945; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0946; RV32IF-NEXT: .LBB18_2:947; RV32IF-NEXT: ret948;949; RV32IZFINX-LABEL: floor_f32:950; RV32IZFINX: # %bb.0:951; RV32IZFINX-NEXT: lui a1, 307200952; RV32IZFINX-NEXT: fabs.s a2, a0953; RV32IZFINX-NEXT: flt.s a1, a2, a1954; RV32IZFINX-NEXT: beqz a1, .LBB18_2955; RV32IZFINX-NEXT: # %bb.1:956; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rdn957; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rdn958; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0959; RV32IZFINX-NEXT: .LBB18_2:960; RV32IZFINX-NEXT: ret961;962; RV64IF-LABEL: floor_f32:963; RV64IF: # %bb.0:964; RV64IF-NEXT: lui a0, 307200965; RV64IF-NEXT: fmv.w.x fa5, a0966; RV64IF-NEXT: fabs.s fa4, fa0967; RV64IF-NEXT: flt.s a0, fa4, fa5968; RV64IF-NEXT: beqz a0, .LBB18_2969; RV64IF-NEXT: # %bb.1:970; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn971; RV64IF-NEXT: fcvt.s.w fa5, a0, rdn972; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0973; RV64IF-NEXT: .LBB18_2:974; RV64IF-NEXT: ret975;976; RV64IZFINX-LABEL: floor_f32:977; RV64IZFINX: # %bb.0:978; RV64IZFINX-NEXT: lui a1, 307200979; RV64IZFINX-NEXT: fabs.s a2, a0980; RV64IZFINX-NEXT: flt.s a1, a2, a1981; RV64IZFINX-NEXT: beqz a1, .LBB18_2982; RV64IZFINX-NEXT: # %bb.1:983; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rdn984; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rdn985; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0986; RV64IZFINX-NEXT: .LBB18_2:987; RV64IZFINX-NEXT: ret988;989; RV64IFD-LABEL: floor_f32:990; RV64IFD: # %bb.0:991; RV64IFD-NEXT: lui a0, 307200992; RV64IFD-NEXT: fmv.w.x fa5, a0993; RV64IFD-NEXT: fabs.s fa4, fa0994; RV64IFD-NEXT: flt.s a0, fa4, fa5995; RV64IFD-NEXT: beqz a0, .LBB18_2996; RV64IFD-NEXT: # %bb.1:997; RV64IFD-NEXT: fcvt.w.s a0, fa0, rdn998; RV64IFD-NEXT: fcvt.s.w fa5, a0, rdn999; RV64IFD-NEXT: fsgnj.s fa0, fa5, fa01000; RV64IFD-NEXT: .LBB18_2:1001; RV64IFD-NEXT: ret1002;1003; RV32I-LABEL: floor_f32:1004; RV32I: # %bb.0:1005; RV32I-NEXT: addi sp, sp, -161006; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1007; RV32I-NEXT: call floorf1008; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1009; RV32I-NEXT: addi sp, sp, 161010; RV32I-NEXT: ret1011;1012; RV64I-LABEL: floor_f32:1013; RV64I: # %bb.0:1014; RV64I-NEXT: addi sp, sp, -161015; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1016; RV64I-NEXT: call floorf1017; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1018; RV64I-NEXT: addi sp, sp, 161019; RV64I-NEXT: ret1020 %1 = call float @llvm.floor.f32(float %a)1021 ret float %11022}1023 1024define float @ceil_f32(float %a) nounwind {1025; RV32IF-LABEL: ceil_f32:1026; RV32IF: # %bb.0:1027; RV32IF-NEXT: lui a0, 3072001028; RV32IF-NEXT: fmv.w.x fa5, a01029; RV32IF-NEXT: fabs.s fa4, fa01030; RV32IF-NEXT: flt.s a0, fa4, fa51031; RV32IF-NEXT: beqz a0, .LBB19_21032; RV32IF-NEXT: # %bb.1:1033; RV32IF-NEXT: fcvt.w.s a0, fa0, rup1034; RV32IF-NEXT: fcvt.s.w fa5, a0, rup1035; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01036; RV32IF-NEXT: .LBB19_2:1037; RV32IF-NEXT: ret1038;1039; RV32IZFINX-LABEL: ceil_f32:1040; RV32IZFINX: # %bb.0:1041; RV32IZFINX-NEXT: lui a1, 3072001042; RV32IZFINX-NEXT: fabs.s a2, a01043; RV32IZFINX-NEXT: flt.s a1, a2, a11044; RV32IZFINX-NEXT: beqz a1, .LBB19_21045; RV32IZFINX-NEXT: # %bb.1:1046; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rup1047; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rup1048; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01049; RV32IZFINX-NEXT: .LBB19_2:1050; RV32IZFINX-NEXT: ret1051;1052; RV64IF-LABEL: ceil_f32:1053; RV64IF: # %bb.0:1054; RV64IF-NEXT: lui a0, 3072001055; RV64IF-NEXT: fmv.w.x fa5, a01056; RV64IF-NEXT: fabs.s fa4, fa01057; RV64IF-NEXT: flt.s a0, fa4, fa51058; RV64IF-NEXT: beqz a0, .LBB19_21059; RV64IF-NEXT: # %bb.1:1060; RV64IF-NEXT: fcvt.w.s a0, fa0, rup1061; RV64IF-NEXT: fcvt.s.w fa5, a0, rup1062; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01063; RV64IF-NEXT: .LBB19_2:1064; RV64IF-NEXT: ret1065;1066; RV64IZFINX-LABEL: ceil_f32:1067; RV64IZFINX: # %bb.0:1068; RV64IZFINX-NEXT: lui a1, 3072001069; RV64IZFINX-NEXT: fabs.s a2, a01070; RV64IZFINX-NEXT: flt.s a1, a2, a11071; RV64IZFINX-NEXT: beqz a1, .LBB19_21072; RV64IZFINX-NEXT: # %bb.1:1073; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rup1074; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rup1075; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01076; RV64IZFINX-NEXT: .LBB19_2:1077; RV64IZFINX-NEXT: ret1078;1079; RV64IFD-LABEL: ceil_f32:1080; RV64IFD: # %bb.0:1081; RV64IFD-NEXT: lui a0, 3072001082; RV64IFD-NEXT: fmv.w.x fa5, a01083; RV64IFD-NEXT: fabs.s fa4, fa01084; RV64IFD-NEXT: flt.s a0, fa4, fa51085; RV64IFD-NEXT: beqz a0, .LBB19_21086; RV64IFD-NEXT: # %bb.1:1087; RV64IFD-NEXT: fcvt.w.s a0, fa0, rup1088; RV64IFD-NEXT: fcvt.s.w fa5, a0, rup1089; RV64IFD-NEXT: fsgnj.s fa0, fa5, fa01090; RV64IFD-NEXT: .LBB19_2:1091; RV64IFD-NEXT: ret1092;1093; RV32I-LABEL: ceil_f32:1094; RV32I: # %bb.0:1095; RV32I-NEXT: addi sp, sp, -161096; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1097; RV32I-NEXT: call ceilf1098; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1099; RV32I-NEXT: addi sp, sp, 161100; RV32I-NEXT: ret1101;1102; RV64I-LABEL: ceil_f32:1103; RV64I: # %bb.0:1104; RV64I-NEXT: addi sp, sp, -161105; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1106; RV64I-NEXT: call ceilf1107; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1108; RV64I-NEXT: addi sp, sp, 161109; RV64I-NEXT: ret1110 %1 = call float @llvm.ceil.f32(float %a)1111 ret float %11112}1113 1114define float @trunc_f32(float %a) nounwind {1115; RV32IF-LABEL: trunc_f32:1116; RV32IF: # %bb.0:1117; RV32IF-NEXT: lui a0, 3072001118; RV32IF-NEXT: fmv.w.x fa5, a01119; RV32IF-NEXT: fabs.s fa4, fa01120; RV32IF-NEXT: flt.s a0, fa4, fa51121; RV32IF-NEXT: beqz a0, .LBB20_21122; RV32IF-NEXT: # %bb.1:1123; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz1124; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz1125; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01126; RV32IF-NEXT: .LBB20_2:1127; RV32IF-NEXT: ret1128;1129; RV32IZFINX-LABEL: trunc_f32:1130; RV32IZFINX: # %bb.0:1131; RV32IZFINX-NEXT: lui a1, 3072001132; RV32IZFINX-NEXT: fabs.s a2, a01133; RV32IZFINX-NEXT: flt.s a1, a2, a11134; RV32IZFINX-NEXT: beqz a1, .LBB20_21135; RV32IZFINX-NEXT: # %bb.1:1136; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rtz1137; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rtz1138; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01139; RV32IZFINX-NEXT: .LBB20_2:1140; RV32IZFINX-NEXT: ret1141;1142; RV64IF-LABEL: trunc_f32:1143; RV64IF: # %bb.0:1144; RV64IF-NEXT: lui a0, 3072001145; RV64IF-NEXT: fmv.w.x fa5, a01146; RV64IF-NEXT: fabs.s fa4, fa01147; RV64IF-NEXT: flt.s a0, fa4, fa51148; RV64IF-NEXT: beqz a0, .LBB20_21149; RV64IF-NEXT: # %bb.1:1150; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz1151; RV64IF-NEXT: fcvt.s.w fa5, a0, rtz1152; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01153; RV64IF-NEXT: .LBB20_2:1154; RV64IF-NEXT: ret1155;1156; RV64IZFINX-LABEL: trunc_f32:1157; RV64IZFINX: # %bb.0:1158; RV64IZFINX-NEXT: lui a1, 3072001159; RV64IZFINX-NEXT: fabs.s a2, a01160; RV64IZFINX-NEXT: flt.s a1, a2, a11161; RV64IZFINX-NEXT: beqz a1, .LBB20_21162; RV64IZFINX-NEXT: # %bb.1:1163; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rtz1164; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rtz1165; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01166; RV64IZFINX-NEXT: .LBB20_2:1167; RV64IZFINX-NEXT: ret1168;1169; RV64IFD-LABEL: trunc_f32:1170; RV64IFD: # %bb.0:1171; RV64IFD-NEXT: lui a0, 3072001172; RV64IFD-NEXT: fmv.w.x fa5, a01173; RV64IFD-NEXT: fabs.s fa4, fa01174; RV64IFD-NEXT: flt.s a0, fa4, fa51175; RV64IFD-NEXT: beqz a0, .LBB20_21176; RV64IFD-NEXT: # %bb.1:1177; RV64IFD-NEXT: fcvt.w.s a0, fa0, rtz1178; RV64IFD-NEXT: fcvt.s.w fa5, a0, rtz1179; RV64IFD-NEXT: fsgnj.s fa0, fa5, fa01180; RV64IFD-NEXT: .LBB20_2:1181; RV64IFD-NEXT: ret1182;1183; RV32I-LABEL: trunc_f32:1184; RV32I: # %bb.0:1185; RV32I-NEXT: addi sp, sp, -161186; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1187; RV32I-NEXT: call truncf1188; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1189; RV32I-NEXT: addi sp, sp, 161190; RV32I-NEXT: ret1191;1192; RV64I-LABEL: trunc_f32:1193; RV64I: # %bb.0:1194; RV64I-NEXT: addi sp, sp, -161195; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1196; RV64I-NEXT: call truncf1197; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1198; RV64I-NEXT: addi sp, sp, 161199; RV64I-NEXT: ret1200 %1 = call float @llvm.trunc.f32(float %a)1201 ret float %11202}1203 1204define float @rint_f32(float %a) nounwind {1205; RV32IF-LABEL: rint_f32:1206; RV32IF: # %bb.0:1207; RV32IF-NEXT: lui a0, 3072001208; RV32IF-NEXT: fmv.w.x fa5, a01209; RV32IF-NEXT: fabs.s fa4, fa01210; RV32IF-NEXT: flt.s a0, fa4, fa51211; RV32IF-NEXT: beqz a0, .LBB21_21212; RV32IF-NEXT: # %bb.1:1213; RV32IF-NEXT: fcvt.w.s a0, fa01214; RV32IF-NEXT: fcvt.s.w fa5, a01215; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01216; RV32IF-NEXT: .LBB21_2:1217; RV32IF-NEXT: ret1218;1219; RV32IZFINX-LABEL: rint_f32:1220; RV32IZFINX: # %bb.0:1221; RV32IZFINX-NEXT: lui a1, 3072001222; RV32IZFINX-NEXT: fabs.s a2, a01223; RV32IZFINX-NEXT: flt.s a1, a2, a11224; RV32IZFINX-NEXT: beqz a1, .LBB21_21225; RV32IZFINX-NEXT: # %bb.1:1226; RV32IZFINX-NEXT: fcvt.w.s a1, a01227; RV32IZFINX-NEXT: fcvt.s.w a1, a11228; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01229; RV32IZFINX-NEXT: .LBB21_2:1230; RV32IZFINX-NEXT: ret1231;1232; RV64IF-LABEL: rint_f32:1233; RV64IF: # %bb.0:1234; RV64IF-NEXT: lui a0, 3072001235; RV64IF-NEXT: fmv.w.x fa5, a01236; RV64IF-NEXT: fabs.s fa4, fa01237; RV64IF-NEXT: flt.s a0, fa4, fa51238; RV64IF-NEXT: beqz a0, .LBB21_21239; RV64IF-NEXT: # %bb.1:1240; RV64IF-NEXT: fcvt.w.s a0, fa01241; RV64IF-NEXT: fcvt.s.w fa5, a01242; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01243; RV64IF-NEXT: .LBB21_2:1244; RV64IF-NEXT: ret1245;1246; RV64IZFINX-LABEL: rint_f32:1247; RV64IZFINX: # %bb.0:1248; RV64IZFINX-NEXT: lui a1, 3072001249; RV64IZFINX-NEXT: fabs.s a2, a01250; RV64IZFINX-NEXT: flt.s a1, a2, a11251; RV64IZFINX-NEXT: beqz a1, .LBB21_21252; RV64IZFINX-NEXT: # %bb.1:1253; RV64IZFINX-NEXT: fcvt.w.s a1, a01254; RV64IZFINX-NEXT: fcvt.s.w a1, a11255; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01256; RV64IZFINX-NEXT: .LBB21_2:1257; RV64IZFINX-NEXT: ret1258;1259; RV64IFD-LABEL: rint_f32:1260; RV64IFD: # %bb.0:1261; RV64IFD-NEXT: lui a0, 3072001262; RV64IFD-NEXT: fmv.w.x fa5, a01263; RV64IFD-NEXT: fabs.s fa4, fa01264; RV64IFD-NEXT: flt.s a0, fa4, fa51265; RV64IFD-NEXT: beqz a0, .LBB21_21266; RV64IFD-NEXT: # %bb.1:1267; RV64IFD-NEXT: fcvt.w.s a0, fa01268; RV64IFD-NEXT: fcvt.s.w fa5, a01269; RV64IFD-NEXT: fsgnj.s fa0, fa5, fa01270; RV64IFD-NEXT: .LBB21_2:1271; RV64IFD-NEXT: ret1272;1273; RV32I-LABEL: rint_f32:1274; RV32I: # %bb.0:1275; RV32I-NEXT: addi sp, sp, -161276; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1277; RV32I-NEXT: call rintf1278; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1279; RV32I-NEXT: addi sp, sp, 161280; RV32I-NEXT: ret1281;1282; RV64I-LABEL: rint_f32:1283; RV64I: # %bb.0:1284; RV64I-NEXT: addi sp, sp, -161285; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1286; RV64I-NEXT: call rintf1287; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1288; RV64I-NEXT: addi sp, sp, 161289; RV64I-NEXT: ret1290 %1 = call float @llvm.rint.f32(float %a)1291 ret float %11292}1293 1294define float @nearbyint_f32(float %a) nounwind {1295; RV32IF-LABEL: nearbyint_f32:1296; RV32IF: # %bb.0:1297; RV32IF-NEXT: tail nearbyintf1298;1299; RV32IZFINX-LABEL: nearbyint_f32:1300; RV32IZFINX: # %bb.0:1301; RV32IZFINX-NEXT: tail nearbyintf1302;1303; RV64IF-LABEL: nearbyint_f32:1304; RV64IF: # %bb.0:1305; RV64IF-NEXT: tail nearbyintf1306;1307; RV64IZFINX-LABEL: nearbyint_f32:1308; RV64IZFINX: # %bb.0:1309; RV64IZFINX-NEXT: tail nearbyintf1310;1311; RV64IFD-LABEL: nearbyint_f32:1312; RV64IFD: # %bb.0:1313; RV64IFD-NEXT: tail nearbyintf1314;1315; RV32I-LABEL: nearbyint_f32:1316; RV32I: # %bb.0:1317; RV32I-NEXT: addi sp, sp, -161318; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1319; RV32I-NEXT: call nearbyintf1320; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1321; RV32I-NEXT: addi sp, sp, 161322; RV32I-NEXT: ret1323;1324; RV64I-LABEL: nearbyint_f32:1325; RV64I: # %bb.0:1326; RV64I-NEXT: addi sp, sp, -161327; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1328; RV64I-NEXT: call nearbyintf1329; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1330; RV64I-NEXT: addi sp, sp, 161331; RV64I-NEXT: ret1332 %1 = call float @llvm.nearbyint.f32(float %a)1333 ret float %11334}1335 1336define float @round_f32(float %a) nounwind {1337; RV32IF-LABEL: round_f32:1338; RV32IF: # %bb.0:1339; RV32IF-NEXT: lui a0, 3072001340; RV32IF-NEXT: fmv.w.x fa5, a01341; RV32IF-NEXT: fabs.s fa4, fa01342; RV32IF-NEXT: flt.s a0, fa4, fa51343; RV32IF-NEXT: beqz a0, .LBB23_21344; RV32IF-NEXT: # %bb.1:1345; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm1346; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm1347; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01348; RV32IF-NEXT: .LBB23_2:1349; RV32IF-NEXT: ret1350;1351; RV32IZFINX-LABEL: round_f32:1352; RV32IZFINX: # %bb.0:1353; RV32IZFINX-NEXT: lui a1, 3072001354; RV32IZFINX-NEXT: fabs.s a2, a01355; RV32IZFINX-NEXT: flt.s a1, a2, a11356; RV32IZFINX-NEXT: beqz a1, .LBB23_21357; RV32IZFINX-NEXT: # %bb.1:1358; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rmm1359; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rmm1360; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01361; RV32IZFINX-NEXT: .LBB23_2:1362; RV32IZFINX-NEXT: ret1363;1364; RV64IF-LABEL: round_f32:1365; RV64IF: # %bb.0:1366; RV64IF-NEXT: lui a0, 3072001367; RV64IF-NEXT: fmv.w.x fa5, a01368; RV64IF-NEXT: fabs.s fa4, fa01369; RV64IF-NEXT: flt.s a0, fa4, fa51370; RV64IF-NEXT: beqz a0, .LBB23_21371; RV64IF-NEXT: # %bb.1:1372; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm1373; RV64IF-NEXT: fcvt.s.w fa5, a0, rmm1374; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01375; RV64IF-NEXT: .LBB23_2:1376; RV64IF-NEXT: ret1377;1378; RV64IZFINX-LABEL: round_f32:1379; RV64IZFINX: # %bb.0:1380; RV64IZFINX-NEXT: lui a1, 3072001381; RV64IZFINX-NEXT: fabs.s a2, a01382; RV64IZFINX-NEXT: flt.s a1, a2, a11383; RV64IZFINX-NEXT: beqz a1, .LBB23_21384; RV64IZFINX-NEXT: # %bb.1:1385; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rmm1386; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rmm1387; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01388; RV64IZFINX-NEXT: .LBB23_2:1389; RV64IZFINX-NEXT: ret1390;1391; RV64IFD-LABEL: round_f32:1392; RV64IFD: # %bb.0:1393; RV64IFD-NEXT: lui a0, 3072001394; RV64IFD-NEXT: fmv.w.x fa5, a01395; RV64IFD-NEXT: fabs.s fa4, fa01396; RV64IFD-NEXT: flt.s a0, fa4, fa51397; RV64IFD-NEXT: beqz a0, .LBB23_21398; RV64IFD-NEXT: # %bb.1:1399; RV64IFD-NEXT: fcvt.w.s a0, fa0, rmm1400; RV64IFD-NEXT: fcvt.s.w fa5, a0, rmm1401; RV64IFD-NEXT: fsgnj.s fa0, fa5, fa01402; RV64IFD-NEXT: .LBB23_2:1403; RV64IFD-NEXT: ret1404;1405; RV32I-LABEL: round_f32:1406; RV32I: # %bb.0:1407; RV32I-NEXT: addi sp, sp, -161408; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1409; RV32I-NEXT: call roundf1410; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1411; RV32I-NEXT: addi sp, sp, 161412; RV32I-NEXT: ret1413;1414; RV64I-LABEL: round_f32:1415; RV64I: # %bb.0:1416; RV64I-NEXT: addi sp, sp, -161417; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1418; RV64I-NEXT: call roundf1419; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1420; RV64I-NEXT: addi sp, sp, 161421; RV64I-NEXT: ret1422 %1 = call float @llvm.round.f32(float %a)1423 ret float %11424}1425 1426define float @roundeven_f32(float %a) nounwind {1427; RV32IF-LABEL: roundeven_f32:1428; RV32IF: # %bb.0:1429; RV32IF-NEXT: lui a0, 3072001430; RV32IF-NEXT: fmv.w.x fa5, a01431; RV32IF-NEXT: fabs.s fa4, fa01432; RV32IF-NEXT: flt.s a0, fa4, fa51433; RV32IF-NEXT: beqz a0, .LBB24_21434; RV32IF-NEXT: # %bb.1:1435; RV32IF-NEXT: fcvt.w.s a0, fa0, rne1436; RV32IF-NEXT: fcvt.s.w fa5, a0, rne1437; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01438; RV32IF-NEXT: .LBB24_2:1439; RV32IF-NEXT: ret1440;1441; RV32IZFINX-LABEL: roundeven_f32:1442; RV32IZFINX: # %bb.0:1443; RV32IZFINX-NEXT: lui a1, 3072001444; RV32IZFINX-NEXT: fabs.s a2, a01445; RV32IZFINX-NEXT: flt.s a1, a2, a11446; RV32IZFINX-NEXT: beqz a1, .LBB24_21447; RV32IZFINX-NEXT: # %bb.1:1448; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rne1449; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rne1450; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01451; RV32IZFINX-NEXT: .LBB24_2:1452; RV32IZFINX-NEXT: ret1453;1454; RV64IF-LABEL: roundeven_f32:1455; RV64IF: # %bb.0:1456; RV64IF-NEXT: lui a0, 3072001457; RV64IF-NEXT: fmv.w.x fa5, a01458; RV64IF-NEXT: fabs.s fa4, fa01459; RV64IF-NEXT: flt.s a0, fa4, fa51460; RV64IF-NEXT: beqz a0, .LBB24_21461; RV64IF-NEXT: # %bb.1:1462; RV64IF-NEXT: fcvt.w.s a0, fa0, rne1463; RV64IF-NEXT: fcvt.s.w fa5, a0, rne1464; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01465; RV64IF-NEXT: .LBB24_2:1466; RV64IF-NEXT: ret1467;1468; RV64IZFINX-LABEL: roundeven_f32:1469; RV64IZFINX: # %bb.0:1470; RV64IZFINX-NEXT: lui a1, 3072001471; RV64IZFINX-NEXT: fabs.s a2, a01472; RV64IZFINX-NEXT: flt.s a1, a2, a11473; RV64IZFINX-NEXT: beqz a1, .LBB24_21474; RV64IZFINX-NEXT: # %bb.1:1475; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rne1476; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rne1477; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01478; RV64IZFINX-NEXT: .LBB24_2:1479; RV64IZFINX-NEXT: ret1480;1481; RV64IFD-LABEL: roundeven_f32:1482; RV64IFD: # %bb.0:1483; RV64IFD-NEXT: lui a0, 3072001484; RV64IFD-NEXT: fmv.w.x fa5, a01485; RV64IFD-NEXT: fabs.s fa4, fa01486; RV64IFD-NEXT: flt.s a0, fa4, fa51487; RV64IFD-NEXT: beqz a0, .LBB24_21488; RV64IFD-NEXT: # %bb.1:1489; RV64IFD-NEXT: fcvt.w.s a0, fa0, rne1490; RV64IFD-NEXT: fcvt.s.w fa5, a0, rne1491; RV64IFD-NEXT: fsgnj.s fa0, fa5, fa01492; RV64IFD-NEXT: .LBB24_2:1493; RV64IFD-NEXT: ret1494;1495; RV32I-LABEL: roundeven_f32:1496; RV32I: # %bb.0:1497; RV32I-NEXT: addi sp, sp, -161498; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1499; RV32I-NEXT: call roundevenf1500; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1501; RV32I-NEXT: addi sp, sp, 161502; RV32I-NEXT: ret1503;1504; RV64I-LABEL: roundeven_f32:1505; RV64I: # %bb.0:1506; RV64I-NEXT: addi sp, sp, -161507; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1508; RV64I-NEXT: call roundevenf1509; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1510; RV64I-NEXT: addi sp, sp, 161511; RV64I-NEXT: ret1512 %1 = call float @llvm.roundeven.f32(float %a)1513 ret float %11514}1515 1516define iXLen @lrint_f32(float %a) nounwind {1517; RV32IF-LABEL: lrint_f32:1518; RV32IF: # %bb.0:1519; RV32IF-NEXT: fcvt.w.s a0, fa01520; RV32IF-NEXT: ret1521;1522; RV32IZFINX-LABEL: lrint_f32:1523; RV32IZFINX: # %bb.0:1524; RV32IZFINX-NEXT: fcvt.w.s a0, a01525; RV32IZFINX-NEXT: ret1526;1527; RV64IF-LABEL: lrint_f32:1528; RV64IF: # %bb.0:1529; RV64IF-NEXT: fcvt.l.s a0, fa01530; RV64IF-NEXT: ret1531;1532; RV64IZFINX-LABEL: lrint_f32:1533; RV64IZFINX: # %bb.0:1534; RV64IZFINX-NEXT: fcvt.l.s a0, a01535; RV64IZFINX-NEXT: ret1536;1537; RV64IFD-LABEL: lrint_f32:1538; RV64IFD: # %bb.0:1539; RV64IFD-NEXT: fcvt.l.s a0, fa01540; RV64IFD-NEXT: ret1541;1542; RV32I-LABEL: lrint_f32:1543; RV32I: # %bb.0:1544; RV32I-NEXT: addi sp, sp, -161545; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1546; RV32I-NEXT: call lrintf1547; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1548; RV32I-NEXT: addi sp, sp, 161549; RV32I-NEXT: ret1550;1551; RV64I-LABEL: lrint_f32:1552; RV64I: # %bb.0:1553; RV64I-NEXT: addi sp, sp, -161554; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1555; RV64I-NEXT: call lrintf1556; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1557; RV64I-NEXT: addi sp, sp, 161558; RV64I-NEXT: ret1559 %1 = call iXLen @llvm.lrint.iXLen.f32(float %a)1560 ret iXLen %11561}1562 1563define iXLen @lround_f32(float %a) nounwind {1564; RV32IF-LABEL: lround_f32:1565; RV32IF: # %bb.0:1566; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm1567; RV32IF-NEXT: ret1568;1569; RV32IZFINX-LABEL: lround_f32:1570; RV32IZFINX: # %bb.0:1571; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm1572; RV32IZFINX-NEXT: ret1573;1574; RV64IF-LABEL: lround_f32:1575; RV64IF: # %bb.0:1576; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm1577; RV64IF-NEXT: ret1578;1579; RV64IZFINX-LABEL: lround_f32:1580; RV64IZFINX: # %bb.0:1581; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm1582; RV64IZFINX-NEXT: ret1583;1584; RV64IFD-LABEL: lround_f32:1585; RV64IFD: # %bb.0:1586; RV64IFD-NEXT: fcvt.l.s a0, fa0, rmm1587; RV64IFD-NEXT: ret1588;1589; RV32I-LABEL: lround_f32:1590; RV32I: # %bb.0:1591; RV32I-NEXT: addi sp, sp, -161592; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1593; RV32I-NEXT: call lroundf1594; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1595; RV32I-NEXT: addi sp, sp, 161596; RV32I-NEXT: ret1597;1598; RV64I-LABEL: lround_f32:1599; RV64I: # %bb.0:1600; RV64I-NEXT: addi sp, sp, -161601; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1602; RV64I-NEXT: call lroundf1603; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1604; RV64I-NEXT: addi sp, sp, 161605; RV64I-NEXT: ret1606 %1 = call iXLen @llvm.lround.iXLen.f32(float %a)1607 ret iXLen %11608}1609 1610; We support i32 lround on RV64 even though long isn't 32 bits. This is needed1611; by flang.1612define i32 @lround_i32_f32(float %a) nounwind {1613; RV32IF-LABEL: lround_i32_f32:1614; RV32IF: # %bb.0:1615; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm1616; RV32IF-NEXT: ret1617;1618; RV32IZFINX-LABEL: lround_i32_f32:1619; RV32IZFINX: # %bb.0:1620; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm1621; RV32IZFINX-NEXT: ret1622;1623; RV64IF-LABEL: lround_i32_f32:1624; RV64IF: # %bb.0:1625; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm1626; RV64IF-NEXT: ret1627;1628; RV64IZFINX-LABEL: lround_i32_f32:1629; RV64IZFINX: # %bb.0:1630; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rmm1631; RV64IZFINX-NEXT: ret1632;1633; RV64IFD-LABEL: lround_i32_f32:1634; RV64IFD: # %bb.0:1635; RV64IFD-NEXT: fcvt.w.s a0, fa0, rmm1636; RV64IFD-NEXT: ret1637;1638; RV32I-LABEL: lround_i32_f32:1639; RV32I: # %bb.0:1640; RV32I-NEXT: addi sp, sp, -161641; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1642; RV32I-NEXT: call lroundf1643; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1644; RV32I-NEXT: addi sp, sp, 161645; RV32I-NEXT: ret1646;1647; RV64I-LABEL: lround_i32_f32:1648; RV64I: # %bb.0:1649; RV64I-NEXT: addi sp, sp, -161650; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1651; RV64I-NEXT: call lroundf1652; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1653; RV64I-NEXT: addi sp, sp, 161654; RV64I-NEXT: ret1655 %1 = call i32 @llvm.lround.i32.f32(float %a)1656 ret i32 %11657}1658 1659define i64 @llrint_f32(float %a) nounwind {1660; RV32IF-LABEL: llrint_f32:1661; RV32IF: # %bb.0:1662; RV32IF-NEXT: addi sp, sp, -161663; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1664; RV32IF-NEXT: call llrintf1665; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1666; RV32IF-NEXT: addi sp, sp, 161667; RV32IF-NEXT: ret1668;1669; RV32IZFINX-LABEL: llrint_f32:1670; RV32IZFINX: # %bb.0:1671; RV32IZFINX-NEXT: addi sp, sp, -161672; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1673; RV32IZFINX-NEXT: call llrintf1674; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1675; RV32IZFINX-NEXT: addi sp, sp, 161676; RV32IZFINX-NEXT: ret1677;1678; RV64IF-LABEL: llrint_f32:1679; RV64IF: # %bb.0:1680; RV64IF-NEXT: fcvt.l.s a0, fa01681; RV64IF-NEXT: ret1682;1683; RV64IZFINX-LABEL: llrint_f32:1684; RV64IZFINX: # %bb.0:1685; RV64IZFINX-NEXT: fcvt.l.s a0, a01686; RV64IZFINX-NEXT: ret1687;1688; RV64IFD-LABEL: llrint_f32:1689; RV64IFD: # %bb.0:1690; RV64IFD-NEXT: fcvt.l.s a0, fa01691; RV64IFD-NEXT: ret1692;1693; RV32I-LABEL: llrint_f32:1694; RV32I: # %bb.0:1695; RV32I-NEXT: addi sp, sp, -161696; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1697; RV32I-NEXT: call llrintf1698; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1699; RV32I-NEXT: addi sp, sp, 161700; RV32I-NEXT: ret1701;1702; RV64I-LABEL: llrint_f32:1703; RV64I: # %bb.0:1704; RV64I-NEXT: addi sp, sp, -161705; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1706; RV64I-NEXT: call llrintf1707; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1708; RV64I-NEXT: addi sp, sp, 161709; RV64I-NEXT: ret1710 %1 = call i64 @llvm.llrint.i64.f32(float %a)1711 ret i64 %11712}1713 1714define i64 @llround_f32(float %a) nounwind {1715; RV32IF-LABEL: llround_f32:1716; RV32IF: # %bb.0:1717; RV32IF-NEXT: addi sp, sp, -161718; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1719; RV32IF-NEXT: call llroundf1720; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1721; RV32IF-NEXT: addi sp, sp, 161722; RV32IF-NEXT: ret1723;1724; RV32IZFINX-LABEL: llround_f32:1725; RV32IZFINX: # %bb.0:1726; RV32IZFINX-NEXT: addi sp, sp, -161727; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1728; RV32IZFINX-NEXT: call llroundf1729; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1730; RV32IZFINX-NEXT: addi sp, sp, 161731; RV32IZFINX-NEXT: ret1732;1733; RV64IF-LABEL: llround_f32:1734; RV64IF: # %bb.0:1735; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm1736; RV64IF-NEXT: ret1737;1738; RV64IZFINX-LABEL: llround_f32:1739; RV64IZFINX: # %bb.0:1740; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm1741; RV64IZFINX-NEXT: ret1742;1743; RV64IFD-LABEL: llround_f32:1744; RV64IFD: # %bb.0:1745; RV64IFD-NEXT: fcvt.l.s a0, fa0, rmm1746; RV64IFD-NEXT: ret1747;1748; RV32I-LABEL: llround_f32:1749; RV32I: # %bb.0:1750; RV32I-NEXT: addi sp, sp, -161751; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1752; RV32I-NEXT: call llroundf1753; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1754; RV32I-NEXT: addi sp, sp, 161755; RV32I-NEXT: ret1756;1757; RV64I-LABEL: llround_f32:1758; RV64I: # %bb.0:1759; RV64I-NEXT: addi sp, sp, -161760; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1761; RV64I-NEXT: call llroundf1762; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1763; RV64I-NEXT: addi sp, sp, 161764; RV64I-NEXT: ret1765 %1 = call i64 @llvm.llround.i64.f32(float %a)1766 ret i64 %11767}1768 1769define i1 @fpclass(float %x) {1770; RV32IF-LABEL: fpclass:1771; RV32IF: # %bb.0:1772; RV32IF-NEXT: fclass.s a0, fa01773; RV32IF-NEXT: andi a0, a0, 9271774; RV32IF-NEXT: snez a0, a01775; RV32IF-NEXT: ret1776;1777; RV32IZFINX-LABEL: fpclass:1778; RV32IZFINX: # %bb.0:1779; RV32IZFINX-NEXT: fclass.s a0, a01780; RV32IZFINX-NEXT: andi a0, a0, 9271781; RV32IZFINX-NEXT: snez a0, a01782; RV32IZFINX-NEXT: ret1783;1784; RV64IF-LABEL: fpclass:1785; RV64IF: # %bb.0:1786; RV64IF-NEXT: fclass.s a0, fa01787; RV64IF-NEXT: andi a0, a0, 9271788; RV64IF-NEXT: snez a0, a01789; RV64IF-NEXT: ret1790;1791; RV64IZFINX-LABEL: fpclass:1792; RV64IZFINX: # %bb.0:1793; RV64IZFINX-NEXT: fclass.s a0, a01794; RV64IZFINX-NEXT: andi a0, a0, 9271795; RV64IZFINX-NEXT: snez a0, a01796; RV64IZFINX-NEXT: ret1797;1798; RV64IFD-LABEL: fpclass:1799; RV64IFD: # %bb.0:1800; RV64IFD-NEXT: fclass.s a0, fa01801; RV64IFD-NEXT: andi a0, a0, 9271802; RV64IFD-NEXT: snez a0, a01803; RV64IFD-NEXT: ret1804;1805; RV32I-LABEL: fpclass:1806; RV32I: # %bb.0:1807; RV32I-NEXT: slli a1, a0, 11808; RV32I-NEXT: lui a2, 20481809; RV32I-NEXT: lui a3, 5222401810; RV32I-NEXT: lui a4, 10465281811; RV32I-NEXT: srli a5, a1, 11812; RV32I-NEXT: addi a2, a2, -11813; RV32I-NEXT: xor a6, a5, a31814; RV32I-NEXT: slt a3, a3, a51815; RV32I-NEXT: add a4, a5, a41816; RV32I-NEXT: addi a5, a5, -11817; RV32I-NEXT: sltu a2, a5, a21818; RV32I-NEXT: srli a0, a0, 311819; RV32I-NEXT: seqz a1, a11820; RV32I-NEXT: seqz a5, a61821; RV32I-NEXT: srli a4, a4, 241822; RV32I-NEXT: and a2, a2, a01823; RV32I-NEXT: or a1, a1, a51824; RV32I-NEXT: sltiu a4, a4, 1271825; RV32I-NEXT: or a1, a1, a21826; RV32I-NEXT: or a1, a1, a31827; RV32I-NEXT: and a0, a4, a01828; RV32I-NEXT: or a0, a1, a01829; RV32I-NEXT: ret1830;1831; RV64I-LABEL: fpclass:1832; RV64I: # %bb.0:1833; RV64I-NEXT: slli a1, a0, 331834; RV64I-NEXT: lui a2, 20481835; RV64I-NEXT: lui a3, 5222401836; RV64I-NEXT: lui a4, 10465281837; RV64I-NEXT: srli a5, a1, 331838; RV64I-NEXT: addi a2, a2, -11839; RV64I-NEXT: xor a6, a5, a31840; RV64I-NEXT: slt a3, a3, a51841; RV64I-NEXT: add a4, a5, a41842; RV64I-NEXT: addi a5, a5, -11843; RV64I-NEXT: sltu a2, a5, a21844; RV64I-NEXT: srliw a0, a0, 311845; RV64I-NEXT: seqz a1, a11846; RV64I-NEXT: seqz a5, a61847; RV64I-NEXT: srliw a4, a4, 241848; RV64I-NEXT: and a2, a2, a01849; RV64I-NEXT: or a1, a1, a51850; RV64I-NEXT: sltiu a4, a4, 1271851; RV64I-NEXT: or a1, a1, a21852; RV64I-NEXT: or a1, a1, a31853; RV64I-NEXT: and a0, a4, a01854; RV64I-NEXT: or a0, a1, a01855; RV64I-NEXT: ret1856 %cmp = call i1 @llvm.is.fpclass.f32(float %x, i32 639)1857 ret i1 %cmp1858}1859 1860define i1 @isnan_fpclass(float %x) {1861; RV32IF-LABEL: isnan_fpclass:1862; RV32IF: # %bb.0:1863; RV32IF-NEXT: fclass.s a0, fa01864; RV32IF-NEXT: andi a0, a0, 7681865; RV32IF-NEXT: snez a0, a01866; RV32IF-NEXT: ret1867;1868; RV32IZFINX-LABEL: isnan_fpclass:1869; RV32IZFINX: # %bb.0:1870; RV32IZFINX-NEXT: fclass.s a0, a01871; RV32IZFINX-NEXT: andi a0, a0, 7681872; RV32IZFINX-NEXT: snez a0, a01873; RV32IZFINX-NEXT: ret1874;1875; RV64IF-LABEL: isnan_fpclass:1876; RV64IF: # %bb.0:1877; RV64IF-NEXT: fclass.s a0, fa01878; RV64IF-NEXT: andi a0, a0, 7681879; RV64IF-NEXT: snez a0, a01880; RV64IF-NEXT: ret1881;1882; RV64IZFINX-LABEL: isnan_fpclass:1883; RV64IZFINX: # %bb.0:1884; RV64IZFINX-NEXT: fclass.s a0, a01885; RV64IZFINX-NEXT: andi a0, a0, 7681886; RV64IZFINX-NEXT: snez a0, a01887; RV64IZFINX-NEXT: ret1888;1889; RV64IFD-LABEL: isnan_fpclass:1890; RV64IFD: # %bb.0:1891; RV64IFD-NEXT: fclass.s a0, fa01892; RV64IFD-NEXT: andi a0, a0, 7681893; RV64IFD-NEXT: snez a0, a01894; RV64IFD-NEXT: ret1895;1896; RV32I-LABEL: isnan_fpclass:1897; RV32I: # %bb.0:1898; RV32I-NEXT: slli a0, a0, 11899; RV32I-NEXT: srli a0, a0, 11900; RV32I-NEXT: lui a1, 5222401901; RV32I-NEXT: slt a0, a1, a01902; RV32I-NEXT: ret1903;1904; RV64I-LABEL: isnan_fpclass:1905; RV64I: # %bb.0:1906; RV64I-NEXT: slli a0, a0, 331907; RV64I-NEXT: srli a0, a0, 331908; RV64I-NEXT: lui a1, 5222401909; RV64I-NEXT: slt a0, a1, a01910; RV64I-NEXT: ret1911 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan1912 ret i1 %11913}1914 1915define i1 @isqnan_fpclass(float %x) {1916; RV32IF-LABEL: isqnan_fpclass:1917; RV32IF: # %bb.0:1918; RV32IF-NEXT: fclass.s a0, fa01919; RV32IF-NEXT: srli a0, a0, 91920; RV32IF-NEXT: ret1921;1922; RV32IZFINX-LABEL: isqnan_fpclass:1923; RV32IZFINX: # %bb.0:1924; RV32IZFINX-NEXT: fclass.s a0, a01925; RV32IZFINX-NEXT: srli a0, a0, 91926; RV32IZFINX-NEXT: ret1927;1928; RV64IF-LABEL: isqnan_fpclass:1929; RV64IF: # %bb.0:1930; RV64IF-NEXT: fclass.s a0, fa01931; RV64IF-NEXT: srli a0, a0, 91932; RV64IF-NEXT: ret1933;1934; RV64IZFINX-LABEL: isqnan_fpclass:1935; RV64IZFINX: # %bb.0:1936; RV64IZFINX-NEXT: fclass.s a0, a01937; RV64IZFINX-NEXT: srli a0, a0, 91938; RV64IZFINX-NEXT: ret1939;1940; RV64IFD-LABEL: isqnan_fpclass:1941; RV64IFD: # %bb.0:1942; RV64IFD-NEXT: fclass.s a0, fa01943; RV64IFD-NEXT: srli a0, a0, 91944; RV64IFD-NEXT: ret1945;1946; RV32I-LABEL: isqnan_fpclass:1947; RV32I: # %bb.0:1948; RV32I-NEXT: slli a0, a0, 11949; RV32I-NEXT: lui a1, 5232641950; RV32I-NEXT: srli a0, a0, 11951; RV32I-NEXT: addi a1, a1, -11952; RV32I-NEXT: slt a0, a1, a01953; RV32I-NEXT: ret1954;1955; RV64I-LABEL: isqnan_fpclass:1956; RV64I: # %bb.0:1957; RV64I-NEXT: slli a0, a0, 331958; RV64I-NEXT: lui a1, 5232641959; RV64I-NEXT: srli a0, a0, 331960; RV64I-NEXT: addi a1, a1, -11961; RV64I-NEXT: slt a0, a1, a01962; RV64I-NEXT: ret1963 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; qnan1964 ret i1 %11965}1966 1967define i1 @issnan_fpclass(float %x) {1968; RV32IF-LABEL: issnan_fpclass:1969; RV32IF: # %bb.0:1970; RV32IF-NEXT: fclass.s a0, fa01971; RV32IF-NEXT: slli a0, a0, 231972; RV32IF-NEXT: srli a0, a0, 311973; RV32IF-NEXT: ret1974;1975; RV32IZFINX-LABEL: issnan_fpclass:1976; RV32IZFINX: # %bb.0:1977; RV32IZFINX-NEXT: fclass.s a0, a01978; RV32IZFINX-NEXT: slli a0, a0, 231979; RV32IZFINX-NEXT: srli a0, a0, 311980; RV32IZFINX-NEXT: ret1981;1982; RV64IF-LABEL: issnan_fpclass:1983; RV64IF: # %bb.0:1984; RV64IF-NEXT: fclass.s a0, fa01985; RV64IF-NEXT: slli a0, a0, 551986; RV64IF-NEXT: srli a0, a0, 631987; RV64IF-NEXT: ret1988;1989; RV64IZFINX-LABEL: issnan_fpclass:1990; RV64IZFINX: # %bb.0:1991; RV64IZFINX-NEXT: fclass.s a0, a01992; RV64IZFINX-NEXT: slli a0, a0, 551993; RV64IZFINX-NEXT: srli a0, a0, 631994; RV64IZFINX-NEXT: ret1995;1996; RV64IFD-LABEL: issnan_fpclass:1997; RV64IFD: # %bb.0:1998; RV64IFD-NEXT: fclass.s a0, fa01999; RV64IFD-NEXT: slli a0, a0, 552000; RV64IFD-NEXT: srli a0, a0, 632001; RV64IFD-NEXT: ret2002;2003; RV32I-LABEL: issnan_fpclass:2004; RV32I: # %bb.0:2005; RV32I-NEXT: slli a0, a0, 12006; RV32I-NEXT: lui a1, 5232642007; RV32I-NEXT: lui a2, 5222402008; RV32I-NEXT: srli a0, a0, 12009; RV32I-NEXT: slt a1, a0, a12010; RV32I-NEXT: slt a0, a2, a02011; RV32I-NEXT: and a0, a0, a12012; RV32I-NEXT: ret2013;2014; RV64I-LABEL: issnan_fpclass:2015; RV64I: # %bb.0:2016; RV64I-NEXT: slli a0, a0, 332017; RV64I-NEXT: lui a1, 5232642018; RV64I-NEXT: lui a2, 5222402019; RV64I-NEXT: srli a0, a0, 332020; RV64I-NEXT: slt a1, a0, a12021; RV64I-NEXT: slt a0, a2, a02022; RV64I-NEXT: and a0, a0, a12023; RV64I-NEXT: ret2024 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; snan2025 ret i1 %12026}2027 2028define i1 @isinf_fpclass(float %x) {2029; RV32IF-LABEL: isinf_fpclass:2030; RV32IF: # %bb.0:2031; RV32IF-NEXT: fclass.s a0, fa02032; RV32IF-NEXT: andi a0, a0, 1292033; RV32IF-NEXT: snez a0, a02034; RV32IF-NEXT: ret2035;2036; RV32IZFINX-LABEL: isinf_fpclass:2037; RV32IZFINX: # %bb.0:2038; RV32IZFINX-NEXT: fclass.s a0, a02039; RV32IZFINX-NEXT: andi a0, a0, 1292040; RV32IZFINX-NEXT: snez a0, a02041; RV32IZFINX-NEXT: ret2042;2043; RV64IF-LABEL: isinf_fpclass:2044; RV64IF: # %bb.0:2045; RV64IF-NEXT: fclass.s a0, fa02046; RV64IF-NEXT: andi a0, a0, 1292047; RV64IF-NEXT: snez a0, a02048; RV64IF-NEXT: ret2049;2050; RV64IZFINX-LABEL: isinf_fpclass:2051; RV64IZFINX: # %bb.0:2052; RV64IZFINX-NEXT: fclass.s a0, a02053; RV64IZFINX-NEXT: andi a0, a0, 1292054; RV64IZFINX-NEXT: snez a0, a02055; RV64IZFINX-NEXT: ret2056;2057; RV64IFD-LABEL: isinf_fpclass:2058; RV64IFD: # %bb.0:2059; RV64IFD-NEXT: fclass.s a0, fa02060; RV64IFD-NEXT: andi a0, a0, 1292061; RV64IFD-NEXT: snez a0, a02062; RV64IFD-NEXT: ret2063;2064; RV32I-LABEL: isinf_fpclass:2065; RV32I: # %bb.0:2066; RV32I-NEXT: slli a0, a0, 12067; RV32I-NEXT: srli a0, a0, 12068; RV32I-NEXT: lui a1, 5222402069; RV32I-NEXT: xor a0, a0, a12070; RV32I-NEXT: seqz a0, a02071; RV32I-NEXT: ret2072;2073; RV64I-LABEL: isinf_fpclass:2074; RV64I: # %bb.0:2075; RV64I-NEXT: slli a0, a0, 332076; RV64I-NEXT: srli a0, a0, 332077; RV64I-NEXT: lui a1, 5222402078; RV64I-NEXT: xor a0, a0, a12079; RV64I-NEXT: seqz a0, a02080; RV64I-NEXT: ret2081 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"2082 ret i1 %12083}2084 2085define i1 @isposinf_fpclass(float %x) {2086; RV32IF-LABEL: isposinf_fpclass:2087; RV32IF: # %bb.0:2088; RV32IF-NEXT: fclass.s a0, fa02089; RV32IF-NEXT: slli a0, a0, 242090; RV32IF-NEXT: srli a0, a0, 312091; RV32IF-NEXT: ret2092;2093; RV32IZFINX-LABEL: isposinf_fpclass:2094; RV32IZFINX: # %bb.0:2095; RV32IZFINX-NEXT: fclass.s a0, a02096; RV32IZFINX-NEXT: slli a0, a0, 242097; RV32IZFINX-NEXT: srli a0, a0, 312098; RV32IZFINX-NEXT: ret2099;2100; RV64IF-LABEL: isposinf_fpclass:2101; RV64IF: # %bb.0:2102; RV64IF-NEXT: fclass.s a0, fa02103; RV64IF-NEXT: slli a0, a0, 562104; RV64IF-NEXT: srli a0, a0, 632105; RV64IF-NEXT: ret2106;2107; RV64IZFINX-LABEL: isposinf_fpclass:2108; RV64IZFINX: # %bb.0:2109; RV64IZFINX-NEXT: fclass.s a0, a02110; RV64IZFINX-NEXT: slli a0, a0, 562111; RV64IZFINX-NEXT: srli a0, a0, 632112; RV64IZFINX-NEXT: ret2113;2114; RV64IFD-LABEL: isposinf_fpclass:2115; RV64IFD: # %bb.0:2116; RV64IFD-NEXT: fclass.s a0, fa02117; RV64IFD-NEXT: slli a0, a0, 562118; RV64IFD-NEXT: srli a0, a0, 632119; RV64IFD-NEXT: ret2120;2121; RV32I-LABEL: isposinf_fpclass:2122; RV32I: # %bb.0:2123; RV32I-NEXT: lui a1, 5222402124; RV32I-NEXT: xor a0, a0, a12125; RV32I-NEXT: seqz a0, a02126; RV32I-NEXT: ret2127;2128; RV64I-LABEL: isposinf_fpclass:2129; RV64I: # %bb.0:2130; RV64I-NEXT: sext.w a0, a02131; RV64I-NEXT: lui a1, 5222402132; RV64I-NEXT: xor a0, a0, a12133; RV64I-NEXT: seqz a0, a02134; RV64I-NEXT: ret2135 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf"2136 ret i1 %12137}2138 2139define i1 @isneginf_fpclass(float %x) {2140; RV32IF-LABEL: isneginf_fpclass:2141; RV32IF: # %bb.0:2142; RV32IF-NEXT: fclass.s a0, fa02143; RV32IF-NEXT: andi a0, a0, 12144; RV32IF-NEXT: ret2145;2146; RV32IZFINX-LABEL: isneginf_fpclass:2147; RV32IZFINX: # %bb.0:2148; RV32IZFINX-NEXT: fclass.s a0, a02149; RV32IZFINX-NEXT: andi a0, a0, 12150; RV32IZFINX-NEXT: ret2151;2152; RV64IF-LABEL: isneginf_fpclass:2153; RV64IF: # %bb.0:2154; RV64IF-NEXT: fclass.s a0, fa02155; RV64IF-NEXT: andi a0, a0, 12156; RV64IF-NEXT: ret2157;2158; RV64IZFINX-LABEL: isneginf_fpclass:2159; RV64IZFINX: # %bb.0:2160; RV64IZFINX-NEXT: fclass.s a0, a02161; RV64IZFINX-NEXT: andi a0, a0, 12162; RV64IZFINX-NEXT: ret2163;2164; RV64IFD-LABEL: isneginf_fpclass:2165; RV64IFD: # %bb.0:2166; RV64IFD-NEXT: fclass.s a0, fa02167; RV64IFD-NEXT: andi a0, a0, 12168; RV64IFD-NEXT: ret2169;2170; RV32I-LABEL: isneginf_fpclass:2171; RV32I: # %bb.0:2172; RV32I-NEXT: lui a1, 10465282173; RV32I-NEXT: xor a0, a0, a12174; RV32I-NEXT: seqz a0, a02175; RV32I-NEXT: ret2176;2177; RV64I-LABEL: isneginf_fpclass:2178; RV64I: # %bb.0:2179; RV64I-NEXT: sext.w a0, a02180; RV64I-NEXT: lui a1, 10465282181; RV64I-NEXT: xor a0, a0, a12182; RV64I-NEXT: seqz a0, a02183; RV64I-NEXT: ret2184 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf"2185 ret i1 %12186}2187 2188define i1 @isfinite_fpclass(float %x) {2189; RV32IF-LABEL: isfinite_fpclass:2190; RV32IF: # %bb.0:2191; RV32IF-NEXT: fclass.s a0, fa02192; RV32IF-NEXT: andi a0, a0, 1262193; RV32IF-NEXT: snez a0, a02194; RV32IF-NEXT: ret2195;2196; RV32IZFINX-LABEL: isfinite_fpclass:2197; RV32IZFINX: # %bb.0:2198; RV32IZFINX-NEXT: fclass.s a0, a02199; RV32IZFINX-NEXT: andi a0, a0, 1262200; RV32IZFINX-NEXT: snez a0, a02201; RV32IZFINX-NEXT: ret2202;2203; RV64IF-LABEL: isfinite_fpclass:2204; RV64IF: # %bb.0:2205; RV64IF-NEXT: fclass.s a0, fa02206; RV64IF-NEXT: andi a0, a0, 1262207; RV64IF-NEXT: snez a0, a02208; RV64IF-NEXT: ret2209;2210; RV64IZFINX-LABEL: isfinite_fpclass:2211; RV64IZFINX: # %bb.0:2212; RV64IZFINX-NEXT: fclass.s a0, a02213; RV64IZFINX-NEXT: andi a0, a0, 1262214; RV64IZFINX-NEXT: snez a0, a02215; RV64IZFINX-NEXT: ret2216;2217; RV64IFD-LABEL: isfinite_fpclass:2218; RV64IFD: # %bb.0:2219; RV64IFD-NEXT: fclass.s a0, fa02220; RV64IFD-NEXT: andi a0, a0, 1262221; RV64IFD-NEXT: snez a0, a02222; RV64IFD-NEXT: ret2223;2224; RV32I-LABEL: isfinite_fpclass:2225; RV32I: # %bb.0:2226; RV32I-NEXT: slli a0, a0, 12227; RV32I-NEXT: srli a0, a0, 12228; RV32I-NEXT: lui a1, 5222402229; RV32I-NEXT: slt a0, a0, a12230; RV32I-NEXT: ret2231;2232; RV64I-LABEL: isfinite_fpclass:2233; RV64I: # %bb.0:2234; RV64I-NEXT: slli a0, a0, 332235; RV64I-NEXT: srli a0, a0, 332236; RV64I-NEXT: lui a1, 5222402237; RV64I-NEXT: slt a0, a0, a12238; RV64I-NEXT: ret2239 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"2240 ret i1 %12241}2242 2243define i1 @isposfinite_fpclass(float %x) {2244; RV32IF-LABEL: isposfinite_fpclass:2245; RV32IF: # %bb.0:2246; RV32IF-NEXT: fclass.s a0, fa02247; RV32IF-NEXT: andi a0, a0, 1122248; RV32IF-NEXT: snez a0, a02249; RV32IF-NEXT: ret2250;2251; RV32IZFINX-LABEL: isposfinite_fpclass:2252; RV32IZFINX: # %bb.0:2253; RV32IZFINX-NEXT: fclass.s a0, a02254; RV32IZFINX-NEXT: andi a0, a0, 1122255; RV32IZFINX-NEXT: snez a0, a02256; RV32IZFINX-NEXT: ret2257;2258; RV64IF-LABEL: isposfinite_fpclass:2259; RV64IF: # %bb.0:2260; RV64IF-NEXT: fclass.s a0, fa02261; RV64IF-NEXT: andi a0, a0, 1122262; RV64IF-NEXT: snez a0, a02263; RV64IF-NEXT: ret2264;2265; RV64IZFINX-LABEL: isposfinite_fpclass:2266; RV64IZFINX: # %bb.0:2267; RV64IZFINX-NEXT: fclass.s a0, a02268; RV64IZFINX-NEXT: andi a0, a0, 1122269; RV64IZFINX-NEXT: snez a0, a02270; RV64IZFINX-NEXT: ret2271;2272; RV64IFD-LABEL: isposfinite_fpclass:2273; RV64IFD: # %bb.0:2274; RV64IFD-NEXT: fclass.s a0, fa02275; RV64IFD-NEXT: andi a0, a0, 1122276; RV64IFD-NEXT: snez a0, a02277; RV64IFD-NEXT: ret2278;2279; RV32I-LABEL: isposfinite_fpclass:2280; RV32I: # %bb.0:2281; RV32I-NEXT: srli a0, a0, 232282; RV32I-NEXT: sltiu a0, a0, 2552283; RV32I-NEXT: ret2284;2285; RV64I-LABEL: isposfinite_fpclass:2286; RV64I: # %bb.0:2287; RV64I-NEXT: srliw a0, a0, 232288; RV64I-NEXT: sltiu a0, a0, 2552289; RV64I-NEXT: ret2290 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite"2291 ret i1 %12292}2293 2294define i1 @isnegfinite_fpclass(float %x) {2295; RV32IF-LABEL: isnegfinite_fpclass:2296; RV32IF: # %bb.0:2297; RV32IF-NEXT: fclass.s a0, fa02298; RV32IF-NEXT: andi a0, a0, 142299; RV32IF-NEXT: snez a0, a02300; RV32IF-NEXT: ret2301;2302; RV32IZFINX-LABEL: isnegfinite_fpclass:2303; RV32IZFINX: # %bb.0:2304; RV32IZFINX-NEXT: fclass.s a0, a02305; RV32IZFINX-NEXT: andi a0, a0, 142306; RV32IZFINX-NEXT: snez a0, a02307; RV32IZFINX-NEXT: ret2308;2309; RV64IF-LABEL: isnegfinite_fpclass:2310; RV64IF: # %bb.0:2311; RV64IF-NEXT: fclass.s a0, fa02312; RV64IF-NEXT: andi a0, a0, 142313; RV64IF-NEXT: snez a0, a02314; RV64IF-NEXT: ret2315;2316; RV64IZFINX-LABEL: isnegfinite_fpclass:2317; RV64IZFINX: # %bb.0:2318; RV64IZFINX-NEXT: fclass.s a0, a02319; RV64IZFINX-NEXT: andi a0, a0, 142320; RV64IZFINX-NEXT: snez a0, a02321; RV64IZFINX-NEXT: ret2322;2323; RV64IFD-LABEL: isnegfinite_fpclass:2324; RV64IFD: # %bb.0:2325; RV64IFD-NEXT: fclass.s a0, fa02326; RV64IFD-NEXT: andi a0, a0, 142327; RV64IFD-NEXT: snez a0, a02328; RV64IFD-NEXT: ret2329;2330; RV32I-LABEL: isnegfinite_fpclass:2331; RV32I: # %bb.0:2332; RV32I-NEXT: slli a1, a0, 12333; RV32I-NEXT: lui a2, 5222402334; RV32I-NEXT: srli a1, a1, 12335; RV32I-NEXT: slt a1, a1, a22336; RV32I-NEXT: srli a0, a0, 312337; RV32I-NEXT: and a0, a1, a02338; RV32I-NEXT: ret2339;2340; RV64I-LABEL: isnegfinite_fpclass:2341; RV64I: # %bb.0:2342; RV64I-NEXT: slli a1, a0, 332343; RV64I-NEXT: lui a2, 5222402344; RV64I-NEXT: srli a1, a1, 332345; RV64I-NEXT: slt a1, a1, a22346; RV64I-NEXT: srliw a0, a0, 312347; RV64I-NEXT: and a0, a1, a02348; RV64I-NEXT: ret2349 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite"2350 ret i1 %12351}2352 2353define i1 @isnotfinite_fpclass(float %x) {2354; RV32IF-LABEL: isnotfinite_fpclass:2355; RV32IF: # %bb.0:2356; RV32IF-NEXT: fclass.s a0, fa02357; RV32IF-NEXT: andi a0, a0, 8972358; RV32IF-NEXT: snez a0, a02359; RV32IF-NEXT: ret2360;2361; RV32IZFINX-LABEL: isnotfinite_fpclass:2362; RV32IZFINX: # %bb.0:2363; RV32IZFINX-NEXT: fclass.s a0, a02364; RV32IZFINX-NEXT: andi a0, a0, 8972365; RV32IZFINX-NEXT: snez a0, a02366; RV32IZFINX-NEXT: ret2367;2368; RV64IF-LABEL: isnotfinite_fpclass:2369; RV64IF: # %bb.0:2370; RV64IF-NEXT: fclass.s a0, fa02371; RV64IF-NEXT: andi a0, a0, 8972372; RV64IF-NEXT: snez a0, a02373; RV64IF-NEXT: ret2374;2375; RV64IZFINX-LABEL: isnotfinite_fpclass:2376; RV64IZFINX: # %bb.0:2377; RV64IZFINX-NEXT: fclass.s a0, a02378; RV64IZFINX-NEXT: andi a0, a0, 8972379; RV64IZFINX-NEXT: snez a0, a02380; RV64IZFINX-NEXT: ret2381;2382; RV64IFD-LABEL: isnotfinite_fpclass:2383; RV64IFD: # %bb.0:2384; RV64IFD-NEXT: fclass.s a0, fa02385; RV64IFD-NEXT: andi a0, a0, 8972386; RV64IFD-NEXT: snez a0, a02387; RV64IFD-NEXT: ret2388;2389; RV32I-LABEL: isnotfinite_fpclass:2390; RV32I: # %bb.0:2391; RV32I-NEXT: slli a0, a0, 12392; RV32I-NEXT: lui a1, 5222402393; RV32I-NEXT: srli a0, a0, 12394; RV32I-NEXT: addi a1, a1, -12395; RV32I-NEXT: slt a0, a1, a02396; RV32I-NEXT: ret2397;2398; RV64I-LABEL: isnotfinite_fpclass:2399; RV64I: # %bb.0:2400; RV64I-NEXT: slli a0, a0, 332401; RV64I-NEXT: lui a1, 5222402402; RV64I-NEXT: srli a0, a0, 332403; RV64I-NEXT: addi a1, a1, -12404; RV64I-NEXT: slt a0, a1, a02405; RV64I-NEXT: ret2406 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ox207 = "inf|nan"2407 ret i1 %12408}2409 2410define float @tan_f32(float %a) nounwind {2411; RV32IF-LABEL: tan_f32:2412; RV32IF: # %bb.0:2413; RV32IF-NEXT: tail tanf2414;2415; RV32IZFINX-LABEL: tan_f32:2416; RV32IZFINX: # %bb.0:2417; RV32IZFINX-NEXT: tail tanf2418;2419; RV64IF-LABEL: tan_f32:2420; RV64IF: # %bb.0:2421; RV64IF-NEXT: tail tanf2422;2423; RV64IZFINX-LABEL: tan_f32:2424; RV64IZFINX: # %bb.0:2425; RV64IZFINX-NEXT: tail tanf2426;2427; RV64IFD-LABEL: tan_f32:2428; RV64IFD: # %bb.0:2429; RV64IFD-NEXT: tail tanf2430;2431; RV32I-LABEL: tan_f32:2432; RV32I: # %bb.0:2433; RV32I-NEXT: addi sp, sp, -162434; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2435; RV32I-NEXT: call tanf2436; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2437; RV32I-NEXT: addi sp, sp, 162438; RV32I-NEXT: ret2439;2440; RV64I-LABEL: tan_f32:2441; RV64I: # %bb.0:2442; RV64I-NEXT: addi sp, sp, -162443; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2444; RV64I-NEXT: call tanf2445; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2446; RV64I-NEXT: addi sp, sp, 162447; RV64I-NEXT: ret2448 %1 = call float @llvm.tan.f32(float %a)2449 ret float %12450}2451 2452define float @maximumnum_float(float %x, float %y) {2453; RV32IF-LABEL: maximumnum_float:2454; RV32IF: # %bb.0:2455; RV32IF-NEXT: fmax.s fa0, fa0, fa12456; RV32IF-NEXT: ret2457;2458; RV32IZFINX-LABEL: maximumnum_float:2459; RV32IZFINX: # %bb.0:2460; RV32IZFINX-NEXT: fmax.s a0, a0, a12461; RV32IZFINX-NEXT: ret2462;2463; RV64IF-LABEL: maximumnum_float:2464; RV64IF: # %bb.0:2465; RV64IF-NEXT: fmax.s fa0, fa0, fa12466; RV64IF-NEXT: ret2467;2468; RV64IZFINX-LABEL: maximumnum_float:2469; RV64IZFINX: # %bb.0:2470; RV64IZFINX-NEXT: fmax.s a0, a0, a12471; RV64IZFINX-NEXT: ret2472;2473; RV64IFD-LABEL: maximumnum_float:2474; RV64IFD: # %bb.0:2475; RV64IFD-NEXT: fmax.s fa0, fa0, fa12476; RV64IFD-NEXT: ret2477;2478; RV32I-LABEL: maximumnum_float:2479; RV32I: # %bb.0:2480; RV32I-NEXT: addi sp, sp, -162481; RV32I-NEXT: .cfi_def_cfa_offset 162482; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2483; RV32I-NEXT: .cfi_offset ra, -42484; RV32I-NEXT: call fmaximum_numf2485; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2486; RV32I-NEXT: .cfi_restore ra2487; RV32I-NEXT: addi sp, sp, 162488; RV32I-NEXT: .cfi_def_cfa_offset 02489; RV32I-NEXT: ret2490;2491; RV64I-LABEL: maximumnum_float:2492; RV64I: # %bb.0:2493; RV64I-NEXT: addi sp, sp, -162494; RV64I-NEXT: .cfi_def_cfa_offset 162495; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2496; RV64I-NEXT: .cfi_offset ra, -82497; RV64I-NEXT: call fmaximum_numf2498; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2499; RV64I-NEXT: .cfi_restore ra2500; RV64I-NEXT: addi sp, sp, 162501; RV64I-NEXT: .cfi_def_cfa_offset 02502; RV64I-NEXT: ret2503 %z = call float @llvm.maximumnum.f32(float %x, float %y)2504 ret float %z2505}2506 2507define float @minimumnum_float(float %x, float %y) {2508; RV32IF-LABEL: minimumnum_float:2509; RV32IF: # %bb.0:2510; RV32IF-NEXT: fmin.s fa0, fa0, fa12511; RV32IF-NEXT: ret2512;2513; RV32IZFINX-LABEL: minimumnum_float:2514; RV32IZFINX: # %bb.0:2515; RV32IZFINX-NEXT: fmin.s a0, a0, a12516; RV32IZFINX-NEXT: ret2517;2518; RV64IF-LABEL: minimumnum_float:2519; RV64IF: # %bb.0:2520; RV64IF-NEXT: fmin.s fa0, fa0, fa12521; RV64IF-NEXT: ret2522;2523; RV64IZFINX-LABEL: minimumnum_float:2524; RV64IZFINX: # %bb.0:2525; RV64IZFINX-NEXT: fmin.s a0, a0, a12526; RV64IZFINX-NEXT: ret2527;2528; RV64IFD-LABEL: minimumnum_float:2529; RV64IFD: # %bb.0:2530; RV64IFD-NEXT: fmin.s fa0, fa0, fa12531; RV64IFD-NEXT: ret2532;2533; RV32I-LABEL: minimumnum_float:2534; RV32I: # %bb.0:2535; RV32I-NEXT: addi sp, sp, -162536; RV32I-NEXT: .cfi_def_cfa_offset 162537; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2538; RV32I-NEXT: .cfi_offset ra, -42539; RV32I-NEXT: call fminimum_numf2540; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2541; RV32I-NEXT: .cfi_restore ra2542; RV32I-NEXT: addi sp, sp, 162543; RV32I-NEXT: .cfi_def_cfa_offset 02544; RV32I-NEXT: ret2545;2546; RV64I-LABEL: minimumnum_float:2547; RV64I: # %bb.0:2548; RV64I-NEXT: addi sp, sp, -162549; RV64I-NEXT: .cfi_def_cfa_offset 162550; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2551; RV64I-NEXT: .cfi_offset ra, -82552; RV64I-NEXT: call fminimum_numf2553; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2554; RV64I-NEXT: .cfi_restore ra2555; RV64I-NEXT: addi sp, sp, 162556; RV64I-NEXT: .cfi_def_cfa_offset 02557; RV64I-NEXT: ret2558 %z = call float @llvm.minimumnum.f32(float %x, float %y)2559 ret float %z2560}2561 2562define float @ldexp_float(float %x, i32 signext %y) nounwind {2563; RV32IF-LABEL: ldexp_float:2564; RV32IF: # %bb.0:2565; RV32IF-NEXT: tail ldexpf2566;2567; RV32IZFINX-LABEL: ldexp_float:2568; RV32IZFINX: # %bb.0:2569; RV32IZFINX-NEXT: tail ldexpf2570;2571; RV64IF-LABEL: ldexp_float:2572; RV64IF: # %bb.0:2573; RV64IF-NEXT: addi sp, sp, -162574; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2575; RV64IF-NEXT: call ldexpf2576; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2577; RV64IF-NEXT: addi sp, sp, 162578; RV64IF-NEXT: ret2579;2580; RV64IZFINX-LABEL: ldexp_float:2581; RV64IZFINX: # %bb.0:2582; RV64IZFINX-NEXT: addi sp, sp, -162583; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2584; RV64IZFINX-NEXT: call ldexpf2585; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2586; RV64IZFINX-NEXT: addi sp, sp, 162587; RV64IZFINX-NEXT: ret2588;2589; RV64IFD-LABEL: ldexp_float:2590; RV64IFD: # %bb.0:2591; RV64IFD-NEXT: addi sp, sp, -162592; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2593; RV64IFD-NEXT: call ldexpf2594; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2595; RV64IFD-NEXT: addi sp, sp, 162596; RV64IFD-NEXT: ret2597;2598; RV32I-LABEL: ldexp_float:2599; RV32I: # %bb.0:2600; RV32I-NEXT: addi sp, sp, -162601; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2602; RV32I-NEXT: call ldexpf2603; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2604; RV32I-NEXT: addi sp, sp, 162605; RV32I-NEXT: ret2606;2607; RV64I-LABEL: ldexp_float:2608; RV64I: # %bb.0:2609; RV64I-NEXT: addi sp, sp, -162610; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2611; RV64I-NEXT: call ldexpf2612; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2613; RV64I-NEXT: addi sp, sp, 162614; RV64I-NEXT: ret2615 %z = call float @llvm.ldexp.f32.i32(float %x, i32 %y)2616 ret float %z2617}2618 2619define {float, i32} @frexp_float(float %x) nounwind {2620; RV32IF-LABEL: frexp_float:2621; RV32IF: # %bb.0:2622; RV32IF-NEXT: addi sp, sp, -162623; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2624; RV32IF-NEXT: addi a0, sp, 82625; RV32IF-NEXT: call frexpf2626; RV32IF-NEXT: lw a0, 8(sp)2627; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2628; RV32IF-NEXT: addi sp, sp, 162629; RV32IF-NEXT: ret2630;2631; RV32IZFINX-LABEL: frexp_float:2632; RV32IZFINX: # %bb.0:2633; RV32IZFINX-NEXT: addi sp, sp, -162634; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2635; RV32IZFINX-NEXT: addi a1, sp, 82636; RV32IZFINX-NEXT: call frexpf2637; RV32IZFINX-NEXT: lw a1, 8(sp)2638; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2639; RV32IZFINX-NEXT: addi sp, sp, 162640; RV32IZFINX-NEXT: ret2641;2642; RV64IF-LABEL: frexp_float:2643; RV64IF: # %bb.0:2644; RV64IF-NEXT: addi sp, sp, -162645; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2646; RV64IF-NEXT: mv a0, sp2647; RV64IF-NEXT: call frexpf2648; RV64IF-NEXT: ld a0, 0(sp)2649; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2650; RV64IF-NEXT: addi sp, sp, 162651; RV64IF-NEXT: ret2652;2653; RV64IZFINX-LABEL: frexp_float:2654; RV64IZFINX: # %bb.0:2655; RV64IZFINX-NEXT: addi sp, sp, -162656; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2657; RV64IZFINX-NEXT: mv a1, sp2658; RV64IZFINX-NEXT: call frexpf2659; RV64IZFINX-NEXT: ld a1, 0(sp)2660; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2661; RV64IZFINX-NEXT: addi sp, sp, 162662; RV64IZFINX-NEXT: ret2663;2664; RV64IFD-LABEL: frexp_float:2665; RV64IFD: # %bb.0:2666; RV64IFD-NEXT: addi sp, sp, -162667; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2668; RV64IFD-NEXT: mv a0, sp2669; RV64IFD-NEXT: call frexpf2670; RV64IFD-NEXT: ld a0, 0(sp)2671; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2672; RV64IFD-NEXT: addi sp, sp, 162673; RV64IFD-NEXT: ret2674;2675; RV32I-LABEL: frexp_float:2676; RV32I: # %bb.0:2677; RV32I-NEXT: addi sp, sp, -162678; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2679; RV32I-NEXT: addi a1, sp, 82680; RV32I-NEXT: call frexpf2681; RV32I-NEXT: lw a1, 8(sp)2682; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2683; RV32I-NEXT: addi sp, sp, 162684; RV32I-NEXT: ret2685;2686; RV64I-LABEL: frexp_float:2687; RV64I: # %bb.0:2688; RV64I-NEXT: addi sp, sp, -162689; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2690; RV64I-NEXT: addi a1, sp, 42691; RV64I-NEXT: call frexpf2692; RV64I-NEXT: lw a1, 4(sp)2693; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2694; RV64I-NEXT: addi sp, sp, 162695; RV64I-NEXT: ret2696 %a = call {float, i32} @llvm.frexp.f32.i32(float %x)2697 ret {float, i32} %a2698}2699 2700define float @asin_f32(float %a) nounwind {2701; RV32IF-LABEL: asin_f32:2702; RV32IF: # %bb.0:2703; RV32IF-NEXT: tail asinf2704;2705; RV32IZFINX-LABEL: asin_f32:2706; RV32IZFINX: # %bb.0:2707; RV32IZFINX-NEXT: tail asinf2708;2709; RV64IF-LABEL: asin_f32:2710; RV64IF: # %bb.0:2711; RV64IF-NEXT: tail asinf2712;2713; RV64IZFINX-LABEL: asin_f32:2714; RV64IZFINX: # %bb.0:2715; RV64IZFINX-NEXT: tail asinf2716;2717; RV64IFD-LABEL: asin_f32:2718; RV64IFD: # %bb.0:2719; RV64IFD-NEXT: tail asinf2720;2721; RV32I-LABEL: asin_f32:2722; RV32I: # %bb.0:2723; RV32I-NEXT: addi sp, sp, -162724; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2725; RV32I-NEXT: call asinf2726; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2727; RV32I-NEXT: addi sp, sp, 162728; RV32I-NEXT: ret2729;2730; RV64I-LABEL: asin_f32:2731; RV64I: # %bb.0:2732; RV64I-NEXT: addi sp, sp, -162733; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2734; RV64I-NEXT: call asinf2735; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2736; RV64I-NEXT: addi sp, sp, 162737; RV64I-NEXT: ret2738 %1 = call float @llvm.asin.f32(float %a)2739 ret float %12740}2741 2742define float @acos_f32(float %a) nounwind {2743; RV32IF-LABEL: acos_f32:2744; RV32IF: # %bb.0:2745; RV32IF-NEXT: tail acosf2746;2747; RV32IZFINX-LABEL: acos_f32:2748; RV32IZFINX: # %bb.0:2749; RV32IZFINX-NEXT: tail acosf2750;2751; RV64IF-LABEL: acos_f32:2752; RV64IF: # %bb.0:2753; RV64IF-NEXT: tail acosf2754;2755; RV64IZFINX-LABEL: acos_f32:2756; RV64IZFINX: # %bb.0:2757; RV64IZFINX-NEXT: tail acosf2758;2759; RV64IFD-LABEL: acos_f32:2760; RV64IFD: # %bb.0:2761; RV64IFD-NEXT: tail acosf2762;2763; RV32I-LABEL: acos_f32:2764; RV32I: # %bb.0:2765; RV32I-NEXT: addi sp, sp, -162766; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2767; RV32I-NEXT: call acosf2768; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2769; RV32I-NEXT: addi sp, sp, 162770; RV32I-NEXT: ret2771;2772; RV64I-LABEL: acos_f32:2773; RV64I: # %bb.0:2774; RV64I-NEXT: addi sp, sp, -162775; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2776; RV64I-NEXT: call acosf2777; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2778; RV64I-NEXT: addi sp, sp, 162779; RV64I-NEXT: ret2780 %1 = call float @llvm.acos.f32(float %a)2781 ret float %12782}2783 2784define float @atan_f32(float %a) nounwind {2785; RV32IF-LABEL: atan_f32:2786; RV32IF: # %bb.0:2787; RV32IF-NEXT: tail atanf2788;2789; RV32IZFINX-LABEL: atan_f32:2790; RV32IZFINX: # %bb.0:2791; RV32IZFINX-NEXT: tail atanf2792;2793; RV64IF-LABEL: atan_f32:2794; RV64IF: # %bb.0:2795; RV64IF-NEXT: tail atanf2796;2797; RV64IZFINX-LABEL: atan_f32:2798; RV64IZFINX: # %bb.0:2799; RV64IZFINX-NEXT: tail atanf2800;2801; RV64IFD-LABEL: atan_f32:2802; RV64IFD: # %bb.0:2803; RV64IFD-NEXT: tail atanf2804;2805; RV32I-LABEL: atan_f32:2806; RV32I: # %bb.0:2807; RV32I-NEXT: addi sp, sp, -162808; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2809; RV32I-NEXT: call atanf2810; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2811; RV32I-NEXT: addi sp, sp, 162812; RV32I-NEXT: ret2813;2814; RV64I-LABEL: atan_f32:2815; RV64I: # %bb.0:2816; RV64I-NEXT: addi sp, sp, -162817; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2818; RV64I-NEXT: call atanf2819; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2820; RV64I-NEXT: addi sp, sp, 162821; RV64I-NEXT: ret2822 %1 = call float @llvm.atan.f32(float %a)2823 ret float %12824}2825 2826define float @atan2_f32(float %a, float %b) nounwind {2827; RV32IF-LABEL: atan2_f32:2828; RV32IF: # %bb.0:2829; RV32IF-NEXT: tail atan2f2830;2831; RV32IZFINX-LABEL: atan2_f32:2832; RV32IZFINX: # %bb.0:2833; RV32IZFINX-NEXT: tail atan2f2834;2835; RV64IF-LABEL: atan2_f32:2836; RV64IF: # %bb.0:2837; RV64IF-NEXT: tail atan2f2838;2839; RV64IZFINX-LABEL: atan2_f32:2840; RV64IZFINX: # %bb.0:2841; RV64IZFINX-NEXT: tail atan2f2842;2843; RV64IFD-LABEL: atan2_f32:2844; RV64IFD: # %bb.0:2845; RV64IFD-NEXT: tail atan2f2846;2847; RV32I-LABEL: atan2_f32:2848; RV32I: # %bb.0:2849; RV32I-NEXT: addi sp, sp, -162850; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2851; RV32I-NEXT: call atan2f2852; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2853; RV32I-NEXT: addi sp, sp, 162854; RV32I-NEXT: ret2855;2856; RV64I-LABEL: atan2_f32:2857; RV64I: # %bb.0:2858; RV64I-NEXT: addi sp, sp, -162859; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2860; RV64I-NEXT: call atan2f2861; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2862; RV64I-NEXT: addi sp, sp, 162863; RV64I-NEXT: ret2864 %1 = call float @llvm.atan2.f32(float %a, float %b)2865 ret float %12866}2867 2868define float @sinh_f32(float %a) nounwind {2869; RV32IF-LABEL: sinh_f32:2870; RV32IF: # %bb.0:2871; RV32IF-NEXT: tail sinhf2872;2873; RV32IZFINX-LABEL: sinh_f32:2874; RV32IZFINX: # %bb.0:2875; RV32IZFINX-NEXT: tail sinhf2876;2877; RV64IF-LABEL: sinh_f32:2878; RV64IF: # %bb.0:2879; RV64IF-NEXT: tail sinhf2880;2881; RV64IZFINX-LABEL: sinh_f32:2882; RV64IZFINX: # %bb.0:2883; RV64IZFINX-NEXT: tail sinhf2884;2885; RV64IFD-LABEL: sinh_f32:2886; RV64IFD: # %bb.0:2887; RV64IFD-NEXT: tail sinhf2888;2889; RV32I-LABEL: sinh_f32:2890; RV32I: # %bb.0:2891; RV32I-NEXT: addi sp, sp, -162892; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2893; RV32I-NEXT: call sinhf2894; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2895; RV32I-NEXT: addi sp, sp, 162896; RV32I-NEXT: ret2897;2898; RV64I-LABEL: sinh_f32:2899; RV64I: # %bb.0:2900; RV64I-NEXT: addi sp, sp, -162901; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2902; RV64I-NEXT: call sinhf2903; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2904; RV64I-NEXT: addi sp, sp, 162905; RV64I-NEXT: ret2906 %1 = call float @llvm.sinh.f32(float %a)2907 ret float %12908}2909 2910define float @cosh_f32(float %a) nounwind {2911; RV32IF-LABEL: cosh_f32:2912; RV32IF: # %bb.0:2913; RV32IF-NEXT: tail coshf2914;2915; RV32IZFINX-LABEL: cosh_f32:2916; RV32IZFINX: # %bb.0:2917; RV32IZFINX-NEXT: tail coshf2918;2919; RV64IF-LABEL: cosh_f32:2920; RV64IF: # %bb.0:2921; RV64IF-NEXT: tail coshf2922;2923; RV64IZFINX-LABEL: cosh_f32:2924; RV64IZFINX: # %bb.0:2925; RV64IZFINX-NEXT: tail coshf2926;2927; RV64IFD-LABEL: cosh_f32:2928; RV64IFD: # %bb.0:2929; RV64IFD-NEXT: tail coshf2930;2931; RV32I-LABEL: cosh_f32:2932; RV32I: # %bb.0:2933; RV32I-NEXT: addi sp, sp, -162934; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2935; RV32I-NEXT: call coshf2936; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2937; RV32I-NEXT: addi sp, sp, 162938; RV32I-NEXT: ret2939;2940; RV64I-LABEL: cosh_f32:2941; RV64I: # %bb.0:2942; RV64I-NEXT: addi sp, sp, -162943; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2944; RV64I-NEXT: call coshf2945; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2946; RV64I-NEXT: addi sp, sp, 162947; RV64I-NEXT: ret2948 %1 = call float @llvm.cosh.f32(float %a)2949 ret float %12950}2951 2952define float @tanh_f32(float %a) nounwind {2953; RV32IF-LABEL: tanh_f32:2954; RV32IF: # %bb.0:2955; RV32IF-NEXT: tail tanhf2956;2957; RV32IZFINX-LABEL: tanh_f32:2958; RV32IZFINX: # %bb.0:2959; RV32IZFINX-NEXT: tail tanhf2960;2961; RV64IF-LABEL: tanh_f32:2962; RV64IF: # %bb.0:2963; RV64IF-NEXT: tail tanhf2964;2965; RV64IZFINX-LABEL: tanh_f32:2966; RV64IZFINX: # %bb.0:2967; RV64IZFINX-NEXT: tail tanhf2968;2969; RV64IFD-LABEL: tanh_f32:2970; RV64IFD: # %bb.0:2971; RV64IFD-NEXT: tail tanhf2972;2973; RV32I-LABEL: tanh_f32:2974; RV32I: # %bb.0:2975; RV32I-NEXT: addi sp, sp, -162976; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2977; RV32I-NEXT: call tanhf2978; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2979; RV32I-NEXT: addi sp, sp, 162980; RV32I-NEXT: ret2981;2982; RV64I-LABEL: tanh_f32:2983; RV64I: # %bb.0:2984; RV64I-NEXT: addi sp, sp, -162985; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill2986; RV64I-NEXT: call tanhf2987; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload2988; RV64I-NEXT: addi sp, sp, 162989; RV64I-NEXT: ret2990 %1 = call float @llvm.tanh.f32(float %a)2991 ret float %12992}2993 2994define { float, float } @test_modf_f32(float %a) nounwind {2995; RV32IF-LABEL: test_modf_f32:2996; RV32IF: # %bb.0:2997; RV32IF-NEXT: addi sp, sp, -162998; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2999; RV32IF-NEXT: addi a0, sp, 83000; RV32IF-NEXT: call modff3001; RV32IF-NEXT: flw fa1, 8(sp)3002; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3003; RV32IF-NEXT: addi sp, sp, 163004; RV32IF-NEXT: ret3005;3006; RV32IZFINX-LABEL: test_modf_f32:3007; RV32IZFINX: # %bb.0:3008; RV32IZFINX-NEXT: addi sp, sp, -163009; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill3010; RV32IZFINX-NEXT: addi a1, sp, 83011; RV32IZFINX-NEXT: call modff3012; RV32IZFINX-NEXT: lw a1, 8(sp)3013; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3014; RV32IZFINX-NEXT: addi sp, sp, 163015; RV32IZFINX-NEXT: ret3016;3017; RV64IF-LABEL: test_modf_f32:3018; RV64IF: # %bb.0:3019; RV64IF-NEXT: addi sp, sp, -163020; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill3021; RV64IF-NEXT: addi a0, sp, 43022; RV64IF-NEXT: call modff3023; RV64IF-NEXT: flw fa1, 4(sp)3024; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload3025; RV64IF-NEXT: addi sp, sp, 163026; RV64IF-NEXT: ret3027;3028; RV64IZFINX-LABEL: test_modf_f32:3029; RV64IZFINX: # %bb.0:3030; RV64IZFINX-NEXT: addi sp, sp, -163031; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill3032; RV64IZFINX-NEXT: addi a1, sp, 43033; RV64IZFINX-NEXT: call modff3034; RV64IZFINX-NEXT: lw a1, 4(sp)3035; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload3036; RV64IZFINX-NEXT: addi sp, sp, 163037; RV64IZFINX-NEXT: ret3038;3039; RV64IFD-LABEL: test_modf_f32:3040; RV64IFD: # %bb.0:3041; RV64IFD-NEXT: addi sp, sp, -163042; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill3043; RV64IFD-NEXT: addi a0, sp, 43044; RV64IFD-NEXT: call modff3045; RV64IFD-NEXT: flw fa1, 4(sp)3046; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload3047; RV64IFD-NEXT: addi sp, sp, 163048; RV64IFD-NEXT: ret3049;3050; RV32I-LABEL: test_modf_f32:3051; RV32I: # %bb.0:3052; RV32I-NEXT: addi sp, sp, -163053; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill3054; RV32I-NEXT: addi a1, sp, 83055; RV32I-NEXT: call modff3056; RV32I-NEXT: lw a1, 8(sp)3057; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3058; RV32I-NEXT: addi sp, sp, 163059; RV32I-NEXT: ret3060;3061; RV64I-LABEL: test_modf_f32:3062; RV64I: # %bb.0:3063; RV64I-NEXT: addi sp, sp, -163064; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill3065; RV64I-NEXT: addi a1, sp, 43066; RV64I-NEXT: call modff3067; RV64I-NEXT: lw a1, 4(sp)3068; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload3069; RV64I-NEXT: addi sp, sp, 163070; RV64I-NEXT: ret3071 %result = call { float, float } @llvm.modf.f32(float %a)3072 ret { float, float } %result3073}3074