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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \3; RUN: -verify-machineinstrs -target-abi=ilp32f \4; RUN: | FileCheck -check-prefix=RV32IF %s5; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \6; RUN: -verify-machineinstrs -target-abi=ilp32 \7; RUN: | FileCheck -check-prefix=RV32IZFINX %s8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \9; RUN: -verify-machineinstrs -target-abi=ilp32f \10; RUN: | FileCheck -check-prefix=RV32IF %s11; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \12; RUN: -verify-machineinstrs -target-abi=ilp32 \13; RUN: | FileCheck -check-prefix=RV32I %s14; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \15; RUN: -verify-machineinstrs -target-abi=lp64f \16; RUN: | FileCheck -check-prefix=RV64IF %s17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \18; RUN: -verify-machineinstrs -target-abi=lp64 \19; RUN: | FileCheck -check-prefix=RV64IZFINX %s20; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \21; RUN: -verify-machineinstrs -target-abi=lp64d \22; RUN: | FileCheck -check-prefix=RV64IF %s23; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \24; RUN: -verify-machineinstrs -target-abi=lp64 \25; RUN: | FileCheck -check-prefix=RV64I %s26 27define float @fminimum_f32(float %a, float %b) nounwind {28; RV32IF-LABEL: fminimum_f32:29; RV32IF: # %bb.0:30; RV32IF-NEXT: feq.s a0, fa0, fa031; RV32IF-NEXT: fmv.s fa5, fa132; RV32IF-NEXT: beqz a0, .LBB0_333; RV32IF-NEXT: # %bb.1:34; RV32IF-NEXT: feq.s a0, fa1, fa135; RV32IF-NEXT: beqz a0, .LBB0_436; RV32IF-NEXT: .LBB0_2:37; RV32IF-NEXT: fmin.s fa0, fa0, fa538; RV32IF-NEXT: ret39; RV32IF-NEXT: .LBB0_3:40; RV32IF-NEXT: fmv.s fa5, fa041; RV32IF-NEXT: feq.s a0, fa1, fa142; RV32IF-NEXT: bnez a0, .LBB0_243; RV32IF-NEXT: .LBB0_4:44; RV32IF-NEXT: fmin.s fa0, fa1, fa545; RV32IF-NEXT: ret46;47; RV32IZFINX-LABEL: fminimum_f32:48; RV32IZFINX: # %bb.0:49; RV32IZFINX-NEXT: feq.s a3, a0, a050; RV32IZFINX-NEXT: mv a2, a151; RV32IZFINX-NEXT: beqz a3, .LBB0_352; RV32IZFINX-NEXT: # %bb.1:53; RV32IZFINX-NEXT: feq.s a3, a1, a154; RV32IZFINX-NEXT: beqz a3, .LBB0_455; RV32IZFINX-NEXT: .LBB0_2:56; RV32IZFINX-NEXT: fmin.s a0, a0, a257; RV32IZFINX-NEXT: ret58; RV32IZFINX-NEXT: .LBB0_3:59; RV32IZFINX-NEXT: mv a2, a060; RV32IZFINX-NEXT: feq.s a3, a1, a161; RV32IZFINX-NEXT: bnez a3, .LBB0_262; RV32IZFINX-NEXT: .LBB0_4:63; RV32IZFINX-NEXT: fmin.s a0, a1, a264; RV32IZFINX-NEXT: ret65;66; RV32I-LABEL: fminimum_f32:67; RV32I: # %bb.0:68; RV32I-NEXT: addi sp, sp, -1669; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill70; RV32I-NEXT: call fminimumf71; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload72; RV32I-NEXT: addi sp, sp, 1673; RV32I-NEXT: ret74;75; RV64IF-LABEL: fminimum_f32:76; RV64IF: # %bb.0:77; RV64IF-NEXT: feq.s a0, fa0, fa078; RV64IF-NEXT: fmv.s fa5, fa179; RV64IF-NEXT: beqz a0, .LBB0_380; RV64IF-NEXT: # %bb.1:81; RV64IF-NEXT: feq.s a0, fa1, fa182; RV64IF-NEXT: beqz a0, .LBB0_483; RV64IF-NEXT: .LBB0_2:84; RV64IF-NEXT: fmin.s fa0, fa0, fa585; RV64IF-NEXT: ret86; RV64IF-NEXT: .LBB0_3:87; RV64IF-NEXT: fmv.s fa5, fa088; RV64IF-NEXT: feq.s a0, fa1, fa189; RV64IF-NEXT: bnez a0, .LBB0_290; RV64IF-NEXT: .LBB0_4:91; RV64IF-NEXT: fmin.s fa0, fa1, fa592; RV64IF-NEXT: ret93;94; RV64IZFINX-LABEL: fminimum_f32:95; RV64IZFINX: # %bb.0:96; RV64IZFINX-NEXT: feq.s a3, a0, a097; RV64IZFINX-NEXT: mv a2, a198; RV64IZFINX-NEXT: beqz a3, .LBB0_399; RV64IZFINX-NEXT: # %bb.1:100; RV64IZFINX-NEXT: feq.s a3, a1, a1101; RV64IZFINX-NEXT: beqz a3, .LBB0_4102; RV64IZFINX-NEXT: .LBB0_2:103; RV64IZFINX-NEXT: fmin.s a0, a0, a2104; RV64IZFINX-NEXT: ret105; RV64IZFINX-NEXT: .LBB0_3:106; RV64IZFINX-NEXT: mv a2, a0107; RV64IZFINX-NEXT: feq.s a3, a1, a1108; RV64IZFINX-NEXT: bnez a3, .LBB0_2109; RV64IZFINX-NEXT: .LBB0_4:110; RV64IZFINX-NEXT: fmin.s a0, a1, a2111; RV64IZFINX-NEXT: ret112;113; RV64I-LABEL: fminimum_f32:114; RV64I: # %bb.0:115; RV64I-NEXT: addi sp, sp, -16116; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill117; RV64I-NEXT: call fminimumf118; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload119; RV64I-NEXT: addi sp, sp, 16120; RV64I-NEXT: ret121 %1 = call float @llvm.minimum.f32(float %a, float %b)122 ret float %1123}124 125define float @fmaximum_f32(float %a, float %b) nounwind {126; RV32IF-LABEL: fmaximum_f32:127; RV32IF: # %bb.0:128; RV32IF-NEXT: feq.s a0, fa0, fa0129; RV32IF-NEXT: fmv.s fa5, fa1130; RV32IF-NEXT: beqz a0, .LBB1_3131; RV32IF-NEXT: # %bb.1:132; RV32IF-NEXT: feq.s a0, fa1, fa1133; RV32IF-NEXT: beqz a0, .LBB1_4134; RV32IF-NEXT: .LBB1_2:135; RV32IF-NEXT: fmax.s fa0, fa0, fa5136; RV32IF-NEXT: ret137; RV32IF-NEXT: .LBB1_3:138; RV32IF-NEXT: fmv.s fa5, fa0139; RV32IF-NEXT: feq.s a0, fa1, fa1140; RV32IF-NEXT: bnez a0, .LBB1_2141; RV32IF-NEXT: .LBB1_4:142; RV32IF-NEXT: fmax.s fa0, fa1, fa5143; RV32IF-NEXT: ret144;145; RV32IZFINX-LABEL: fmaximum_f32:146; RV32IZFINX: # %bb.0:147; RV32IZFINX-NEXT: feq.s a3, a0, a0148; RV32IZFINX-NEXT: mv a2, a1149; RV32IZFINX-NEXT: beqz a3, .LBB1_3150; RV32IZFINX-NEXT: # %bb.1:151; RV32IZFINX-NEXT: feq.s a3, a1, a1152; RV32IZFINX-NEXT: beqz a3, .LBB1_4153; RV32IZFINX-NEXT: .LBB1_2:154; RV32IZFINX-NEXT: fmax.s a0, a0, a2155; RV32IZFINX-NEXT: ret156; RV32IZFINX-NEXT: .LBB1_3:157; RV32IZFINX-NEXT: mv a2, a0158; RV32IZFINX-NEXT: feq.s a3, a1, a1159; RV32IZFINX-NEXT: bnez a3, .LBB1_2160; RV32IZFINX-NEXT: .LBB1_4:161; RV32IZFINX-NEXT: fmax.s a0, a1, a2162; RV32IZFINX-NEXT: ret163;164; RV32I-LABEL: fmaximum_f32:165; RV32I: # %bb.0:166; RV32I-NEXT: addi sp, sp, -16167; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill168; RV32I-NEXT: call fmaximumf169; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload170; RV32I-NEXT: addi sp, sp, 16171; RV32I-NEXT: ret172;173; RV64IF-LABEL: fmaximum_f32:174; RV64IF: # %bb.0:175; RV64IF-NEXT: feq.s a0, fa0, fa0176; RV64IF-NEXT: fmv.s fa5, fa1177; RV64IF-NEXT: beqz a0, .LBB1_3178; RV64IF-NEXT: # %bb.1:179; RV64IF-NEXT: feq.s a0, fa1, fa1180; RV64IF-NEXT: beqz a0, .LBB1_4181; RV64IF-NEXT: .LBB1_2:182; RV64IF-NEXT: fmax.s fa0, fa0, fa5183; RV64IF-NEXT: ret184; RV64IF-NEXT: .LBB1_3:185; RV64IF-NEXT: fmv.s fa5, fa0186; RV64IF-NEXT: feq.s a0, fa1, fa1187; RV64IF-NEXT: bnez a0, .LBB1_2188; RV64IF-NEXT: .LBB1_4:189; RV64IF-NEXT: fmax.s fa0, fa1, fa5190; RV64IF-NEXT: ret191;192; RV64IZFINX-LABEL: fmaximum_f32:193; RV64IZFINX: # %bb.0:194; RV64IZFINX-NEXT: feq.s a3, a0, a0195; RV64IZFINX-NEXT: mv a2, a1196; RV64IZFINX-NEXT: beqz a3, .LBB1_3197; RV64IZFINX-NEXT: # %bb.1:198; RV64IZFINX-NEXT: feq.s a3, a1, a1199; RV64IZFINX-NEXT: beqz a3, .LBB1_4200; RV64IZFINX-NEXT: .LBB1_2:201; RV64IZFINX-NEXT: fmax.s a0, a0, a2202; RV64IZFINX-NEXT: ret203; RV64IZFINX-NEXT: .LBB1_3:204; RV64IZFINX-NEXT: mv a2, a0205; RV64IZFINX-NEXT: feq.s a3, a1, a1206; RV64IZFINX-NEXT: bnez a3, .LBB1_2207; RV64IZFINX-NEXT: .LBB1_4:208; RV64IZFINX-NEXT: fmax.s a0, a1, a2209; RV64IZFINX-NEXT: ret210;211; RV64I-LABEL: fmaximum_f32:212; RV64I: # %bb.0:213; RV64I-NEXT: addi sp, sp, -16214; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill215; RV64I-NEXT: call fmaximumf216; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload217; RV64I-NEXT: addi sp, sp, 16218; RV64I-NEXT: ret219 %1 = call float @llvm.maximum.f32(float %a, float %b)220 ret float %1221}222 223define float @fminimum_nnan_f32(float %a, float %b) nounwind {224; RV32IF-LABEL: fminimum_nnan_f32:225; RV32IF: # %bb.0:226; RV32IF-NEXT: fmin.s fa0, fa0, fa1227; RV32IF-NEXT: ret228;229; RV32IZFINX-LABEL: fminimum_nnan_f32:230; RV32IZFINX: # %bb.0:231; RV32IZFINX-NEXT: fmin.s a0, a0, a1232; RV32IZFINX-NEXT: ret233;234; RV32I-LABEL: fminimum_nnan_f32:235; RV32I: # %bb.0:236; RV32I-NEXT: addi sp, sp, -16237; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill238; RV32I-NEXT: call fminimumf239; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload240; RV32I-NEXT: addi sp, sp, 16241; RV32I-NEXT: ret242;243; RV64IF-LABEL: fminimum_nnan_f32:244; RV64IF: # %bb.0:245; RV64IF-NEXT: fmin.s fa0, fa0, fa1246; RV64IF-NEXT: ret247;248; RV64IZFINX-LABEL: fminimum_nnan_f32:249; RV64IZFINX: # %bb.0:250; RV64IZFINX-NEXT: fmin.s a0, a0, a1251; RV64IZFINX-NEXT: ret252;253; RV64I-LABEL: fminimum_nnan_f32:254; RV64I: # %bb.0:255; RV64I-NEXT: addi sp, sp, -16256; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill257; RV64I-NEXT: call fminimumf258; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload259; RV64I-NEXT: addi sp, sp, 16260; RV64I-NEXT: ret261 %1 = call nnan float @llvm.minimum.f32(float %a, float %b)262 ret float %1263}264 265define float @fmaximum_nnan_f32(float %a, float %b) nounwind {266; RV32IF-LABEL: fmaximum_nnan_f32:267; RV32IF: # %bb.0:268; RV32IF-NEXT: fmax.s fa0, fa0, fa1269; RV32IF-NEXT: ret270;271; RV32IZFINX-LABEL: fmaximum_nnan_f32:272; RV32IZFINX: # %bb.0:273; RV32IZFINX-NEXT: fmax.s a0, a0, a1274; RV32IZFINX-NEXT: ret275;276; RV32I-LABEL: fmaximum_nnan_f32:277; RV32I: # %bb.0:278; RV32I-NEXT: addi sp, sp, -16279; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill280; RV32I-NEXT: call fmaximumf281; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload282; RV32I-NEXT: addi sp, sp, 16283; RV32I-NEXT: ret284;285; RV64IF-LABEL: fmaximum_nnan_f32:286; RV64IF: # %bb.0:287; RV64IF-NEXT: fmax.s fa0, fa0, fa1288; RV64IF-NEXT: ret289;290; RV64IZFINX-LABEL: fmaximum_nnan_f32:291; RV64IZFINX: # %bb.0:292; RV64IZFINX-NEXT: fmax.s a0, a0, a1293; RV64IZFINX-NEXT: ret294;295; RV64I-LABEL: fmaximum_nnan_f32:296; RV64I: # %bb.0:297; RV64I-NEXT: addi sp, sp, -16298; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill299; RV64I-NEXT: call fmaximumf300; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload301; RV64I-NEXT: addi sp, sp, 16302; RV64I-NEXT: ret303 %1 = call nnan float @llvm.maximum.f32(float %a, float %b)304 ret float %1305}306 307define float @fminimum_nnan_attr_f32(float %a, float %b) nounwind "no-nans-fp-math"="true" {308; RV32IF-LABEL: fminimum_nnan_attr_f32:309; RV32IF: # %bb.0:310; RV32IF-NEXT: fmin.s fa0, fa0, fa1311; RV32IF-NEXT: ret312;313; RV32IZFINX-LABEL: fminimum_nnan_attr_f32:314; RV32IZFINX: # %bb.0:315; RV32IZFINX-NEXT: fmin.s a0, a0, a1316; RV32IZFINX-NEXT: ret317;318; RV32I-LABEL: fminimum_nnan_attr_f32:319; RV32I: # %bb.0:320; RV32I-NEXT: addi sp, sp, -16321; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill322; RV32I-NEXT: call fminimumf323; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload324; RV32I-NEXT: addi sp, sp, 16325; RV32I-NEXT: ret326;327; RV64IF-LABEL: fminimum_nnan_attr_f32:328; RV64IF: # %bb.0:329; RV64IF-NEXT: fmin.s fa0, fa0, fa1330; RV64IF-NEXT: ret331;332; RV64IZFINX-LABEL: fminimum_nnan_attr_f32:333; RV64IZFINX: # %bb.0:334; RV64IZFINX-NEXT: fmin.s a0, a0, a1335; RV64IZFINX-NEXT: ret336;337; RV64I-LABEL: fminimum_nnan_attr_f32:338; RV64I: # %bb.0:339; RV64I-NEXT: addi sp, sp, -16340; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill341; RV64I-NEXT: call fminimumf342; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload343; RV64I-NEXT: addi sp, sp, 16344; RV64I-NEXT: ret345 %1 = call float @llvm.minimum.f32(float %a, float %b)346 ret float %1347}348 349define float @fminimum_nnan_op_f32(float %a, float %b) nounwind {350; RV32IF-LABEL: fminimum_nnan_op_f32:351; RV32IF: # %bb.0:352; RV32IF-NEXT: feq.s a0, fa0, fa0353; RV32IF-NEXT: bnez a0, .LBB5_2354; RV32IF-NEXT: # %bb.1:355; RV32IF-NEXT: fmin.s fa0, fa0, fa0356; RV32IF-NEXT: ret357; RV32IF-NEXT: .LBB5_2:358; RV32IF-NEXT: fadd.s fa5, fa0, fa0359; RV32IF-NEXT: fmin.s fa0, fa0, fa5360; RV32IF-NEXT: ret361;362; RV32IZFINX-LABEL: fminimum_nnan_op_f32:363; RV32IZFINX: # %bb.0:364; RV32IZFINX-NEXT: feq.s a1, a0, a0365; RV32IZFINX-NEXT: bnez a1, .LBB5_2366; RV32IZFINX-NEXT: # %bb.1:367; RV32IZFINX-NEXT: fmin.s a0, a0, a0368; RV32IZFINX-NEXT: ret369; RV32IZFINX-NEXT: .LBB5_2:370; RV32IZFINX-NEXT: fadd.s a1, a0, a0371; RV32IZFINX-NEXT: fmin.s a0, a0, a1372; RV32IZFINX-NEXT: ret373;374; RV32I-LABEL: fminimum_nnan_op_f32:375; RV32I: # %bb.0:376; RV32I-NEXT: addi sp, sp, -16377; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill378; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill379; RV32I-NEXT: mv s0, a0380; RV32I-NEXT: mv a1, a0381; RV32I-NEXT: call __addsf3382; RV32I-NEXT: mv a1, a0383; RV32I-NEXT: mv a0, s0384; RV32I-NEXT: call fminimumf385; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload386; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload387; RV32I-NEXT: addi sp, sp, 16388; RV32I-NEXT: ret389;390; RV64IF-LABEL: fminimum_nnan_op_f32:391; RV64IF: # %bb.0:392; RV64IF-NEXT: feq.s a0, fa0, fa0393; RV64IF-NEXT: bnez a0, .LBB5_2394; RV64IF-NEXT: # %bb.1:395; RV64IF-NEXT: fmin.s fa0, fa0, fa0396; RV64IF-NEXT: ret397; RV64IF-NEXT: .LBB5_2:398; RV64IF-NEXT: fadd.s fa5, fa0, fa0399; RV64IF-NEXT: fmin.s fa0, fa0, fa5400; RV64IF-NEXT: ret401;402; RV64IZFINX-LABEL: fminimum_nnan_op_f32:403; RV64IZFINX: # %bb.0:404; RV64IZFINX-NEXT: feq.s a1, a0, a0405; RV64IZFINX-NEXT: bnez a1, .LBB5_2406; RV64IZFINX-NEXT: # %bb.1:407; RV64IZFINX-NEXT: fmin.s a0, a0, a0408; RV64IZFINX-NEXT: ret409; RV64IZFINX-NEXT: .LBB5_2:410; RV64IZFINX-NEXT: fadd.s a1, a0, a0411; RV64IZFINX-NEXT: fmin.s a0, a0, a1412; RV64IZFINX-NEXT: ret413;414; RV64I-LABEL: fminimum_nnan_op_f32:415; RV64I: # %bb.0:416; RV64I-NEXT: addi sp, sp, -16417; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill418; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill419; RV64I-NEXT: mv s0, a0420; RV64I-NEXT: mv a1, a0421; RV64I-NEXT: call __addsf3422; RV64I-NEXT: mv a1, a0423; RV64I-NEXT: mv a0, s0424; RV64I-NEXT: call fminimumf425; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload426; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload427; RV64I-NEXT: addi sp, sp, 16428; RV64I-NEXT: ret429 %c = fadd nnan float %a, %a430 %1 = call float @llvm.minimum.f32(float %a, float %c)431 ret float %1432}433 434define float @fmaximum_nnan_op_f32(float %a, float %b) nounwind {435; RV32IF-LABEL: fmaximum_nnan_op_f32:436; RV32IF: # %bb.0:437; RV32IF-NEXT: fadd.s fa5, fa0, fa1438; RV32IF-NEXT: fsub.s fa4, fa0, fa1439; RV32IF-NEXT: fmax.s fa0, fa5, fa4440; RV32IF-NEXT: ret441;442; RV32IZFINX-LABEL: fmaximum_nnan_op_f32:443; RV32IZFINX: # %bb.0:444; RV32IZFINX-NEXT: fadd.s a2, a0, a1445; RV32IZFINX-NEXT: fsub.s a0, a0, a1446; RV32IZFINX-NEXT: fmax.s a0, a2, a0447; RV32IZFINX-NEXT: ret448;449; RV32I-LABEL: fmaximum_nnan_op_f32:450; RV32I: # %bb.0:451; RV32I-NEXT: addi sp, sp, -16452; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill453; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill454; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill455; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill456; RV32I-NEXT: mv s0, a1457; RV32I-NEXT: mv s1, a0458; RV32I-NEXT: call __addsf3459; RV32I-NEXT: mv s2, a0460; RV32I-NEXT: mv a0, s1461; RV32I-NEXT: mv a1, s0462; RV32I-NEXT: call __subsf3463; RV32I-NEXT: mv a1, a0464; RV32I-NEXT: mv a0, s2465; RV32I-NEXT: call fmaximumf466; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload467; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload468; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload469; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload470; RV32I-NEXT: addi sp, sp, 16471; RV32I-NEXT: ret472;473; RV64IF-LABEL: fmaximum_nnan_op_f32:474; RV64IF: # %bb.0:475; RV64IF-NEXT: fadd.s fa5, fa0, fa1476; RV64IF-NEXT: fsub.s fa4, fa0, fa1477; RV64IF-NEXT: fmax.s fa0, fa5, fa4478; RV64IF-NEXT: ret479;480; RV64IZFINX-LABEL: fmaximum_nnan_op_f32:481; RV64IZFINX: # %bb.0:482; RV64IZFINX-NEXT: fadd.s a2, a0, a1483; RV64IZFINX-NEXT: fsub.s a0, a0, a1484; RV64IZFINX-NEXT: fmax.s a0, a2, a0485; RV64IZFINX-NEXT: ret486;487; RV64I-LABEL: fmaximum_nnan_op_f32:488; RV64I: # %bb.0:489; RV64I-NEXT: addi sp, sp, -32490; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill491; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill492; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill493; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill494; RV64I-NEXT: mv s0, a1495; RV64I-NEXT: mv s1, a0496; RV64I-NEXT: call __addsf3497; RV64I-NEXT: mv s2, a0498; RV64I-NEXT: mv a0, s1499; RV64I-NEXT: mv a1, s0500; RV64I-NEXT: call __subsf3501; RV64I-NEXT: mv a1, a0502; RV64I-NEXT: mv a0, s2503; RV64I-NEXT: call fmaximumf504; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload505; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload506; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload507; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload508; RV64I-NEXT: addi sp, sp, 32509; RV64I-NEXT: ret510 %c = fadd nnan float %a, %b511 %d = fsub nnan float %a, %b512 %1 = call float @llvm.maximum.f32(float %c, float %d)513 ret float %1514}515