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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \5; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s6; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \7; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \9; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s10 11define dso_local float @flw(ptr %a) nounwind {12; CHECKIF-LABEL: flw:13; CHECKIF: # %bb.0:14; CHECKIF-NEXT: flw fa5, 0(a0)15; CHECKIF-NEXT: flw fa4, 12(a0)16; CHECKIF-NEXT: fadd.s fa0, fa5, fa417; CHECKIF-NEXT: ret18;19; CHECKIZFINX-LABEL: flw:20; CHECKIZFINX: # %bb.0:21; CHECKIZFINX-NEXT: lw a1, 0(a0)22; CHECKIZFINX-NEXT: lw a0, 12(a0)23; CHECKIZFINX-NEXT: fadd.s a0, a1, a024; CHECKIZFINX-NEXT: ret25 %1 = load float, ptr %a26 %2 = getelementptr float, ptr %a, i32 327 %3 = load float, ptr %228; Use both loaded values in an FP op to ensure an flw is used, even for the29; soft float ABI30 %4 = fadd float %1, %331 ret float %432}33 34define dso_local void @fsw(ptr %a, float %b, float %c) nounwind {35; Use %b and %c in an FP op to ensure floating point registers are used, even36; for the soft float ABI37; CHECKIF-LABEL: fsw:38; CHECKIF: # %bb.0:39; CHECKIF-NEXT: fadd.s fa5, fa0, fa140; CHECKIF-NEXT: fsw fa5, 0(a0)41; CHECKIF-NEXT: fsw fa5, 32(a0)42; CHECKIF-NEXT: ret43;44; CHECKIZFINX-LABEL: fsw:45; CHECKIZFINX: # %bb.0:46; CHECKIZFINX-NEXT: fadd.s a1, a1, a247; CHECKIZFINX-NEXT: sw a1, 0(a0)48; CHECKIZFINX-NEXT: sw a1, 32(a0)49; CHECKIZFINX-NEXT: ret50 %1 = fadd float %b, %c51 store float %1, ptr %a52 %2 = getelementptr float, ptr %a, i32 853 store float %1, ptr %254 ret void55}56 57; Check load and store to a global58@G = dso_local global float 0.059 60define dso_local float @flw_fsw_global(float %a, float %b) nounwind {61; Use %a and %b in an FP op to ensure floating point registers are used, even62; for the soft float ABI63; CHECKIF-LABEL: flw_fsw_global:64; CHECKIF: # %bb.0:65; CHECKIF-NEXT: fadd.s fa0, fa0, fa166; CHECKIF-NEXT: lui a0, %hi(G)67; CHECKIF-NEXT: addi a0, a0, %lo(G)68; CHECKIF-NEXT: flw fa5, 0(a0)69; CHECKIF-NEXT: fsw fa0, 0(a0)70; CHECKIF-NEXT: flw fa5, 36(a0)71; CHECKIF-NEXT: fsw fa0, 36(a0)72; CHECKIF-NEXT: ret73;74; CHECKIZFINX-LABEL: flw_fsw_global:75; CHECKIZFINX: # %bb.0:76; CHECKIZFINX-NEXT: fadd.s a0, a0, a177; CHECKIZFINX-NEXT: lui a1, %hi(G)78; CHECKIZFINX-NEXT: addi a1, a1, %lo(G)79; CHECKIZFINX-NEXT: lw zero, 0(a1)80; CHECKIZFINX-NEXT: sw a0, 0(a1)81; CHECKIZFINX-NEXT: lw zero, 36(a1)82; CHECKIZFINX-NEXT: sw a0, 36(a1)83; CHECKIZFINX-NEXT: ret84 %1 = fadd float %a, %b85 %2 = load volatile float, ptr @G86 store float %1, ptr @G87 %3 = getelementptr float, ptr @G, i32 988 %4 = load volatile float, ptr %389 store float %1, ptr %390 ret float %191}92 93; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 194define dso_local float @flw_fsw_constant(float %a) nounwind {95; RV32IF-LABEL: flw_fsw_constant:96; RV32IF: # %bb.0:97; RV32IF-NEXT: lui a0, 91209298; RV32IF-NEXT: flw fa5, -273(a0)99; RV32IF-NEXT: fadd.s fa0, fa0, fa5100; RV32IF-NEXT: fsw fa0, -273(a0)101; RV32IF-NEXT: ret102;103; RV64IF-LABEL: flw_fsw_constant:104; RV64IF: # %bb.0:105; RV64IF-NEXT: lui a0, 228023106; RV64IF-NEXT: slli a0, a0, 2107; RV64IF-NEXT: flw fa5, -273(a0)108; RV64IF-NEXT: fadd.s fa0, fa0, fa5109; RV64IF-NEXT: fsw fa0, -273(a0)110; RV64IF-NEXT: ret111;112; RV32IZFINX-LABEL: flw_fsw_constant:113; RV32IZFINX: # %bb.0:114; RV32IZFINX-NEXT: lui a1, 912092115; RV32IZFINX-NEXT: lw a2, -273(a1)116; RV32IZFINX-NEXT: fadd.s a0, a0, a2117; RV32IZFINX-NEXT: sw a0, -273(a1)118; RV32IZFINX-NEXT: ret119;120; RV64IZFINX-LABEL: flw_fsw_constant:121; RV64IZFINX: # %bb.0:122; RV64IZFINX-NEXT: lui a1, 228023123; RV64IZFINX-NEXT: slli a1, a1, 2124; RV64IZFINX-NEXT: lw a2, -273(a1)125; RV64IZFINX-NEXT: fadd.s a0, a0, a2126; RV64IZFINX-NEXT: sw a0, -273(a1)127; RV64IZFINX-NEXT: ret128 %1 = inttoptr i32 3735928559 to ptr129 %2 = load volatile float, ptr %1130 %3 = fadd float %a, %2131 store float %3, ptr %1132 ret float %3133}134 135declare void @notdead(ptr)136 137define dso_local float @flw_stack(float %a) nounwind {138; RV32IF-LABEL: flw_stack:139; RV32IF: # %bb.0:140; RV32IF-NEXT: addi sp, sp, -16141; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill142; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill143; RV32IF-NEXT: fmv.s fs0, fa0144; RV32IF-NEXT: addi a0, sp, 4145; RV32IF-NEXT: call notdead146; RV32IF-NEXT: flw fa5, 4(sp)147; RV32IF-NEXT: fadd.s fa0, fa5, fs0148; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload149; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload150; RV32IF-NEXT: addi sp, sp, 16151; RV32IF-NEXT: ret152;153; RV64IF-LABEL: flw_stack:154; RV64IF: # %bb.0:155; RV64IF-NEXT: addi sp, sp, -16156; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill157; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill158; RV64IF-NEXT: fmv.s fs0, fa0159; RV64IF-NEXT: mv a0, sp160; RV64IF-NEXT: call notdead161; RV64IF-NEXT: flw fa5, 0(sp)162; RV64IF-NEXT: fadd.s fa0, fa5, fs0163; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload164; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload165; RV64IF-NEXT: addi sp, sp, 16166; RV64IF-NEXT: ret167;168; RV32IZFINX-LABEL: flw_stack:169; RV32IZFINX: # %bb.0:170; RV32IZFINX-NEXT: addi sp, sp, -16171; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill172; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill173; RV32IZFINX-NEXT: mv s0, a0174; RV32IZFINX-NEXT: addi a0, sp, 4175; RV32IZFINX-NEXT: call notdead176; RV32IZFINX-NEXT: lw a0, 4(sp)177; RV32IZFINX-NEXT: fadd.s a0, a0, s0178; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload179; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload180; RV32IZFINX-NEXT: addi sp, sp, 16181; RV32IZFINX-NEXT: ret182;183; RV64IZFINX-LABEL: flw_stack:184; RV64IZFINX: # %bb.0:185; RV64IZFINX-NEXT: addi sp, sp, -32186; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill187; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill188; RV64IZFINX-NEXT: mv s0, a0189; RV64IZFINX-NEXT: addi a0, sp, 12190; RV64IZFINX-NEXT: call notdead191; RV64IZFINX-NEXT: lw a0, 12(sp)192; RV64IZFINX-NEXT: fadd.s a0, a0, s0193; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload194; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload195; RV64IZFINX-NEXT: addi sp, sp, 32196; RV64IZFINX-NEXT: ret197 %1 = alloca float, align 4198 call void @notdead(ptr %1)199 %2 = load float, ptr %1200 %3 = fadd float %2, %a ; force load in to FPR32201 ret float %3202}203 204define dso_local void @fsw_stack(float %a, float %b) nounwind {205; RV32IF-LABEL: fsw_stack:206; RV32IF: # %bb.0:207; RV32IF-NEXT: addi sp, sp, -16208; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill209; RV32IF-NEXT: fadd.s fa5, fa0, fa1210; RV32IF-NEXT: fsw fa5, 8(sp)211; RV32IF-NEXT: addi a0, sp, 8212; RV32IF-NEXT: call notdead213; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload214; RV32IF-NEXT: addi sp, sp, 16215; RV32IF-NEXT: ret216;217; RV64IF-LABEL: fsw_stack:218; RV64IF: # %bb.0:219; RV64IF-NEXT: addi sp, sp, -16220; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill221; RV64IF-NEXT: fadd.s fa5, fa0, fa1222; RV64IF-NEXT: fsw fa5, 4(sp)223; RV64IF-NEXT: addi a0, sp, 4224; RV64IF-NEXT: call notdead225; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload226; RV64IF-NEXT: addi sp, sp, 16227; RV64IF-NEXT: ret228;229; RV32IZFINX-LABEL: fsw_stack:230; RV32IZFINX: # %bb.0:231; RV32IZFINX-NEXT: addi sp, sp, -16232; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill233; RV32IZFINX-NEXT: fadd.s a0, a0, a1234; RV32IZFINX-NEXT: sw a0, 8(sp)235; RV32IZFINX-NEXT: addi a0, sp, 8236; RV32IZFINX-NEXT: call notdead237; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload238; RV32IZFINX-NEXT: addi sp, sp, 16239; RV32IZFINX-NEXT: ret240;241; RV64IZFINX-LABEL: fsw_stack:242; RV64IZFINX: # %bb.0:243; RV64IZFINX-NEXT: addi sp, sp, -16244; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill245; RV64IZFINX-NEXT: fadd.s a0, a0, a1246; RV64IZFINX-NEXT: sw a0, 4(sp)247; RV64IZFINX-NEXT: addi a0, sp, 4248; RV64IZFINX-NEXT: call notdead249; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload250; RV64IZFINX-NEXT: addi sp, sp, 16251; RV64IZFINX-NEXT: ret252 %1 = fadd float %a, %b ; force store from FPR32253 %2 = alloca float, align 4254 store float %1, ptr %2255 call void @notdead(ptr %2)256 ret void257}258