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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \5; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s6; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \7; RUN: -target-abi=ilp32 | FileCheck -check-prefix=RV32IZFINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \9; RUN: -target-abi=lp64 | FileCheck -check-prefix=RV64IZFINX %s10 11define signext i8 @test_floor_si8(float %x) {12; RV32IF-LABEL: test_floor_si8:13; RV32IF: # %bb.0:14; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn15; RV32IF-NEXT: ret16;17; RV64IF-LABEL: test_floor_si8:18; RV64IF: # %bb.0:19; RV64IF-NEXT: fcvt.l.s a0, fa0, rdn20; RV64IF-NEXT: ret21;22; RV32IZFINX-LABEL: test_floor_si8:23; RV32IZFINX: # %bb.0:24; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rdn25; RV32IZFINX-NEXT: ret26;27; RV64IZFINX-LABEL: test_floor_si8:28; RV64IZFINX: # %bb.0:29; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rdn30; RV64IZFINX-NEXT: ret31 %a = call float @llvm.floor.f32(float %x)32 %b = fptosi float %a to i833 ret i8 %b34}35 36define signext i16 @test_floor_si16(float %x) {37; RV32IF-LABEL: test_floor_si16:38; RV32IF: # %bb.0:39; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn40; RV32IF-NEXT: ret41;42; RV64IF-LABEL: test_floor_si16:43; RV64IF: # %bb.0:44; RV64IF-NEXT: fcvt.l.s a0, fa0, rdn45; RV64IF-NEXT: ret46;47; RV32IZFINX-LABEL: test_floor_si16:48; RV32IZFINX: # %bb.0:49; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rdn50; RV32IZFINX-NEXT: ret51;52; RV64IZFINX-LABEL: test_floor_si16:53; RV64IZFINX: # %bb.0:54; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rdn55; RV64IZFINX-NEXT: ret56 %a = call float @llvm.floor.f32(float %x)57 %b = fptosi float %a to i1658 ret i16 %b59}60 61define signext i32 @test_floor_si32(float %x) {62; RV32IF-LABEL: test_floor_si32:63; RV32IF: # %bb.0:64; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn65; RV32IF-NEXT: ret66;67; RV64IF-LABEL: test_floor_si32:68; RV64IF: # %bb.0:69; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn70; RV64IF-NEXT: ret71;72; RV32IZFINX-LABEL: test_floor_si32:73; RV32IZFINX: # %bb.0:74; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rdn75; RV32IZFINX-NEXT: ret76;77; RV64IZFINX-LABEL: test_floor_si32:78; RV64IZFINX: # %bb.0:79; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rdn80; RV64IZFINX-NEXT: ret81 %a = call float @llvm.floor.f32(float %x)82 %b = fptosi float %a to i3283 ret i32 %b84}85 86define i64 @test_floor_si64(float %x) {87; RV32IF-LABEL: test_floor_si64:88; RV32IF: # %bb.0:89; RV32IF-NEXT: lui a0, 30720090; RV32IF-NEXT: fmv.w.x fa5, a091; RV32IF-NEXT: fabs.s fa4, fa092; RV32IF-NEXT: flt.s a0, fa4, fa593; RV32IF-NEXT: beqz a0, .LBB3_294; RV32IF-NEXT: # %bb.1:95; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn96; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn97; RV32IF-NEXT: fsgnj.s fa0, fa5, fa098; RV32IF-NEXT: .LBB3_2:99; RV32IF-NEXT: addi sp, sp, -16100; RV32IF-NEXT: .cfi_def_cfa_offset 16101; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill102; RV32IF-NEXT: .cfi_offset ra, -4103; RV32IF-NEXT: call __fixsfdi104; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload105; RV32IF-NEXT: .cfi_restore ra106; RV32IF-NEXT: addi sp, sp, 16107; RV32IF-NEXT: .cfi_def_cfa_offset 0108; RV32IF-NEXT: ret109;110; RV64IF-LABEL: test_floor_si64:111; RV64IF: # %bb.0:112; RV64IF-NEXT: fcvt.l.s a0, fa0, rdn113; RV64IF-NEXT: ret114;115; RV32IZFINX-LABEL: test_floor_si64:116; RV32IZFINX: # %bb.0:117; RV32IZFINX-NEXT: lui a1, 307200118; RV32IZFINX-NEXT: fabs.s a2, a0119; RV32IZFINX-NEXT: flt.s a1, a2, a1120; RV32IZFINX-NEXT: beqz a1, .LBB3_2121; RV32IZFINX-NEXT: # %bb.1:122; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rdn123; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rdn124; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0125; RV32IZFINX-NEXT: .LBB3_2:126; RV32IZFINX-NEXT: addi sp, sp, -16127; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16128; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill129; RV32IZFINX-NEXT: .cfi_offset ra, -4130; RV32IZFINX-NEXT: call __fixsfdi131; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload132; RV32IZFINX-NEXT: .cfi_restore ra133; RV32IZFINX-NEXT: addi sp, sp, 16134; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0135; RV32IZFINX-NEXT: ret136;137; RV64IZFINX-LABEL: test_floor_si64:138; RV64IZFINX: # %bb.0:139; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rdn140; RV64IZFINX-NEXT: ret141 %a = call float @llvm.floor.f32(float %x)142 %b = fptosi float %a to i64143 ret i64 %b144}145 146define zeroext i8 @test_floor_ui8(float %x) {147; RV32IF-LABEL: test_floor_ui8:148; RV32IF: # %bb.0:149; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn150; RV32IF-NEXT: ret151;152; RV64IF-LABEL: test_floor_ui8:153; RV64IF: # %bb.0:154; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn155; RV64IF-NEXT: ret156;157; RV32IZFINX-LABEL: test_floor_ui8:158; RV32IZFINX: # %bb.0:159; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rdn160; RV32IZFINX-NEXT: ret161;162; RV64IZFINX-LABEL: test_floor_ui8:163; RV64IZFINX: # %bb.0:164; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rdn165; RV64IZFINX-NEXT: ret166 %a = call float @llvm.floor.f32(float %x)167 %b = fptoui float %a to i8168 ret i8 %b169}170 171define zeroext i16 @test_floor_ui16(float %x) {172; RV32IF-LABEL: test_floor_ui16:173; RV32IF: # %bb.0:174; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn175; RV32IF-NEXT: ret176;177; RV64IF-LABEL: test_floor_ui16:178; RV64IF: # %bb.0:179; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn180; RV64IF-NEXT: ret181;182; RV32IZFINX-LABEL: test_floor_ui16:183; RV32IZFINX: # %bb.0:184; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rdn185; RV32IZFINX-NEXT: ret186;187; RV64IZFINX-LABEL: test_floor_ui16:188; RV64IZFINX: # %bb.0:189; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rdn190; RV64IZFINX-NEXT: ret191 %a = call float @llvm.floor.f32(float %x)192 %b = fptoui float %a to i16193 ret i16 %b194}195 196define signext i32 @test_floor_ui32(float %x) {197; RV32IF-LABEL: test_floor_ui32:198; RV32IF: # %bb.0:199; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn200; RV32IF-NEXT: ret201;202; RV64IF-LABEL: test_floor_ui32:203; RV64IF: # %bb.0:204; RV64IF-NEXT: fcvt.wu.s a0, fa0, rdn205; RV64IF-NEXT: ret206;207; RV32IZFINX-LABEL: test_floor_ui32:208; RV32IZFINX: # %bb.0:209; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rdn210; RV32IZFINX-NEXT: ret211;212; RV64IZFINX-LABEL: test_floor_ui32:213; RV64IZFINX: # %bb.0:214; RV64IZFINX-NEXT: fcvt.wu.s a0, a0, rdn215; RV64IZFINX-NEXT: ret216 %a = call float @llvm.floor.f32(float %x)217 %b = fptoui float %a to i32218 ret i32 %b219}220 221define i64 @test_floor_ui64(float %x) {222; RV32IF-LABEL: test_floor_ui64:223; RV32IF: # %bb.0:224; RV32IF-NEXT: lui a0, 307200225; RV32IF-NEXT: fmv.w.x fa5, a0226; RV32IF-NEXT: fabs.s fa4, fa0227; RV32IF-NEXT: flt.s a0, fa4, fa5228; RV32IF-NEXT: beqz a0, .LBB7_2229; RV32IF-NEXT: # %bb.1:230; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn231; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn232; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0233; RV32IF-NEXT: .LBB7_2:234; RV32IF-NEXT: addi sp, sp, -16235; RV32IF-NEXT: .cfi_def_cfa_offset 16236; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill237; RV32IF-NEXT: .cfi_offset ra, -4238; RV32IF-NEXT: call __fixunssfdi239; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload240; RV32IF-NEXT: .cfi_restore ra241; RV32IF-NEXT: addi sp, sp, 16242; RV32IF-NEXT: .cfi_def_cfa_offset 0243; RV32IF-NEXT: ret244;245; RV64IF-LABEL: test_floor_ui64:246; RV64IF: # %bb.0:247; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn248; RV64IF-NEXT: ret249;250; RV32IZFINX-LABEL: test_floor_ui64:251; RV32IZFINX: # %bb.0:252; RV32IZFINX-NEXT: lui a1, 307200253; RV32IZFINX-NEXT: fabs.s a2, a0254; RV32IZFINX-NEXT: flt.s a1, a2, a1255; RV32IZFINX-NEXT: beqz a1, .LBB7_2256; RV32IZFINX-NEXT: # %bb.1:257; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rdn258; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rdn259; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0260; RV32IZFINX-NEXT: .LBB7_2:261; RV32IZFINX-NEXT: addi sp, sp, -16262; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16263; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill264; RV32IZFINX-NEXT: .cfi_offset ra, -4265; RV32IZFINX-NEXT: call __fixunssfdi266; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload267; RV32IZFINX-NEXT: .cfi_restore ra268; RV32IZFINX-NEXT: addi sp, sp, 16269; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0270; RV32IZFINX-NEXT: ret271;272; RV64IZFINX-LABEL: test_floor_ui64:273; RV64IZFINX: # %bb.0:274; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rdn275; RV64IZFINX-NEXT: ret276 %a = call float @llvm.floor.f32(float %x)277 %b = fptoui float %a to i64278 ret i64 %b279}280 281define signext i8 @test_ceil_si8(float %x) {282; RV32IF-LABEL: test_ceil_si8:283; RV32IF: # %bb.0:284; RV32IF-NEXT: fcvt.w.s a0, fa0, rup285; RV32IF-NEXT: ret286;287; RV64IF-LABEL: test_ceil_si8:288; RV64IF: # %bb.0:289; RV64IF-NEXT: fcvt.l.s a0, fa0, rup290; RV64IF-NEXT: ret291;292; RV32IZFINX-LABEL: test_ceil_si8:293; RV32IZFINX: # %bb.0:294; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rup295; RV32IZFINX-NEXT: ret296;297; RV64IZFINX-LABEL: test_ceil_si8:298; RV64IZFINX: # %bb.0:299; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rup300; RV64IZFINX-NEXT: ret301 %a = call float @llvm.ceil.f32(float %x)302 %b = fptosi float %a to i8303 ret i8 %b304}305 306define signext i16 @test_ceil_si16(float %x) {307; RV32IF-LABEL: test_ceil_si16:308; RV32IF: # %bb.0:309; RV32IF-NEXT: fcvt.w.s a0, fa0, rup310; RV32IF-NEXT: ret311;312; RV64IF-LABEL: test_ceil_si16:313; RV64IF: # %bb.0:314; RV64IF-NEXT: fcvt.l.s a0, fa0, rup315; RV64IF-NEXT: ret316;317; RV32IZFINX-LABEL: test_ceil_si16:318; RV32IZFINX: # %bb.0:319; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rup320; RV32IZFINX-NEXT: ret321;322; RV64IZFINX-LABEL: test_ceil_si16:323; RV64IZFINX: # %bb.0:324; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rup325; RV64IZFINX-NEXT: ret326 %a = call float @llvm.ceil.f32(float %x)327 %b = fptosi float %a to i16328 ret i16 %b329}330 331define signext i32 @test_ceil_si32(float %x) {332; RV32IF-LABEL: test_ceil_si32:333; RV32IF: # %bb.0:334; RV32IF-NEXT: fcvt.w.s a0, fa0, rup335; RV32IF-NEXT: ret336;337; RV64IF-LABEL: test_ceil_si32:338; RV64IF: # %bb.0:339; RV64IF-NEXT: fcvt.w.s a0, fa0, rup340; RV64IF-NEXT: ret341;342; RV32IZFINX-LABEL: test_ceil_si32:343; RV32IZFINX: # %bb.0:344; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rup345; RV32IZFINX-NEXT: ret346;347; RV64IZFINX-LABEL: test_ceil_si32:348; RV64IZFINX: # %bb.0:349; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rup350; RV64IZFINX-NEXT: ret351 %a = call float @llvm.ceil.f32(float %x)352 %b = fptosi float %a to i32353 ret i32 %b354}355 356define i64 @test_ceil_si64(float %x) {357; RV32IF-LABEL: test_ceil_si64:358; RV32IF: # %bb.0:359; RV32IF-NEXT: lui a0, 307200360; RV32IF-NEXT: fmv.w.x fa5, a0361; RV32IF-NEXT: fabs.s fa4, fa0362; RV32IF-NEXT: flt.s a0, fa4, fa5363; RV32IF-NEXT: beqz a0, .LBB11_2364; RV32IF-NEXT: # %bb.1:365; RV32IF-NEXT: fcvt.w.s a0, fa0, rup366; RV32IF-NEXT: fcvt.s.w fa5, a0, rup367; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0368; RV32IF-NEXT: .LBB11_2:369; RV32IF-NEXT: addi sp, sp, -16370; RV32IF-NEXT: .cfi_def_cfa_offset 16371; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill372; RV32IF-NEXT: .cfi_offset ra, -4373; RV32IF-NEXT: call __fixsfdi374; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload375; RV32IF-NEXT: .cfi_restore ra376; RV32IF-NEXT: addi sp, sp, 16377; RV32IF-NEXT: .cfi_def_cfa_offset 0378; RV32IF-NEXT: ret379;380; RV64IF-LABEL: test_ceil_si64:381; RV64IF: # %bb.0:382; RV64IF-NEXT: fcvt.l.s a0, fa0, rup383; RV64IF-NEXT: ret384;385; RV32IZFINX-LABEL: test_ceil_si64:386; RV32IZFINX: # %bb.0:387; RV32IZFINX-NEXT: lui a1, 307200388; RV32IZFINX-NEXT: fabs.s a2, a0389; RV32IZFINX-NEXT: flt.s a1, a2, a1390; RV32IZFINX-NEXT: beqz a1, .LBB11_2391; RV32IZFINX-NEXT: # %bb.1:392; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rup393; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rup394; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0395; RV32IZFINX-NEXT: .LBB11_2:396; RV32IZFINX-NEXT: addi sp, sp, -16397; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16398; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill399; RV32IZFINX-NEXT: .cfi_offset ra, -4400; RV32IZFINX-NEXT: call __fixsfdi401; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload402; RV32IZFINX-NEXT: .cfi_restore ra403; RV32IZFINX-NEXT: addi sp, sp, 16404; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0405; RV32IZFINX-NEXT: ret406;407; RV64IZFINX-LABEL: test_ceil_si64:408; RV64IZFINX: # %bb.0:409; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rup410; RV64IZFINX-NEXT: ret411 %a = call float @llvm.ceil.f32(float %x)412 %b = fptosi float %a to i64413 ret i64 %b414}415 416define zeroext i8 @test_ceil_ui8(float %x) {417; RV32IF-LABEL: test_ceil_ui8:418; RV32IF: # %bb.0:419; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup420; RV32IF-NEXT: ret421;422; RV64IF-LABEL: test_ceil_ui8:423; RV64IF: # %bb.0:424; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup425; RV64IF-NEXT: ret426;427; RV32IZFINX-LABEL: test_ceil_ui8:428; RV32IZFINX: # %bb.0:429; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rup430; RV32IZFINX-NEXT: ret431;432; RV64IZFINX-LABEL: test_ceil_ui8:433; RV64IZFINX: # %bb.0:434; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rup435; RV64IZFINX-NEXT: ret436 %a = call float @llvm.ceil.f32(float %x)437 %b = fptoui float %a to i8438 ret i8 %b439}440 441define zeroext i16 @test_ceil_ui16(float %x) {442; RV32IF-LABEL: test_ceil_ui16:443; RV32IF: # %bb.0:444; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup445; RV32IF-NEXT: ret446;447; RV64IF-LABEL: test_ceil_ui16:448; RV64IF: # %bb.0:449; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup450; RV64IF-NEXT: ret451;452; RV32IZFINX-LABEL: test_ceil_ui16:453; RV32IZFINX: # %bb.0:454; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rup455; RV32IZFINX-NEXT: ret456;457; RV64IZFINX-LABEL: test_ceil_ui16:458; RV64IZFINX: # %bb.0:459; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rup460; RV64IZFINX-NEXT: ret461 %a = call float @llvm.ceil.f32(float %x)462 %b = fptoui float %a to i16463 ret i16 %b464}465 466define signext i32 @test_ceil_ui32(float %x) {467; RV32IF-LABEL: test_ceil_ui32:468; RV32IF: # %bb.0:469; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup470; RV32IF-NEXT: ret471;472; RV64IF-LABEL: test_ceil_ui32:473; RV64IF: # %bb.0:474; RV64IF-NEXT: fcvt.wu.s a0, fa0, rup475; RV64IF-NEXT: ret476;477; RV32IZFINX-LABEL: test_ceil_ui32:478; RV32IZFINX: # %bb.0:479; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rup480; RV32IZFINX-NEXT: ret481;482; RV64IZFINX-LABEL: test_ceil_ui32:483; RV64IZFINX: # %bb.0:484; RV64IZFINX-NEXT: fcvt.wu.s a0, a0, rup485; RV64IZFINX-NEXT: ret486 %a = call float @llvm.ceil.f32(float %x)487 %b = fptoui float %a to i32488 ret i32 %b489}490 491define i64 @test_ceil_ui64(float %x) {492; RV32IF-LABEL: test_ceil_ui64:493; RV32IF: # %bb.0:494; RV32IF-NEXT: lui a0, 307200495; RV32IF-NEXT: fmv.w.x fa5, a0496; RV32IF-NEXT: fabs.s fa4, fa0497; RV32IF-NEXT: flt.s a0, fa4, fa5498; RV32IF-NEXT: beqz a0, .LBB15_2499; RV32IF-NEXT: # %bb.1:500; RV32IF-NEXT: fcvt.w.s a0, fa0, rup501; RV32IF-NEXT: fcvt.s.w fa5, a0, rup502; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0503; RV32IF-NEXT: .LBB15_2:504; RV32IF-NEXT: addi sp, sp, -16505; RV32IF-NEXT: .cfi_def_cfa_offset 16506; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill507; RV32IF-NEXT: .cfi_offset ra, -4508; RV32IF-NEXT: call __fixunssfdi509; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload510; RV32IF-NEXT: .cfi_restore ra511; RV32IF-NEXT: addi sp, sp, 16512; RV32IF-NEXT: .cfi_def_cfa_offset 0513; RV32IF-NEXT: ret514;515; RV64IF-LABEL: test_ceil_ui64:516; RV64IF: # %bb.0:517; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup518; RV64IF-NEXT: ret519;520; RV32IZFINX-LABEL: test_ceil_ui64:521; RV32IZFINX: # %bb.0:522; RV32IZFINX-NEXT: lui a1, 307200523; RV32IZFINX-NEXT: fabs.s a2, a0524; RV32IZFINX-NEXT: flt.s a1, a2, a1525; RV32IZFINX-NEXT: beqz a1, .LBB15_2526; RV32IZFINX-NEXT: # %bb.1:527; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rup528; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rup529; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0530; RV32IZFINX-NEXT: .LBB15_2:531; RV32IZFINX-NEXT: addi sp, sp, -16532; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16533; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill534; RV32IZFINX-NEXT: .cfi_offset ra, -4535; RV32IZFINX-NEXT: call __fixunssfdi536; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload537; RV32IZFINX-NEXT: .cfi_restore ra538; RV32IZFINX-NEXT: addi sp, sp, 16539; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0540; RV32IZFINX-NEXT: ret541;542; RV64IZFINX-LABEL: test_ceil_ui64:543; RV64IZFINX: # %bb.0:544; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rup545; RV64IZFINX-NEXT: ret546 %a = call float @llvm.ceil.f32(float %x)547 %b = fptoui float %a to i64548 ret i64 %b549}550 551define signext i8 @test_trunc_si8(float %x) {552; RV32IF-LABEL: test_trunc_si8:553; RV32IF: # %bb.0:554; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz555; RV32IF-NEXT: ret556;557; RV64IF-LABEL: test_trunc_si8:558; RV64IF: # %bb.0:559; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz560; RV64IF-NEXT: ret561;562; RV32IZFINX-LABEL: test_trunc_si8:563; RV32IZFINX: # %bb.0:564; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz565; RV32IZFINX-NEXT: ret566;567; RV64IZFINX-LABEL: test_trunc_si8:568; RV64IZFINX: # %bb.0:569; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz570; RV64IZFINX-NEXT: ret571 %a = call float @llvm.trunc.f32(float %x)572 %b = fptosi float %a to i8573 ret i8 %b574}575 576define signext i16 @test_trunc_si16(float %x) {577; RV32IF-LABEL: test_trunc_si16:578; RV32IF: # %bb.0:579; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz580; RV32IF-NEXT: ret581;582; RV64IF-LABEL: test_trunc_si16:583; RV64IF: # %bb.0:584; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz585; RV64IF-NEXT: ret586;587; RV32IZFINX-LABEL: test_trunc_si16:588; RV32IZFINX: # %bb.0:589; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz590; RV32IZFINX-NEXT: ret591;592; RV64IZFINX-LABEL: test_trunc_si16:593; RV64IZFINX: # %bb.0:594; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz595; RV64IZFINX-NEXT: ret596 %a = call float @llvm.trunc.f32(float %x)597 %b = fptosi float %a to i16598 ret i16 %b599}600 601define signext i32 @test_trunc_si32(float %x) {602; RV32IF-LABEL: test_trunc_si32:603; RV32IF: # %bb.0:604; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz605; RV32IF-NEXT: ret606;607; RV64IF-LABEL: test_trunc_si32:608; RV64IF: # %bb.0:609; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz610; RV64IF-NEXT: ret611;612; RV32IZFINX-LABEL: test_trunc_si32:613; RV32IZFINX: # %bb.0:614; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz615; RV32IZFINX-NEXT: ret616;617; RV64IZFINX-LABEL: test_trunc_si32:618; RV64IZFINX: # %bb.0:619; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rtz620; RV64IZFINX-NEXT: ret621 %a = call float @llvm.trunc.f32(float %x)622 %b = fptosi float %a to i32623 ret i32 %b624}625 626define i64 @test_trunc_si64(float %x) {627; RV32IF-LABEL: test_trunc_si64:628; RV32IF: # %bb.0:629; RV32IF-NEXT: lui a0, 307200630; RV32IF-NEXT: fmv.w.x fa5, a0631; RV32IF-NEXT: fabs.s fa4, fa0632; RV32IF-NEXT: flt.s a0, fa4, fa5633; RV32IF-NEXT: beqz a0, .LBB19_2634; RV32IF-NEXT: # %bb.1:635; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz636; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz637; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0638; RV32IF-NEXT: .LBB19_2:639; RV32IF-NEXT: addi sp, sp, -16640; RV32IF-NEXT: .cfi_def_cfa_offset 16641; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill642; RV32IF-NEXT: .cfi_offset ra, -4643; RV32IF-NEXT: call __fixsfdi644; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload645; RV32IF-NEXT: .cfi_restore ra646; RV32IF-NEXT: addi sp, sp, 16647; RV32IF-NEXT: .cfi_def_cfa_offset 0648; RV32IF-NEXT: ret649;650; RV64IF-LABEL: test_trunc_si64:651; RV64IF: # %bb.0:652; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz653; RV64IF-NEXT: ret654;655; RV32IZFINX-LABEL: test_trunc_si64:656; RV32IZFINX: # %bb.0:657; RV32IZFINX-NEXT: lui a1, 307200658; RV32IZFINX-NEXT: fabs.s a2, a0659; RV32IZFINX-NEXT: flt.s a1, a2, a1660; RV32IZFINX-NEXT: beqz a1, .LBB19_2661; RV32IZFINX-NEXT: # %bb.1:662; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rtz663; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rtz664; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0665; RV32IZFINX-NEXT: .LBB19_2:666; RV32IZFINX-NEXT: addi sp, sp, -16667; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16668; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill669; RV32IZFINX-NEXT: .cfi_offset ra, -4670; RV32IZFINX-NEXT: call __fixsfdi671; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload672; RV32IZFINX-NEXT: .cfi_restore ra673; RV32IZFINX-NEXT: addi sp, sp, 16674; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0675; RV32IZFINX-NEXT: ret676;677; RV64IZFINX-LABEL: test_trunc_si64:678; RV64IZFINX: # %bb.0:679; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz680; RV64IZFINX-NEXT: ret681 %a = call float @llvm.trunc.f32(float %x)682 %b = fptosi float %a to i64683 ret i64 %b684}685 686define zeroext i8 @test_trunc_ui8(float %x) {687; RV32IF-LABEL: test_trunc_ui8:688; RV32IF: # %bb.0:689; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz690; RV32IF-NEXT: ret691;692; RV64IF-LABEL: test_trunc_ui8:693; RV64IF: # %bb.0:694; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz695; RV64IF-NEXT: ret696;697; RV32IZFINX-LABEL: test_trunc_ui8:698; RV32IZFINX: # %bb.0:699; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz700; RV32IZFINX-NEXT: ret701;702; RV64IZFINX-LABEL: test_trunc_ui8:703; RV64IZFINX: # %bb.0:704; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz705; RV64IZFINX-NEXT: ret706 %a = call float @llvm.trunc.f32(float %x)707 %b = fptoui float %a to i8708 ret i8 %b709}710 711define zeroext i16 @test_trunc_ui16(float %x) {712; RV32IF-LABEL: test_trunc_ui16:713; RV32IF: # %bb.0:714; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz715; RV32IF-NEXT: ret716;717; RV64IF-LABEL: test_trunc_ui16:718; RV64IF: # %bb.0:719; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz720; RV64IF-NEXT: ret721;722; RV32IZFINX-LABEL: test_trunc_ui16:723; RV32IZFINX: # %bb.0:724; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz725; RV32IZFINX-NEXT: ret726;727; RV64IZFINX-LABEL: test_trunc_ui16:728; RV64IZFINX: # %bb.0:729; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz730; RV64IZFINX-NEXT: ret731 %a = call float @llvm.trunc.f32(float %x)732 %b = fptoui float %a to i16733 ret i16 %b734}735 736define signext i32 @test_trunc_ui32(float %x) {737; RV32IF-LABEL: test_trunc_ui32:738; RV32IF: # %bb.0:739; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz740; RV32IF-NEXT: ret741;742; RV64IF-LABEL: test_trunc_ui32:743; RV64IF: # %bb.0:744; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz745; RV64IF-NEXT: ret746;747; RV32IZFINX-LABEL: test_trunc_ui32:748; RV32IZFINX: # %bb.0:749; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz750; RV32IZFINX-NEXT: ret751;752; RV64IZFINX-LABEL: test_trunc_ui32:753; RV64IZFINX: # %bb.0:754; RV64IZFINX-NEXT: fcvt.wu.s a0, a0, rtz755; RV64IZFINX-NEXT: ret756 %a = call float @llvm.trunc.f32(float %x)757 %b = fptoui float %a to i32758 ret i32 %b759}760 761define i64 @test_trunc_ui64(float %x) {762; RV32IF-LABEL: test_trunc_ui64:763; RV32IF: # %bb.0:764; RV32IF-NEXT: lui a0, 307200765; RV32IF-NEXT: fmv.w.x fa5, a0766; RV32IF-NEXT: fabs.s fa4, fa0767; RV32IF-NEXT: flt.s a0, fa4, fa5768; RV32IF-NEXT: beqz a0, .LBB23_2769; RV32IF-NEXT: # %bb.1:770; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz771; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz772; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0773; RV32IF-NEXT: .LBB23_2:774; RV32IF-NEXT: addi sp, sp, -16775; RV32IF-NEXT: .cfi_def_cfa_offset 16776; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill777; RV32IF-NEXT: .cfi_offset ra, -4778; RV32IF-NEXT: call __fixunssfdi779; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload780; RV32IF-NEXT: .cfi_restore ra781; RV32IF-NEXT: addi sp, sp, 16782; RV32IF-NEXT: .cfi_def_cfa_offset 0783; RV32IF-NEXT: ret784;785; RV64IF-LABEL: test_trunc_ui64:786; RV64IF: # %bb.0:787; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz788; RV64IF-NEXT: ret789;790; RV32IZFINX-LABEL: test_trunc_ui64:791; RV32IZFINX: # %bb.0:792; RV32IZFINX-NEXT: lui a1, 307200793; RV32IZFINX-NEXT: fabs.s a2, a0794; RV32IZFINX-NEXT: flt.s a1, a2, a1795; RV32IZFINX-NEXT: beqz a1, .LBB23_2796; RV32IZFINX-NEXT: # %bb.1:797; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rtz798; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rtz799; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0800; RV32IZFINX-NEXT: .LBB23_2:801; RV32IZFINX-NEXT: addi sp, sp, -16802; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16803; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill804; RV32IZFINX-NEXT: .cfi_offset ra, -4805; RV32IZFINX-NEXT: call __fixunssfdi806; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload807; RV32IZFINX-NEXT: .cfi_restore ra808; RV32IZFINX-NEXT: addi sp, sp, 16809; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0810; RV32IZFINX-NEXT: ret811;812; RV64IZFINX-LABEL: test_trunc_ui64:813; RV64IZFINX: # %bb.0:814; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz815; RV64IZFINX-NEXT: ret816 %a = call float @llvm.trunc.f32(float %x)817 %b = fptoui float %a to i64818 ret i64 %b819}820 821define signext i8 @test_round_si8(float %x) {822; RV32IF-LABEL: test_round_si8:823; RV32IF: # %bb.0:824; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm825; RV32IF-NEXT: ret826;827; RV64IF-LABEL: test_round_si8:828; RV64IF: # %bb.0:829; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm830; RV64IF-NEXT: ret831;832; RV32IZFINX-LABEL: test_round_si8:833; RV32IZFINX: # %bb.0:834; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm835; RV32IZFINX-NEXT: ret836;837; RV64IZFINX-LABEL: test_round_si8:838; RV64IZFINX: # %bb.0:839; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm840; RV64IZFINX-NEXT: ret841 %a = call float @llvm.round.f32(float %x)842 %b = fptosi float %a to i8843 ret i8 %b844}845 846define signext i16 @test_round_si16(float %x) {847; RV32IF-LABEL: test_round_si16:848; RV32IF: # %bb.0:849; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm850; RV32IF-NEXT: ret851;852; RV64IF-LABEL: test_round_si16:853; RV64IF: # %bb.0:854; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm855; RV64IF-NEXT: ret856;857; RV32IZFINX-LABEL: test_round_si16:858; RV32IZFINX: # %bb.0:859; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm860; RV32IZFINX-NEXT: ret861;862; RV64IZFINX-LABEL: test_round_si16:863; RV64IZFINX: # %bb.0:864; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm865; RV64IZFINX-NEXT: ret866 %a = call float @llvm.round.f32(float %x)867 %b = fptosi float %a to i16868 ret i16 %b869}870 871define signext i32 @test_round_si32(float %x) {872; RV32IF-LABEL: test_round_si32:873; RV32IF: # %bb.0:874; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm875; RV32IF-NEXT: ret876;877; RV64IF-LABEL: test_round_si32:878; RV64IF: # %bb.0:879; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm880; RV64IF-NEXT: ret881;882; RV32IZFINX-LABEL: test_round_si32:883; RV32IZFINX: # %bb.0:884; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm885; RV32IZFINX-NEXT: ret886;887; RV64IZFINX-LABEL: test_round_si32:888; RV64IZFINX: # %bb.0:889; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rmm890; RV64IZFINX-NEXT: ret891 %a = call float @llvm.round.f32(float %x)892 %b = fptosi float %a to i32893 ret i32 %b894}895 896define i64 @test_round_si64(float %x) {897; RV32IF-LABEL: test_round_si64:898; RV32IF: # %bb.0:899; RV32IF-NEXT: lui a0, 307200900; RV32IF-NEXT: fmv.w.x fa5, a0901; RV32IF-NEXT: fabs.s fa4, fa0902; RV32IF-NEXT: flt.s a0, fa4, fa5903; RV32IF-NEXT: beqz a0, .LBB27_2904; RV32IF-NEXT: # %bb.1:905; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm906; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm907; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0908; RV32IF-NEXT: .LBB27_2:909; RV32IF-NEXT: addi sp, sp, -16910; RV32IF-NEXT: .cfi_def_cfa_offset 16911; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill912; RV32IF-NEXT: .cfi_offset ra, -4913; RV32IF-NEXT: call __fixsfdi914; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload915; RV32IF-NEXT: .cfi_restore ra916; RV32IF-NEXT: addi sp, sp, 16917; RV32IF-NEXT: .cfi_def_cfa_offset 0918; RV32IF-NEXT: ret919;920; RV64IF-LABEL: test_round_si64:921; RV64IF: # %bb.0:922; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm923; RV64IF-NEXT: ret924;925; RV32IZFINX-LABEL: test_round_si64:926; RV32IZFINX: # %bb.0:927; RV32IZFINX-NEXT: lui a1, 307200928; RV32IZFINX-NEXT: fabs.s a2, a0929; RV32IZFINX-NEXT: flt.s a1, a2, a1930; RV32IZFINX-NEXT: beqz a1, .LBB27_2931; RV32IZFINX-NEXT: # %bb.1:932; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rmm933; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rmm934; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0935; RV32IZFINX-NEXT: .LBB27_2:936; RV32IZFINX-NEXT: addi sp, sp, -16937; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16938; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill939; RV32IZFINX-NEXT: .cfi_offset ra, -4940; RV32IZFINX-NEXT: call __fixsfdi941; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload942; RV32IZFINX-NEXT: .cfi_restore ra943; RV32IZFINX-NEXT: addi sp, sp, 16944; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0945; RV32IZFINX-NEXT: ret946;947; RV64IZFINX-LABEL: test_round_si64:948; RV64IZFINX: # %bb.0:949; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm950; RV64IZFINX-NEXT: ret951 %a = call float @llvm.round.f32(float %x)952 %b = fptosi float %a to i64953 ret i64 %b954}955 956define zeroext i8 @test_round_ui8(float %x) {957; RV32IF-LABEL: test_round_ui8:958; RV32IF: # %bb.0:959; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm960; RV32IF-NEXT: ret961;962; RV64IF-LABEL: test_round_ui8:963; RV64IF: # %bb.0:964; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm965; RV64IF-NEXT: ret966;967; RV32IZFINX-LABEL: test_round_ui8:968; RV32IZFINX: # %bb.0:969; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rmm970; RV32IZFINX-NEXT: ret971;972; RV64IZFINX-LABEL: test_round_ui8:973; RV64IZFINX: # %bb.0:974; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rmm975; RV64IZFINX-NEXT: ret976 %a = call float @llvm.round.f32(float %x)977 %b = fptoui float %a to i8978 ret i8 %b979}980 981define zeroext i16 @test_round_ui16(float %x) {982; RV32IF-LABEL: test_round_ui16:983; RV32IF: # %bb.0:984; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm985; RV32IF-NEXT: ret986;987; RV64IF-LABEL: test_round_ui16:988; RV64IF: # %bb.0:989; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm990; RV64IF-NEXT: ret991;992; RV32IZFINX-LABEL: test_round_ui16:993; RV32IZFINX: # %bb.0:994; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rmm995; RV32IZFINX-NEXT: ret996;997; RV64IZFINX-LABEL: test_round_ui16:998; RV64IZFINX: # %bb.0:999; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rmm1000; RV64IZFINX-NEXT: ret1001 %a = call float @llvm.round.f32(float %x)1002 %b = fptoui float %a to i161003 ret i16 %b1004}1005 1006define signext i32 @test_round_ui32(float %x) {1007; RV32IF-LABEL: test_round_ui32:1008; RV32IF: # %bb.0:1009; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm1010; RV32IF-NEXT: ret1011;1012; RV64IF-LABEL: test_round_ui32:1013; RV64IF: # %bb.0:1014; RV64IF-NEXT: fcvt.wu.s a0, fa0, rmm1015; RV64IF-NEXT: ret1016;1017; RV32IZFINX-LABEL: test_round_ui32:1018; RV32IZFINX: # %bb.0:1019; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rmm1020; RV32IZFINX-NEXT: ret1021;1022; RV64IZFINX-LABEL: test_round_ui32:1023; RV64IZFINX: # %bb.0:1024; RV64IZFINX-NEXT: fcvt.wu.s a0, a0, rmm1025; RV64IZFINX-NEXT: ret1026 %a = call float @llvm.round.f32(float %x)1027 %b = fptoui float %a to i321028 ret i32 %b1029}1030 1031define i64 @test_round_ui64(float %x) {1032; RV32IF-LABEL: test_round_ui64:1033; RV32IF: # %bb.0:1034; RV32IF-NEXT: lui a0, 3072001035; RV32IF-NEXT: fmv.w.x fa5, a01036; RV32IF-NEXT: fabs.s fa4, fa01037; RV32IF-NEXT: flt.s a0, fa4, fa51038; RV32IF-NEXT: beqz a0, .LBB31_21039; RV32IF-NEXT: # %bb.1:1040; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm1041; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm1042; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01043; RV32IF-NEXT: .LBB31_2:1044; RV32IF-NEXT: addi sp, sp, -161045; RV32IF-NEXT: .cfi_def_cfa_offset 161046; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1047; RV32IF-NEXT: .cfi_offset ra, -41048; RV32IF-NEXT: call __fixunssfdi1049; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1050; RV32IF-NEXT: .cfi_restore ra1051; RV32IF-NEXT: addi sp, sp, 161052; RV32IF-NEXT: .cfi_def_cfa_offset 01053; RV32IF-NEXT: ret1054;1055; RV64IF-LABEL: test_round_ui64:1056; RV64IF: # %bb.0:1057; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm1058; RV64IF-NEXT: ret1059;1060; RV32IZFINX-LABEL: test_round_ui64:1061; RV32IZFINX: # %bb.0:1062; RV32IZFINX-NEXT: lui a1, 3072001063; RV32IZFINX-NEXT: fabs.s a2, a01064; RV32IZFINX-NEXT: flt.s a1, a2, a11065; RV32IZFINX-NEXT: beqz a1, .LBB31_21066; RV32IZFINX-NEXT: # %bb.1:1067; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rmm1068; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rmm1069; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01070; RV32IZFINX-NEXT: .LBB31_2:1071; RV32IZFINX-NEXT: addi sp, sp, -161072; RV32IZFINX-NEXT: .cfi_def_cfa_offset 161073; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1074; RV32IZFINX-NEXT: .cfi_offset ra, -41075; RV32IZFINX-NEXT: call __fixunssfdi1076; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1077; RV32IZFINX-NEXT: .cfi_restore ra1078; RV32IZFINX-NEXT: addi sp, sp, 161079; RV32IZFINX-NEXT: .cfi_def_cfa_offset 01080; RV32IZFINX-NEXT: ret1081;1082; RV64IZFINX-LABEL: test_round_ui64:1083; RV64IZFINX: # %bb.0:1084; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rmm1085; RV64IZFINX-NEXT: ret1086 %a = call float @llvm.round.f32(float %x)1087 %b = fptoui float %a to i641088 ret i64 %b1089}1090 1091define signext i8 @test_roundeven_si8(float %x) {1092; RV32IF-LABEL: test_roundeven_si8:1093; RV32IF: # %bb.0:1094; RV32IF-NEXT: fcvt.w.s a0, fa0, rne1095; RV32IF-NEXT: ret1096;1097; RV64IF-LABEL: test_roundeven_si8:1098; RV64IF: # %bb.0:1099; RV64IF-NEXT: fcvt.l.s a0, fa0, rne1100; RV64IF-NEXT: ret1101;1102; RV32IZFINX-LABEL: test_roundeven_si8:1103; RV32IZFINX: # %bb.0:1104; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rne1105; RV32IZFINX-NEXT: ret1106;1107; RV64IZFINX-LABEL: test_roundeven_si8:1108; RV64IZFINX: # %bb.0:1109; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rne1110; RV64IZFINX-NEXT: ret1111 %a = call float @llvm.roundeven.f32(float %x)1112 %b = fptosi float %a to i81113 ret i8 %b1114}1115 1116define signext i16 @test_roundeven_si16(float %x) {1117; RV32IF-LABEL: test_roundeven_si16:1118; RV32IF: # %bb.0:1119; RV32IF-NEXT: fcvt.w.s a0, fa0, rne1120; RV32IF-NEXT: ret1121;1122; RV64IF-LABEL: test_roundeven_si16:1123; RV64IF: # %bb.0:1124; RV64IF-NEXT: fcvt.l.s a0, fa0, rne1125; RV64IF-NEXT: ret1126;1127; RV32IZFINX-LABEL: test_roundeven_si16:1128; RV32IZFINX: # %bb.0:1129; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rne1130; RV32IZFINX-NEXT: ret1131;1132; RV64IZFINX-LABEL: test_roundeven_si16:1133; RV64IZFINX: # %bb.0:1134; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rne1135; RV64IZFINX-NEXT: ret1136 %a = call float @llvm.roundeven.f32(float %x)1137 %b = fptosi float %a to i161138 ret i16 %b1139}1140 1141define signext i32 @test_roundeven_si32(float %x) {1142; RV32IF-LABEL: test_roundeven_si32:1143; RV32IF: # %bb.0:1144; RV32IF-NEXT: fcvt.w.s a0, fa0, rne1145; RV32IF-NEXT: ret1146;1147; RV64IF-LABEL: test_roundeven_si32:1148; RV64IF: # %bb.0:1149; RV64IF-NEXT: fcvt.w.s a0, fa0, rne1150; RV64IF-NEXT: ret1151;1152; RV32IZFINX-LABEL: test_roundeven_si32:1153; RV32IZFINX: # %bb.0:1154; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rne1155; RV32IZFINX-NEXT: ret1156;1157; RV64IZFINX-LABEL: test_roundeven_si32:1158; RV64IZFINX: # %bb.0:1159; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rne1160; RV64IZFINX-NEXT: ret1161 %a = call float @llvm.roundeven.f32(float %x)1162 %b = fptosi float %a to i321163 ret i32 %b1164}1165 1166define i64 @test_roundeven_si64(float %x) {1167; RV32IF-LABEL: test_roundeven_si64:1168; RV32IF: # %bb.0:1169; RV32IF-NEXT: lui a0, 3072001170; RV32IF-NEXT: fmv.w.x fa5, a01171; RV32IF-NEXT: fabs.s fa4, fa01172; RV32IF-NEXT: flt.s a0, fa4, fa51173; RV32IF-NEXT: beqz a0, .LBB35_21174; RV32IF-NEXT: # %bb.1:1175; RV32IF-NEXT: fcvt.w.s a0, fa0, rne1176; RV32IF-NEXT: fcvt.s.w fa5, a0, rne1177; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01178; RV32IF-NEXT: .LBB35_2:1179; RV32IF-NEXT: addi sp, sp, -161180; RV32IF-NEXT: .cfi_def_cfa_offset 161181; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1182; RV32IF-NEXT: .cfi_offset ra, -41183; RV32IF-NEXT: call __fixsfdi1184; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1185; RV32IF-NEXT: .cfi_restore ra1186; RV32IF-NEXT: addi sp, sp, 161187; RV32IF-NEXT: .cfi_def_cfa_offset 01188; RV32IF-NEXT: ret1189;1190; RV64IF-LABEL: test_roundeven_si64:1191; RV64IF: # %bb.0:1192; RV64IF-NEXT: fcvt.l.s a0, fa0, rne1193; RV64IF-NEXT: ret1194;1195; RV32IZFINX-LABEL: test_roundeven_si64:1196; RV32IZFINX: # %bb.0:1197; RV32IZFINX-NEXT: lui a1, 3072001198; RV32IZFINX-NEXT: fabs.s a2, a01199; RV32IZFINX-NEXT: flt.s a1, a2, a11200; RV32IZFINX-NEXT: beqz a1, .LBB35_21201; RV32IZFINX-NEXT: # %bb.1:1202; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rne1203; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rne1204; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01205; RV32IZFINX-NEXT: .LBB35_2:1206; RV32IZFINX-NEXT: addi sp, sp, -161207; RV32IZFINX-NEXT: .cfi_def_cfa_offset 161208; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1209; RV32IZFINX-NEXT: .cfi_offset ra, -41210; RV32IZFINX-NEXT: call __fixsfdi1211; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1212; RV32IZFINX-NEXT: .cfi_restore ra1213; RV32IZFINX-NEXT: addi sp, sp, 161214; RV32IZFINX-NEXT: .cfi_def_cfa_offset 01215; RV32IZFINX-NEXT: ret1216;1217; RV64IZFINX-LABEL: test_roundeven_si64:1218; RV64IZFINX: # %bb.0:1219; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rne1220; RV64IZFINX-NEXT: ret1221 %a = call float @llvm.roundeven.f32(float %x)1222 %b = fptosi float %a to i641223 ret i64 %b1224}1225 1226define zeroext i8 @test_roundeven_ui8(float %x) {1227; RV32IF-LABEL: test_roundeven_ui8:1228; RV32IF: # %bb.0:1229; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne1230; RV32IF-NEXT: ret1231;1232; RV64IF-LABEL: test_roundeven_ui8:1233; RV64IF: # %bb.0:1234; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne1235; RV64IF-NEXT: ret1236;1237; RV32IZFINX-LABEL: test_roundeven_ui8:1238; RV32IZFINX: # %bb.0:1239; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rne1240; RV32IZFINX-NEXT: ret1241;1242; RV64IZFINX-LABEL: test_roundeven_ui8:1243; RV64IZFINX: # %bb.0:1244; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rne1245; RV64IZFINX-NEXT: ret1246 %a = call float @llvm.roundeven.f32(float %x)1247 %b = fptoui float %a to i81248 ret i8 %b1249}1250 1251define zeroext i16 @test_roundeven_ui16(float %x) {1252; RV32IF-LABEL: test_roundeven_ui16:1253; RV32IF: # %bb.0:1254; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne1255; RV32IF-NEXT: ret1256;1257; RV64IF-LABEL: test_roundeven_ui16:1258; RV64IF: # %bb.0:1259; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne1260; RV64IF-NEXT: ret1261;1262; RV32IZFINX-LABEL: test_roundeven_ui16:1263; RV32IZFINX: # %bb.0:1264; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rne1265; RV32IZFINX-NEXT: ret1266;1267; RV64IZFINX-LABEL: test_roundeven_ui16:1268; RV64IZFINX: # %bb.0:1269; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rne1270; RV64IZFINX-NEXT: ret1271 %a = call float @llvm.roundeven.f32(float %x)1272 %b = fptoui float %a to i161273 ret i16 %b1274}1275 1276define signext i32 @test_roundeven_ui32(float %x) {1277; RV32IF-LABEL: test_roundeven_ui32:1278; RV32IF: # %bb.0:1279; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne1280; RV32IF-NEXT: ret1281;1282; RV64IF-LABEL: test_roundeven_ui32:1283; RV64IF: # %bb.0:1284; RV64IF-NEXT: fcvt.wu.s a0, fa0, rne1285; RV64IF-NEXT: ret1286;1287; RV32IZFINX-LABEL: test_roundeven_ui32:1288; RV32IZFINX: # %bb.0:1289; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rne1290; RV32IZFINX-NEXT: ret1291;1292; RV64IZFINX-LABEL: test_roundeven_ui32:1293; RV64IZFINX: # %bb.0:1294; RV64IZFINX-NEXT: fcvt.wu.s a0, a0, rne1295; RV64IZFINX-NEXT: ret1296 %a = call float @llvm.roundeven.f32(float %x)1297 %b = fptoui float %a to i321298 ret i32 %b1299}1300 1301define i64 @test_roundeven_ui64(float %x) {1302; RV32IF-LABEL: test_roundeven_ui64:1303; RV32IF: # %bb.0:1304; RV32IF-NEXT: lui a0, 3072001305; RV32IF-NEXT: fmv.w.x fa5, a01306; RV32IF-NEXT: fabs.s fa4, fa01307; RV32IF-NEXT: flt.s a0, fa4, fa51308; RV32IF-NEXT: beqz a0, .LBB39_21309; RV32IF-NEXT: # %bb.1:1310; RV32IF-NEXT: fcvt.w.s a0, fa0, rne1311; RV32IF-NEXT: fcvt.s.w fa5, a0, rne1312; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01313; RV32IF-NEXT: .LBB39_2:1314; RV32IF-NEXT: addi sp, sp, -161315; RV32IF-NEXT: .cfi_def_cfa_offset 161316; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1317; RV32IF-NEXT: .cfi_offset ra, -41318; RV32IF-NEXT: call __fixunssfdi1319; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1320; RV32IF-NEXT: .cfi_restore ra1321; RV32IF-NEXT: addi sp, sp, 161322; RV32IF-NEXT: .cfi_def_cfa_offset 01323; RV32IF-NEXT: ret1324;1325; RV64IF-LABEL: test_roundeven_ui64:1326; RV64IF: # %bb.0:1327; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne1328; RV64IF-NEXT: ret1329;1330; RV32IZFINX-LABEL: test_roundeven_ui64:1331; RV32IZFINX: # %bb.0:1332; RV32IZFINX-NEXT: lui a1, 3072001333; RV32IZFINX-NEXT: fabs.s a2, a01334; RV32IZFINX-NEXT: flt.s a1, a2, a11335; RV32IZFINX-NEXT: beqz a1, .LBB39_21336; RV32IZFINX-NEXT: # %bb.1:1337; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rne1338; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rne1339; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01340; RV32IZFINX-NEXT: .LBB39_2:1341; RV32IZFINX-NEXT: addi sp, sp, -161342; RV32IZFINX-NEXT: .cfi_def_cfa_offset 161343; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1344; RV32IZFINX-NEXT: .cfi_offset ra, -41345; RV32IZFINX-NEXT: call __fixunssfdi1346; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1347; RV32IZFINX-NEXT: .cfi_restore ra1348; RV32IZFINX-NEXT: addi sp, sp, 161349; RV32IZFINX-NEXT: .cfi_def_cfa_offset 01350; RV32IZFINX-NEXT: ret1351;1352; RV64IZFINX-LABEL: test_roundeven_ui64:1353; RV64IZFINX: # %bb.0:1354; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rne1355; RV64IZFINX-NEXT: ret1356 %a = call float @llvm.roundeven.f32(float %x)1357 %b = fptoui float %a to i641358 ret i64 %b1359}1360 1361define float @test_floor_float(float %x) {1362; RV32IFD-LABEL: test_floor_float:1363; RV32IFD: # %bb.0:1364; RV32IFD-NEXT: addi sp, sp, -161365; RV32IFD-NEXT: .cfi_def_cfa_offset 161366; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1367; RV32IFD-NEXT: .cfi_offset ra, -41368; RV32IFD-NEXT: call floor@plt1369; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1370; RV32IFD-NEXT: addi sp, sp, 161371; RV32IFD-NEXT: ret1372;1373; RV64IFD-LABEL: test_floor_float:1374; RV64IFD: # %bb.0:1375; RV64IFD-NEXT: addi sp, sp, -161376; RV64IFD-NEXT: .cfi_def_cfa_offset 161377; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1378; RV64IFD-NEXT: .cfi_offset ra, -81379; RV64IFD-NEXT: call floor@plt1380; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1381; RV64IFD-NEXT: addi sp, sp, 161382; RV64IFD-NEXT: ret1383; RV32IF-LABEL: test_floor_float:1384; RV32IF: # %bb.0:1385; RV32IF-NEXT: lui a0, 3072001386; RV32IF-NEXT: fmv.w.x fa5, a01387; RV32IF-NEXT: fabs.s fa4, fa01388; RV32IF-NEXT: flt.s a0, fa4, fa51389; RV32IF-NEXT: beqz a0, .LBB40_21390; RV32IF-NEXT: # %bb.1:1391; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn1392; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn1393; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01394; RV32IF-NEXT: .LBB40_2:1395; RV32IF-NEXT: ret1396;1397; RV64IF-LABEL: test_floor_float:1398; RV64IF: # %bb.0:1399; RV64IF-NEXT: lui a0, 3072001400; RV64IF-NEXT: fmv.w.x fa5, a01401; RV64IF-NEXT: fabs.s fa4, fa01402; RV64IF-NEXT: flt.s a0, fa4, fa51403; RV64IF-NEXT: beqz a0, .LBB40_21404; RV64IF-NEXT: # %bb.1:1405; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn1406; RV64IF-NEXT: fcvt.s.w fa5, a0, rdn1407; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01408; RV64IF-NEXT: .LBB40_2:1409; RV64IF-NEXT: ret1410;1411; RV32IZFINX-LABEL: test_floor_float:1412; RV32IZFINX: # %bb.0:1413; RV32IZFINX-NEXT: lui a1, 3072001414; RV32IZFINX-NEXT: fabs.s a2, a01415; RV32IZFINX-NEXT: flt.s a1, a2, a11416; RV32IZFINX-NEXT: beqz a1, .LBB40_21417; RV32IZFINX-NEXT: # %bb.1:1418; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rdn1419; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rdn1420; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01421; RV32IZFINX-NEXT: .LBB40_2:1422; RV32IZFINX-NEXT: ret1423;1424; RV64IZFINX-LABEL: test_floor_float:1425; RV64IZFINX: # %bb.0:1426; RV64IZFINX-NEXT: lui a1, 3072001427; RV64IZFINX-NEXT: fabs.s a2, a01428; RV64IZFINX-NEXT: flt.s a1, a2, a11429; RV64IZFINX-NEXT: beqz a1, .LBB40_21430; RV64IZFINX-NEXT: # %bb.1:1431; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rdn1432; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rdn1433; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01434; RV64IZFINX-NEXT: .LBB40_2:1435; RV64IZFINX-NEXT: ret1436 %a = call float @llvm.floor.f32(float %x)1437 ret float %a1438}1439 1440define float @test_ceil_float(float %x) {1441; RV32IFD-LABEL: test_ceil_float:1442; RV32IFD: # %bb.0:1443; RV32IFD-NEXT: addi sp, sp, -161444; RV32IFD-NEXT: .cfi_def_cfa_offset 161445; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1446; RV32IFD-NEXT: .cfi_offset ra, -41447; RV32IFD-NEXT: call ceil@plt1448; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1449; RV32IFD-NEXT: addi sp, sp, 161450; RV32IFD-NEXT: ret1451;1452; RV64IFD-LABEL: test_ceil_float:1453; RV64IFD: # %bb.0:1454; RV64IFD-NEXT: addi sp, sp, -161455; RV64IFD-NEXT: .cfi_def_cfa_offset 161456; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1457; RV64IFD-NEXT: .cfi_offset ra, -81458; RV64IFD-NEXT: call ceil@plt1459; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1460; RV64IFD-NEXT: addi sp, sp, 161461; RV64IFD-NEXT: ret1462; RV32IF-LABEL: test_ceil_float:1463; RV32IF: # %bb.0:1464; RV32IF-NEXT: lui a0, 3072001465; RV32IF-NEXT: fmv.w.x fa5, a01466; RV32IF-NEXT: fabs.s fa4, fa01467; RV32IF-NEXT: flt.s a0, fa4, fa51468; RV32IF-NEXT: beqz a0, .LBB41_21469; RV32IF-NEXT: # %bb.1:1470; RV32IF-NEXT: fcvt.w.s a0, fa0, rup1471; RV32IF-NEXT: fcvt.s.w fa5, a0, rup1472; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01473; RV32IF-NEXT: .LBB41_2:1474; RV32IF-NEXT: ret1475;1476; RV64IF-LABEL: test_ceil_float:1477; RV64IF: # %bb.0:1478; RV64IF-NEXT: lui a0, 3072001479; RV64IF-NEXT: fmv.w.x fa5, a01480; RV64IF-NEXT: fabs.s fa4, fa01481; RV64IF-NEXT: flt.s a0, fa4, fa51482; RV64IF-NEXT: beqz a0, .LBB41_21483; RV64IF-NEXT: # %bb.1:1484; RV64IF-NEXT: fcvt.w.s a0, fa0, rup1485; RV64IF-NEXT: fcvt.s.w fa5, a0, rup1486; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01487; RV64IF-NEXT: .LBB41_2:1488; RV64IF-NEXT: ret1489;1490; RV32IZFINX-LABEL: test_ceil_float:1491; RV32IZFINX: # %bb.0:1492; RV32IZFINX-NEXT: lui a1, 3072001493; RV32IZFINX-NEXT: fabs.s a2, a01494; RV32IZFINX-NEXT: flt.s a1, a2, a11495; RV32IZFINX-NEXT: beqz a1, .LBB41_21496; RV32IZFINX-NEXT: # %bb.1:1497; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rup1498; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rup1499; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01500; RV32IZFINX-NEXT: .LBB41_2:1501; RV32IZFINX-NEXT: ret1502;1503; RV64IZFINX-LABEL: test_ceil_float:1504; RV64IZFINX: # %bb.0:1505; RV64IZFINX-NEXT: lui a1, 3072001506; RV64IZFINX-NEXT: fabs.s a2, a01507; RV64IZFINX-NEXT: flt.s a1, a2, a11508; RV64IZFINX-NEXT: beqz a1, .LBB41_21509; RV64IZFINX-NEXT: # %bb.1:1510; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rup1511; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rup1512; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01513; RV64IZFINX-NEXT: .LBB41_2:1514; RV64IZFINX-NEXT: ret1515 %a = call float @llvm.ceil.f32(float %x)1516 ret float %a1517}1518 1519define float @test_trunc_float(float %x) {1520; RV32IFD-LABEL: test_trunc_float:1521; RV32IFD: # %bb.0:1522; RV32IFD-NEXT: addi sp, sp, -161523; RV32IFD-NEXT: .cfi_def_cfa_offset 161524; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1525; RV32IFD-NEXT: .cfi_offset ra, -41526; RV32IFD-NEXT: call trunc@plt1527; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1528; RV32IFD-NEXT: addi sp, sp, 161529; RV32IFD-NEXT: ret1530;1531; RV64IFD-LABEL: test_trunc_float:1532; RV64IFD: # %bb.0:1533; RV64IFD-NEXT: addi sp, sp, -161534; RV64IFD-NEXT: .cfi_def_cfa_offset 161535; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1536; RV64IFD-NEXT: .cfi_offset ra, -81537; RV64IFD-NEXT: call trunc@plt1538; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1539; RV64IFD-NEXT: addi sp, sp, 161540; RV64IFD-NEXT: ret1541; RV32IF-LABEL: test_trunc_float:1542; RV32IF: # %bb.0:1543; RV32IF-NEXT: lui a0, 3072001544; RV32IF-NEXT: fmv.w.x fa5, a01545; RV32IF-NEXT: fabs.s fa4, fa01546; RV32IF-NEXT: flt.s a0, fa4, fa51547; RV32IF-NEXT: beqz a0, .LBB42_21548; RV32IF-NEXT: # %bb.1:1549; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz1550; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz1551; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01552; RV32IF-NEXT: .LBB42_2:1553; RV32IF-NEXT: ret1554;1555; RV64IF-LABEL: test_trunc_float:1556; RV64IF: # %bb.0:1557; RV64IF-NEXT: lui a0, 3072001558; RV64IF-NEXT: fmv.w.x fa5, a01559; RV64IF-NEXT: fabs.s fa4, fa01560; RV64IF-NEXT: flt.s a0, fa4, fa51561; RV64IF-NEXT: beqz a0, .LBB42_21562; RV64IF-NEXT: # %bb.1:1563; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz1564; RV64IF-NEXT: fcvt.s.w fa5, a0, rtz1565; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01566; RV64IF-NEXT: .LBB42_2:1567; RV64IF-NEXT: ret1568;1569; RV32IZFINX-LABEL: test_trunc_float:1570; RV32IZFINX: # %bb.0:1571; RV32IZFINX-NEXT: lui a1, 3072001572; RV32IZFINX-NEXT: fabs.s a2, a01573; RV32IZFINX-NEXT: flt.s a1, a2, a11574; RV32IZFINX-NEXT: beqz a1, .LBB42_21575; RV32IZFINX-NEXT: # %bb.1:1576; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rtz1577; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rtz1578; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01579; RV32IZFINX-NEXT: .LBB42_2:1580; RV32IZFINX-NEXT: ret1581;1582; RV64IZFINX-LABEL: test_trunc_float:1583; RV64IZFINX: # %bb.0:1584; RV64IZFINX-NEXT: lui a1, 3072001585; RV64IZFINX-NEXT: fabs.s a2, a01586; RV64IZFINX-NEXT: flt.s a1, a2, a11587; RV64IZFINX-NEXT: beqz a1, .LBB42_21588; RV64IZFINX-NEXT: # %bb.1:1589; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rtz1590; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rtz1591; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01592; RV64IZFINX-NEXT: .LBB42_2:1593; RV64IZFINX-NEXT: ret1594 %a = call float @llvm.trunc.f32(float %x)1595 ret float %a1596}1597 1598define float @test_round_float(float %x) {1599; RV32IFD-LABEL: test_round_float:1600; RV32IFD: # %bb.0:1601; RV32IFD-NEXT: addi sp, sp, -161602; RV32IFD-NEXT: .cfi_def_cfa_offset 161603; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1604; RV32IFD-NEXT: .cfi_offset ra, -41605; RV32IFD-NEXT: call round@plt1606; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1607; RV32IFD-NEXT: addi sp, sp, 161608; RV32IFD-NEXT: ret1609;1610; RV64IFD-LABEL: test_round_float:1611; RV64IFD: # %bb.0:1612; RV64IFD-NEXT: addi sp, sp, -161613; RV64IFD-NEXT: .cfi_def_cfa_offset 161614; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1615; RV64IFD-NEXT: .cfi_offset ra, -81616; RV64IFD-NEXT: call round@plt1617; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1618; RV64IFD-NEXT: addi sp, sp, 161619; RV64IFD-NEXT: ret1620; RV32IF-LABEL: test_round_float:1621; RV32IF: # %bb.0:1622; RV32IF-NEXT: lui a0, 3072001623; RV32IF-NEXT: fmv.w.x fa5, a01624; RV32IF-NEXT: fabs.s fa4, fa01625; RV32IF-NEXT: flt.s a0, fa4, fa51626; RV32IF-NEXT: beqz a0, .LBB43_21627; RV32IF-NEXT: # %bb.1:1628; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm1629; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm1630; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01631; RV32IF-NEXT: .LBB43_2:1632; RV32IF-NEXT: ret1633;1634; RV64IF-LABEL: test_round_float:1635; RV64IF: # %bb.0:1636; RV64IF-NEXT: lui a0, 3072001637; RV64IF-NEXT: fmv.w.x fa5, a01638; RV64IF-NEXT: fabs.s fa4, fa01639; RV64IF-NEXT: flt.s a0, fa4, fa51640; RV64IF-NEXT: beqz a0, .LBB43_21641; RV64IF-NEXT: # %bb.1:1642; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm1643; RV64IF-NEXT: fcvt.s.w fa5, a0, rmm1644; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01645; RV64IF-NEXT: .LBB43_2:1646; RV64IF-NEXT: ret1647;1648; RV32IZFINX-LABEL: test_round_float:1649; RV32IZFINX: # %bb.0:1650; RV32IZFINX-NEXT: lui a1, 3072001651; RV32IZFINX-NEXT: fabs.s a2, a01652; RV32IZFINX-NEXT: flt.s a1, a2, a11653; RV32IZFINX-NEXT: beqz a1, .LBB43_21654; RV32IZFINX-NEXT: # %bb.1:1655; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rmm1656; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rmm1657; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01658; RV32IZFINX-NEXT: .LBB43_2:1659; RV32IZFINX-NEXT: ret1660;1661; RV64IZFINX-LABEL: test_round_float:1662; RV64IZFINX: # %bb.0:1663; RV64IZFINX-NEXT: lui a1, 3072001664; RV64IZFINX-NEXT: fabs.s a2, a01665; RV64IZFINX-NEXT: flt.s a1, a2, a11666; RV64IZFINX-NEXT: beqz a1, .LBB43_21667; RV64IZFINX-NEXT: # %bb.1:1668; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rmm1669; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rmm1670; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01671; RV64IZFINX-NEXT: .LBB43_2:1672; RV64IZFINX-NEXT: ret1673 %a = call float @llvm.round.f32(float %x)1674 ret float %a1675}1676 1677define float @test_roundeven_float(float %x) {1678; RV32IFD-LABEL: test_roundeven_float:1679; RV32IFD: # %bb.0:1680; RV32IFD-NEXT: addi sp, sp, -161681; RV32IFD-NEXT: .cfi_def_cfa_offset 161682; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1683; RV32IFD-NEXT: .cfi_offset ra, -41684; RV32IFD-NEXT: call roundeven@plt1685; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1686; RV32IFD-NEXT: addi sp, sp, 161687; RV32IFD-NEXT: ret1688;1689; RV64IFD-LABEL: test_roundeven_float:1690; RV64IFD: # %bb.0:1691; RV64IFD-NEXT: addi sp, sp, -161692; RV64IFD-NEXT: .cfi_def_cfa_offset 161693; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1694; RV64IFD-NEXT: .cfi_offset ra, -81695; RV64IFD-NEXT: call roundeven@plt1696; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1697; RV64IFD-NEXT: addi sp, sp, 161698; RV64IFD-NEXT: ret1699; RV32IF-LABEL: test_roundeven_float:1700; RV32IF: # %bb.0:1701; RV32IF-NEXT: lui a0, 3072001702; RV32IF-NEXT: fmv.w.x fa5, a01703; RV32IF-NEXT: fabs.s fa4, fa01704; RV32IF-NEXT: flt.s a0, fa4, fa51705; RV32IF-NEXT: beqz a0, .LBB44_21706; RV32IF-NEXT: # %bb.1:1707; RV32IF-NEXT: fcvt.w.s a0, fa0, rne1708; RV32IF-NEXT: fcvt.s.w fa5, a0, rne1709; RV32IF-NEXT: fsgnj.s fa0, fa5, fa01710; RV32IF-NEXT: .LBB44_2:1711; RV32IF-NEXT: ret1712;1713; RV64IF-LABEL: test_roundeven_float:1714; RV64IF: # %bb.0:1715; RV64IF-NEXT: lui a0, 3072001716; RV64IF-NEXT: fmv.w.x fa5, a01717; RV64IF-NEXT: fabs.s fa4, fa01718; RV64IF-NEXT: flt.s a0, fa4, fa51719; RV64IF-NEXT: beqz a0, .LBB44_21720; RV64IF-NEXT: # %bb.1:1721; RV64IF-NEXT: fcvt.w.s a0, fa0, rne1722; RV64IF-NEXT: fcvt.s.w fa5, a0, rne1723; RV64IF-NEXT: fsgnj.s fa0, fa5, fa01724; RV64IF-NEXT: .LBB44_2:1725; RV64IF-NEXT: ret1726;1727; RV32IZFINX-LABEL: test_roundeven_float:1728; RV32IZFINX: # %bb.0:1729; RV32IZFINX-NEXT: lui a1, 3072001730; RV32IZFINX-NEXT: fabs.s a2, a01731; RV32IZFINX-NEXT: flt.s a1, a2, a11732; RV32IZFINX-NEXT: beqz a1, .LBB44_21733; RV32IZFINX-NEXT: # %bb.1:1734; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rne1735; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rne1736; RV32IZFINX-NEXT: fsgnj.s a0, a1, a01737; RV32IZFINX-NEXT: .LBB44_2:1738; RV32IZFINX-NEXT: ret1739;1740; RV64IZFINX-LABEL: test_roundeven_float:1741; RV64IZFINX: # %bb.0:1742; RV64IZFINX-NEXT: lui a1, 3072001743; RV64IZFINX-NEXT: fabs.s a2, a01744; RV64IZFINX-NEXT: flt.s a1, a2, a11745; RV64IZFINX-NEXT: beqz a1, .LBB44_21746; RV64IZFINX-NEXT: # %bb.1:1747; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rne1748; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rne1749; RV64IZFINX-NEXT: fsgnj.s a0, a1, a01750; RV64IZFINX-NEXT: .LBB44_2:1751; RV64IZFINX-NEXT: ret1752 %a = call float @llvm.roundeven.f32(float %x)1753 ret float %a1754}1755 1756