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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -stop-after=finalize-isel < %s | FileCheck %s3 4define dso_local void @buz(i1 %pred, float %a, float %b) {5 ; CHECK-LABEL: name: buz6 ; CHECK: bb.0.entry:7 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)8 ; CHECK-NEXT: liveins: $x10, $x11, $x129 ; CHECK-NEXT: {{ $}}10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1211 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1112 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x1013 ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[COPY]]14 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 115 ; CHECK-NEXT: [[FMV_W_X1:%[0-9]+]]:fpr32 = FMV_W_X [[COPY1]]16 ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 30720017 ; CHECK-NEXT: [[FMV_W_X2:%[0-9]+]]:fpr32 = FMV_W_X killed [[LUI]]18 ; CHECK-NEXT: [[FSGNJX_S:%[0-9]+]]:fpr32 = FSGNJX_S [[FMV_W_X1]], [[FMV_W_X1]]19 ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = nofpexcept FLT_S [[FSGNJX_S]], [[FMV_W_X2]]20 ; CHECK-NEXT: BEQ [[FLT_S]], $x0, %bb.221 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: bb.1.entry:23 ; CHECK-NEXT: successors: %bb.2(0x80000000)24 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[FMV_W_X1]], 426 ; CHECK-NEXT: [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[FCVT_W_S]], 427 ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[FCVT_S_W]], [[FMV_W_X1]]28 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: bb.2.entry:30 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)31 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr32 = PHI [[FMV_W_X1]], %bb.0, [[FSGNJ_S]], %bb.133 ; CHECK-NEXT: BNE [[ANDI]], $x0, %bb.434 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: bb.3.entry:36 ; CHECK-NEXT: successors: %bb.4(0x80000000)37 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: bb.4.entry:39 ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)40 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:fpr32 = PHI [[PHI]], %bb.2, [[FMV_W_X1]], %bb.342 ; CHECK-NEXT: [[FSGNJX_S1:%[0-9]+]]:fpr32 = FSGNJX_S [[FMV_W_X]], [[FMV_W_X]]43 ; CHECK-NEXT: [[FLT_S1:%[0-9]+]]:gpr = nofpexcept FLT_S [[FSGNJX_S1]], [[FMV_W_X2]]44 ; CHECK-NEXT: BEQ [[FLT_S1]], $x0, %bb.645 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: bb.5.entry:47 ; CHECK-NEXT: successors: %bb.6(0x80000000)48 ; CHECK-NEXT: {{ $}}49 ; CHECK-NEXT: [[FCVT_W_S1:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[FMV_W_X]], 450 ; CHECK-NEXT: [[FCVT_S_W1:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[FCVT_W_S1]], 451 ; CHECK-NEXT: [[FSGNJ_S1:%[0-9]+]]:fpr32 = FSGNJ_S [[FCVT_S_W1]], [[FMV_W_X]]52 ; CHECK-NEXT: {{ $}}53 ; CHECK-NEXT: bb.6.entry:54 ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.8(0x40000000)55 ; CHECK-NEXT: {{ $}}56 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:fpr32 = PHI [[FMV_W_X]], %bb.4, [[FSGNJ_S1]], %bb.557 ; CHECK-NEXT: BNE [[ANDI]], $x0, %bb.858 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: bb.7.entry:60 ; CHECK-NEXT: successors: %bb.8(0x80000000)61 ; CHECK-NEXT: {{ $}}62 ; CHECK-NEXT: bb.8.entry:63 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:fpr32 = PHI [[PHI2]], %bb.6, [[FMV_W_X]], %bb.764 ; CHECK-NEXT: [[FCVT_L_S:%[0-9]+]]:gpr = nofpexcept FCVT_L_S killed [[PHI3]], 165 ; CHECK-NEXT: [[FMV_X_W:%[0-9]+]]:gpr = FMV_X_W killed [[PHI1]]66 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x267 ; CHECK-NEXT: $x10 = COPY [[FMV_X_W]]68 ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x269 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x270 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x271 ; CHECK-NEXT: $x10 = COPY [[FCVT_L_S]]72 ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x273 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x274 ; CHECK-NEXT: PseudoRET75entry:76 %0 = call float @llvm.round.f32(float %a)77 %cond = select i1 %pred, float %0, float %a78 %1 = call float @llvm.round.f32(float %b)79 %cond2 = select i1 %pred, float %1, float %b80 %conv = fptosi float %cond2 to i6481 call void @bar(float %cond)82 call void @foo(i64 %conv)83 ret void84}85 86declare void @foo(i64)87 88declare void @bar(float)89 90