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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f,+d -stop-after=finalize-isel < %s \3; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=RV32IF %s4; RUN: llc -mtriple=riscv64 -mattr=+f,+d -stop-after=finalize-isel < %s \5; RUN: -target-abi=lp64d | FileCheck -check-prefixes=RV64IF %s6 7; Make sure an implicit FRM dependency is added to instructions with dynamic8; rounding.9 10define float @fadd_s(float %a, float %b) nounwind {11 ; RV32IF-LABEL: name: fadd_s12 ; RV32IF: bb.0 (%ir-block.0):13 ; RV32IF-NEXT: liveins: $f10_f, $f11_f14 ; RV32IF-NEXT: {{ $}}15 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f11_f16 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f17 ; RV32IF-NEXT: %2:fpr32 = nofpexcept FADD_S [[COPY1]], [[COPY]], 7, implicit $frm18 ; RV32IF-NEXT: $f10_f = COPY %219 ; RV32IF-NEXT: PseudoRET implicit $f10_f20 ; RV64IF-LABEL: name: fadd_s21 ; RV64IF: bb.0 (%ir-block.0):22 ; RV64IF-NEXT: liveins: $f10_f, $f11_f23 ; RV64IF-NEXT: {{ $}}24 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f11_f25 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f26 ; RV64IF-NEXT: %2:fpr32 = nofpexcept FADD_S [[COPY1]], [[COPY]], 7, implicit $frm27 ; RV64IF-NEXT: $f10_f = COPY %228 ; RV64IF-NEXT: PseudoRET implicit $f10_f29 %1 = fadd float %a, %b30 ret float %131}32 33define float @fmadd_s(float %a, float %b, float %c) nounwind {34 ; RV32IF-LABEL: name: fmadd_s35 ; RV32IF: bb.0 (%ir-block.0):36 ; RV32IF-NEXT: liveins: $f10_f, $f11_f, $f12_f37 ; RV32IF-NEXT: {{ $}}38 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f12_f39 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f40 ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f10_f41 ; RV32IF-NEXT: %3:fpr32 = nofpexcept FMADD_S [[COPY2]], [[COPY1]], [[COPY]], 7, implicit $frm42 ; RV32IF-NEXT: $f10_f = COPY %343 ; RV32IF-NEXT: PseudoRET implicit $f10_f44 ; RV64IF-LABEL: name: fmadd_s45 ; RV64IF: bb.0 (%ir-block.0):46 ; RV64IF-NEXT: liveins: $f10_f, $f11_f, $f12_f47 ; RV64IF-NEXT: {{ $}}48 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f12_f49 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f50 ; RV64IF-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f10_f51 ; RV64IF-NEXT: %3:fpr32 = nofpexcept FMADD_S [[COPY2]], [[COPY1]], [[COPY]], 7, implicit $frm52 ; RV64IF-NEXT: $f10_f = COPY %353 ; RV64IF-NEXT: PseudoRET implicit $f10_f54 %1 = call float @llvm.fma.f32(float %a, float %b, float %c)55 ret float %156}57 58; This uses rtz instead of dyn rounding mode so shouldn't have an FRM dependncy.59define i32 @fcvt_w_s(float %a) nounwind {60 ; RV32IF-LABEL: name: fcvt_w_s61 ; RV32IF: bb.0 (%ir-block.0):62 ; RV32IF-NEXT: liveins: $f10_f63 ; RV32IF-NEXT: {{ $}}64 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f65 ; RV32IF-NEXT: %1:gpr = nofpexcept FCVT_W_S [[COPY]], 166 ; RV32IF-NEXT: $x10 = COPY %167 ; RV32IF-NEXT: PseudoRET implicit $x1068 ; RV64IF-LABEL: name: fcvt_w_s69 ; RV64IF: bb.0 (%ir-block.0):70 ; RV64IF-NEXT: liveins: $f10_f71 ; RV64IF-NEXT: {{ $}}72 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f73 ; RV64IF-NEXT: %1:gpr = nofpexcept FCVT_W_S [[COPY]], 174 ; RV64IF-NEXT: $x10 = COPY %175 ; RV64IF-NEXT: PseudoRET implicit $x1076 %1 = fptosi float %a to i3277 ret i32 %178}79 80; This doesn't use a rounding mode since i32 can be represented exactly as a81; double.82define double @fcvt_d_w(i32 %a) nounwind {83 ; RV32IF-LABEL: name: fcvt_d_w84 ; RV32IF: bb.0 (%ir-block.0):85 ; RV32IF-NEXT: liveins: $x1086 ; RV32IF-NEXT: {{ $}}87 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1088 ; RV32IF-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 089 ; RV32IF-NEXT: $f10_d = COPY [[FCVT_D_W]]90 ; RV32IF-NEXT: PseudoRET implicit $f10_d91 ;92 ; RV64IF-LABEL: name: fcvt_d_w93 ; RV64IF: bb.0 (%ir-block.0):94 ; RV64IF-NEXT: liveins: $x1095 ; RV64IF-NEXT: {{ $}}96 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1097 ; RV64IF-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 098 ; RV64IF-NEXT: $f10_d = COPY [[FCVT_D_W]]99 ; RV64IF-NEXT: PseudoRET implicit $f10_d100 %1 = sitofp i32 %a to double101 ret double %1102}103