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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \3; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \5; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s6; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \7; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \9; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s10; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \11; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=RV32I %s12; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \13; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=RV64I %s14; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \15; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s16; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \17; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s18; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \19; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s20; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \21; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s22; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \23; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s24; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \25; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s26 27define i32 @fcmp_false(half %a, half %b) nounwind {28; CHECKIZFH-LABEL: fcmp_false:29; CHECKIZFH: # %bb.0:30; CHECKIZFH-NEXT: li a0, 031; CHECKIZFH-NEXT: ret32;33; CHECKIZHINX-LABEL: fcmp_false:34; CHECKIZHINX: # %bb.0:35; CHECKIZHINX-NEXT: li a0, 036; CHECKIZHINX-NEXT: ret37;38; RV32I-LABEL: fcmp_false:39; RV32I: # %bb.0:40; RV32I-NEXT: li a0, 041; RV32I-NEXT: ret42;43; RV64I-LABEL: fcmp_false:44; RV64I: # %bb.0:45; RV64I-NEXT: li a0, 046; RV64I-NEXT: ret47;48; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_false:49; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:50; CHECKIZFHMIN-ILP32F-LP64F-NEXT: li a0, 051; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret52;53; CHECKIZFHMIN-LABEL: fcmp_false:54; CHECKIZFHMIN: # %bb.0:55; CHECKIZFHMIN-NEXT: li a0, 056; CHECKIZFHMIN-NEXT: ret57;58; CHECKIZHINXMIN-LABEL: fcmp_false:59; CHECKIZHINXMIN: # %bb.0:60; CHECKIZHINXMIN-NEXT: li a0, 061; CHECKIZHINXMIN-NEXT: ret62 %1 = fcmp false half %a, %b63 %2 = zext i1 %1 to i3264 ret i32 %265}66 67define i32 @fcmp_oeq(half %a, half %b) nounwind {68; CHECKIZFH-LABEL: fcmp_oeq:69; CHECKIZFH: # %bb.0:70; CHECKIZFH-NEXT: feq.h a0, fa0, fa171; CHECKIZFH-NEXT: ret72;73; CHECKIZHINX-LABEL: fcmp_oeq:74; CHECKIZHINX: # %bb.0:75; CHECKIZHINX-NEXT: feq.h a0, a0, a176; CHECKIZHINX-NEXT: ret77;78; RV32I-LABEL: fcmp_oeq:79; RV32I: # %bb.0:80; RV32I-NEXT: fmv.h.x fa5, a181; RV32I-NEXT: fmv.h.x fa4, a082; RV32I-NEXT: feq.h a0, fa4, fa583; RV32I-NEXT: ret84;85; RV64I-LABEL: fcmp_oeq:86; RV64I: # %bb.0:87; RV64I-NEXT: fmv.h.x fa5, a188; RV64I-NEXT: fmv.h.x fa4, a089; RV64I-NEXT: feq.h a0, fa4, fa590; RV64I-NEXT: ret91;92; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_oeq:93; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:94; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa195; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa096; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a0, fa4, fa597; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret98;99; CHECKIZFHMIN-LABEL: fcmp_oeq:100; CHECKIZFHMIN: # %bb.0:101; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0102; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1103; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4104; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5105; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa4106; CHECKIZFHMIN-NEXT: ret107;108; CHECKIZHINXMIN-LABEL: fcmp_oeq:109; CHECKIZHINXMIN: # %bb.0:110; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1111; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0112; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a1113; CHECKIZHINXMIN-NEXT: ret114 %1 = fcmp oeq half %a, %b115 %2 = zext i1 %1 to i32116 ret i32 %2117}118 119define i32 @fcmp_ogt(half %a, half %b) nounwind {120; CHECKIZFH-LABEL: fcmp_ogt:121; CHECKIZFH: # %bb.0:122; CHECKIZFH-NEXT: flt.h a0, fa1, fa0123; CHECKIZFH-NEXT: ret124;125; CHECKIZHINX-LABEL: fcmp_ogt:126; CHECKIZHINX: # %bb.0:127; CHECKIZHINX-NEXT: flt.h a0, a1, a0128; CHECKIZHINX-NEXT: ret129;130; RV32I-LABEL: fcmp_ogt:131; RV32I: # %bb.0:132; RV32I-NEXT: fmv.h.x fa5, a0133; RV32I-NEXT: fmv.h.x fa4, a1134; RV32I-NEXT: flt.h a0, fa4, fa5135; RV32I-NEXT: ret136;137; RV64I-LABEL: fcmp_ogt:138; RV64I: # %bb.0:139; RV64I-NEXT: fmv.h.x fa5, a0140; RV64I-NEXT: fmv.h.x fa4, a1141; RV64I-NEXT: flt.h a0, fa4, fa5142; RV64I-NEXT: ret143;144; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ogt:145; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:146; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0147; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1148; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5149; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret150;151; CHECKIZFHMIN-LABEL: fcmp_ogt:152; CHECKIZFHMIN: # %bb.0:153; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1154; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0155; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4156; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5157; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4158; CHECKIZFHMIN-NEXT: ret159;160; CHECKIZHINXMIN-LABEL: fcmp_ogt:161; CHECKIZHINXMIN: # %bb.0:162; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0163; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1164; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0165; CHECKIZHINXMIN-NEXT: ret166 %1 = fcmp ogt half %a, %b167 %2 = zext i1 %1 to i32168 ret i32 %2169}170 171define i32 @fcmp_oge(half %a, half %b) nounwind {172; CHECKIZFH-LABEL: fcmp_oge:173; CHECKIZFH: # %bb.0:174; CHECKIZFH-NEXT: fle.h a0, fa1, fa0175; CHECKIZFH-NEXT: ret176;177; CHECKIZHINX-LABEL: fcmp_oge:178; CHECKIZHINX: # %bb.0:179; CHECKIZHINX-NEXT: fle.h a0, a1, a0180; CHECKIZHINX-NEXT: ret181;182; RV32I-LABEL: fcmp_oge:183; RV32I: # %bb.0:184; RV32I-NEXT: fmv.h.x fa5, a0185; RV32I-NEXT: fmv.h.x fa4, a1186; RV32I-NEXT: fle.h a0, fa4, fa5187; RV32I-NEXT: ret188;189; RV64I-LABEL: fcmp_oge:190; RV64I: # %bb.0:191; RV64I-NEXT: fmv.h.x fa5, a0192; RV64I-NEXT: fmv.h.x fa4, a1193; RV64I-NEXT: fle.h a0, fa4, fa5194; RV64I-NEXT: ret195;196; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_oge:197; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:198; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0199; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1200; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5201; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret202;203; CHECKIZFHMIN-LABEL: fcmp_oge:204; CHECKIZFHMIN: # %bb.0:205; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1206; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0207; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4208; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5209; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4210; CHECKIZFHMIN-NEXT: ret211;212; CHECKIZHINXMIN-LABEL: fcmp_oge:213; CHECKIZHINXMIN: # %bb.0:214; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0215; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1216; CHECKIZHINXMIN-NEXT: fle.s a0, a1, a0217; CHECKIZHINXMIN-NEXT: ret218 %1 = fcmp oge half %a, %b219 %2 = zext i1 %1 to i32220 ret i32 %2221}222 223define i32 @fcmp_olt(half %a, half %b) nounwind {224; CHECKIZFH-LABEL: fcmp_olt:225; CHECKIZFH: # %bb.0:226; CHECKIZFH-NEXT: flt.h a0, fa0, fa1227; CHECKIZFH-NEXT: ret228;229; CHECKIZHINX-LABEL: fcmp_olt:230; CHECKIZHINX: # %bb.0:231; CHECKIZHINX-NEXT: flt.h a0, a0, a1232; CHECKIZHINX-NEXT: ret233;234; RV32I-LABEL: fcmp_olt:235; RV32I: # %bb.0:236; RV32I-NEXT: fmv.h.x fa5, a1237; RV32I-NEXT: fmv.h.x fa4, a0238; RV32I-NEXT: flt.h a0, fa4, fa5239; RV32I-NEXT: ret240;241; RV64I-LABEL: fcmp_olt:242; RV64I: # %bb.0:243; RV64I-NEXT: fmv.h.x fa5, a1244; RV64I-NEXT: fmv.h.x fa4, a0245; RV64I-NEXT: flt.h a0, fa4, fa5246; RV64I-NEXT: ret247;248; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_olt:249; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:250; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1251; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0252; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5253; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret254;255; CHECKIZFHMIN-LABEL: fcmp_olt:256; CHECKIZFHMIN: # %bb.0:257; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0258; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1259; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4260; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5261; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4262; CHECKIZFHMIN-NEXT: ret263;264; CHECKIZHINXMIN-LABEL: fcmp_olt:265; CHECKIZHINXMIN: # %bb.0:266; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1267; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0268; CHECKIZHINXMIN-NEXT: flt.s a0, a0, a1269; CHECKIZHINXMIN-NEXT: ret270 %1 = fcmp olt half %a, %b271 %2 = zext i1 %1 to i32272 ret i32 %2273}274 275define i32 @fcmp_ole(half %a, half %b) nounwind {276; CHECKIZFH-LABEL: fcmp_ole:277; CHECKIZFH: # %bb.0:278; CHECKIZFH-NEXT: fle.h a0, fa0, fa1279; CHECKIZFH-NEXT: ret280;281; CHECKIZHINX-LABEL: fcmp_ole:282; CHECKIZHINX: # %bb.0:283; CHECKIZHINX-NEXT: fle.h a0, a0, a1284; CHECKIZHINX-NEXT: ret285;286; RV32I-LABEL: fcmp_ole:287; RV32I: # %bb.0:288; RV32I-NEXT: fmv.h.x fa5, a1289; RV32I-NEXT: fmv.h.x fa4, a0290; RV32I-NEXT: fle.h a0, fa4, fa5291; RV32I-NEXT: ret292;293; RV64I-LABEL: fcmp_ole:294; RV64I: # %bb.0:295; RV64I-NEXT: fmv.h.x fa5, a1296; RV64I-NEXT: fmv.h.x fa4, a0297; RV64I-NEXT: fle.h a0, fa4, fa5298; RV64I-NEXT: ret299;300; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ole:301; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:302; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1303; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0304; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5305; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret306;307; CHECKIZFHMIN-LABEL: fcmp_ole:308; CHECKIZFHMIN: # %bb.0:309; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0310; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1311; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4312; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5313; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4314; CHECKIZFHMIN-NEXT: ret315;316; CHECKIZHINXMIN-LABEL: fcmp_ole:317; CHECKIZHINXMIN: # %bb.0:318; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1319; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0320; CHECKIZHINXMIN-NEXT: fle.s a0, a0, a1321; CHECKIZHINXMIN-NEXT: ret322 %1 = fcmp ole half %a, %b323 %2 = zext i1 %1 to i32324 ret i32 %2325}326 327define i32 @fcmp_one(half %a, half %b) nounwind {328; CHECKIZFH-LABEL: fcmp_one:329; CHECKIZFH: # %bb.0:330; CHECKIZFH-NEXT: flt.h a0, fa0, fa1331; CHECKIZFH-NEXT: flt.h a1, fa1, fa0332; CHECKIZFH-NEXT: or a0, a1, a0333; CHECKIZFH-NEXT: ret334;335; CHECKIZHINX-LABEL: fcmp_one:336; CHECKIZHINX: # %bb.0:337; CHECKIZHINX-NEXT: flt.h a2, a0, a1338; CHECKIZHINX-NEXT: flt.h a0, a1, a0339; CHECKIZHINX-NEXT: or a0, a0, a2340; CHECKIZHINX-NEXT: ret341;342; RV32I-LABEL: fcmp_one:343; RV32I: # %bb.0:344; RV32I-NEXT: fmv.h.x fa5, a1345; RV32I-NEXT: fmv.h.x fa4, a0346; RV32I-NEXT: flt.h a0, fa4, fa5347; RV32I-NEXT: flt.h a1, fa5, fa4348; RV32I-NEXT: or a0, a1, a0349; RV32I-NEXT: ret350;351; RV64I-LABEL: fcmp_one:352; RV64I: # %bb.0:353; RV64I-NEXT: fmv.h.x fa5, a1354; RV64I-NEXT: fmv.h.x fa4, a0355; RV64I-NEXT: flt.h a0, fa4, fa5356; RV64I-NEXT: flt.h a1, fa5, fa4357; RV64I-NEXT: or a0, a1, a0358; RV64I-NEXT: ret359;360; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_one:361; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:362; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1363; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0364; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5365; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a1, fa5, fa4366; CHECKIZFHMIN-ILP32F-LP64F-NEXT: or a0, a1, a0367; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret368;369; CHECKIZFHMIN-LABEL: fcmp_one:370; CHECKIZFHMIN: # %bb.0:371; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0372; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1373; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4374; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5375; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4376; CHECKIZFHMIN-NEXT: flt.s a1, fa4, fa5377; CHECKIZFHMIN-NEXT: or a0, a1, a0378; CHECKIZFHMIN-NEXT: ret379;380; CHECKIZHINXMIN-LABEL: fcmp_one:381; CHECKIZHINXMIN: # %bb.0:382; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1383; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0384; CHECKIZHINXMIN-NEXT: flt.s a2, a0, a1385; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0386; CHECKIZHINXMIN-NEXT: or a0, a0, a2387; CHECKIZHINXMIN-NEXT: ret388 %1 = fcmp one half %a, %b389 %2 = zext i1 %1 to i32390 ret i32 %2391}392 393define i32 @fcmp_ord(half %a, half %b) nounwind {394; CHECKIZFH-LABEL: fcmp_ord:395; CHECKIZFH: # %bb.0:396; CHECKIZFH-NEXT: feq.h a0, fa1, fa1397; CHECKIZFH-NEXT: feq.h a1, fa0, fa0398; CHECKIZFH-NEXT: and a0, a1, a0399; CHECKIZFH-NEXT: ret400;401; CHECKIZHINX-LABEL: fcmp_ord:402; CHECKIZHINX: # %bb.0:403; CHECKIZHINX-NEXT: feq.h a1, a1, a1404; CHECKIZHINX-NEXT: feq.h a0, a0, a0405; CHECKIZHINX-NEXT: and a0, a0, a1406; CHECKIZHINX-NEXT: ret407;408; RV32I-LABEL: fcmp_ord:409; RV32I: # %bb.0:410; RV32I-NEXT: fmv.h.x fa5, a0411; RV32I-NEXT: fmv.h.x fa4, a1412; RV32I-NEXT: feq.h a0, fa4, fa4413; RV32I-NEXT: feq.h a1, fa5, fa5414; RV32I-NEXT: and a0, a1, a0415; RV32I-NEXT: ret416;417; RV64I-LABEL: fcmp_ord:418; RV64I: # %bb.0:419; RV64I-NEXT: fmv.h.x fa5, a0420; RV64I-NEXT: fmv.h.x fa4, a1421; RV64I-NEXT: feq.h a0, fa4, fa4422; RV64I-NEXT: feq.h a1, fa5, fa5423; RV64I-NEXT: and a0, a1, a0424; RV64I-NEXT: ret425;426; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ord:427; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:428; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1429; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0430; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a0, fa5, fa5431; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a1, fa4, fa4432; CHECKIZFHMIN-ILP32F-LP64F-NEXT: and a0, a1, a0433; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret434;435; CHECKIZFHMIN-LABEL: fcmp_ord:436; CHECKIZFHMIN: # %bb.0:437; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0438; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1439; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4440; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5441; CHECKIZFHMIN-NEXT: feq.s a0, fa4, fa4442; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5443; CHECKIZFHMIN-NEXT: and a0, a1, a0444; CHECKIZFHMIN-NEXT: ret445;446; CHECKIZHINXMIN-LABEL: fcmp_ord:447; CHECKIZHINXMIN: # %bb.0:448; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1449; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0450; CHECKIZHINXMIN-NEXT: feq.s a1, a1, a1451; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0452; CHECKIZHINXMIN-NEXT: and a0, a0, a1453; CHECKIZHINXMIN-NEXT: ret454 %1 = fcmp ord half %a, %b455 %2 = zext i1 %1 to i32456 ret i32 %2457}458 459define i32 @fcmp_ueq(half %a, half %b) nounwind {460; CHECKIZFH-LABEL: fcmp_ueq:461; CHECKIZFH: # %bb.0:462; CHECKIZFH-NEXT: flt.h a0, fa0, fa1463; CHECKIZFH-NEXT: flt.h a1, fa1, fa0464; CHECKIZFH-NEXT: or a0, a1, a0465; CHECKIZFH-NEXT: xori a0, a0, 1466; CHECKIZFH-NEXT: ret467;468; CHECKIZHINX-LABEL: fcmp_ueq:469; CHECKIZHINX: # %bb.0:470; CHECKIZHINX-NEXT: flt.h a2, a0, a1471; CHECKIZHINX-NEXT: flt.h a0, a1, a0472; CHECKIZHINX-NEXT: or a0, a0, a2473; CHECKIZHINX-NEXT: xori a0, a0, 1474; CHECKIZHINX-NEXT: ret475;476; RV32I-LABEL: fcmp_ueq:477; RV32I: # %bb.0:478; RV32I-NEXT: fmv.h.x fa5, a1479; RV32I-NEXT: fmv.h.x fa4, a0480; RV32I-NEXT: flt.h a0, fa4, fa5481; RV32I-NEXT: flt.h a1, fa5, fa4482; RV32I-NEXT: or a0, a1, a0483; RV32I-NEXT: xori a0, a0, 1484; RV32I-NEXT: ret485;486; RV64I-LABEL: fcmp_ueq:487; RV64I: # %bb.0:488; RV64I-NEXT: fmv.h.x fa5, a1489; RV64I-NEXT: fmv.h.x fa4, a0490; RV64I-NEXT: flt.h a0, fa4, fa5491; RV64I-NEXT: flt.h a1, fa5, fa4492; RV64I-NEXT: or a0, a1, a0493; RV64I-NEXT: xori a0, a0, 1494; RV64I-NEXT: ret495;496; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ueq:497; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:498; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1499; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0500; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5501; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a1, fa5, fa4502; CHECKIZFHMIN-ILP32F-LP64F-NEXT: or a0, a1, a0503; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1504; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret505;506; CHECKIZFHMIN-LABEL: fcmp_ueq:507; CHECKIZFHMIN: # %bb.0:508; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0509; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1510; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4511; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5512; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4513; CHECKIZFHMIN-NEXT: flt.s a1, fa4, fa5514; CHECKIZFHMIN-NEXT: or a0, a1, a0515; CHECKIZFHMIN-NEXT: xori a0, a0, 1516; CHECKIZFHMIN-NEXT: ret517;518; CHECKIZHINXMIN-LABEL: fcmp_ueq:519; CHECKIZHINXMIN: # %bb.0:520; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1521; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0522; CHECKIZHINXMIN-NEXT: flt.s a2, a0, a1523; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0524; CHECKIZHINXMIN-NEXT: or a0, a0, a2525; CHECKIZHINXMIN-NEXT: xori a0, a0, 1526; CHECKIZHINXMIN-NEXT: ret527 %1 = fcmp ueq half %a, %b528 %2 = zext i1 %1 to i32529 ret i32 %2530}531 532define i32 @fcmp_ugt(half %a, half %b) nounwind {533; CHECKIZFH-LABEL: fcmp_ugt:534; CHECKIZFH: # %bb.0:535; CHECKIZFH-NEXT: fle.h a0, fa0, fa1536; CHECKIZFH-NEXT: xori a0, a0, 1537; CHECKIZFH-NEXT: ret538;539; CHECKIZHINX-LABEL: fcmp_ugt:540; CHECKIZHINX: # %bb.0:541; CHECKIZHINX-NEXT: fle.h a0, a0, a1542; CHECKIZHINX-NEXT: xori a0, a0, 1543; CHECKIZHINX-NEXT: ret544;545; RV32I-LABEL: fcmp_ugt:546; RV32I: # %bb.0:547; RV32I-NEXT: fmv.h.x fa5, a1548; RV32I-NEXT: fmv.h.x fa4, a0549; RV32I-NEXT: fle.h a0, fa4, fa5550; RV32I-NEXT: xori a0, a0, 1551; RV32I-NEXT: ret552;553; RV64I-LABEL: fcmp_ugt:554; RV64I: # %bb.0:555; RV64I-NEXT: fmv.h.x fa5, a1556; RV64I-NEXT: fmv.h.x fa4, a0557; RV64I-NEXT: fle.h a0, fa4, fa5558; RV64I-NEXT: xori a0, a0, 1559; RV64I-NEXT: ret560;561; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ugt:562; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:563; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1564; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0565; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5566; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1567; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret568;569; CHECKIZFHMIN-LABEL: fcmp_ugt:570; CHECKIZFHMIN: # %bb.0:571; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0572; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1573; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4574; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5575; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4576; CHECKIZFHMIN-NEXT: xori a0, a0, 1577; CHECKIZFHMIN-NEXT: ret578;579; CHECKIZHINXMIN-LABEL: fcmp_ugt:580; CHECKIZHINXMIN: # %bb.0:581; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1582; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0583; CHECKIZHINXMIN-NEXT: fle.s a0, a0, a1584; CHECKIZHINXMIN-NEXT: xori a0, a0, 1585; CHECKIZHINXMIN-NEXT: ret586 %1 = fcmp ugt half %a, %b587 %2 = zext i1 %1 to i32588 ret i32 %2589}590 591define i32 @fcmp_uge(half %a, half %b) nounwind {592; CHECKIZFH-LABEL: fcmp_uge:593; CHECKIZFH: # %bb.0:594; CHECKIZFH-NEXT: flt.h a0, fa0, fa1595; CHECKIZFH-NEXT: xori a0, a0, 1596; CHECKIZFH-NEXT: ret597;598; CHECKIZHINX-LABEL: fcmp_uge:599; CHECKIZHINX: # %bb.0:600; CHECKIZHINX-NEXT: flt.h a0, a0, a1601; CHECKIZHINX-NEXT: xori a0, a0, 1602; CHECKIZHINX-NEXT: ret603;604; RV32I-LABEL: fcmp_uge:605; RV32I: # %bb.0:606; RV32I-NEXT: fmv.h.x fa5, a1607; RV32I-NEXT: fmv.h.x fa4, a0608; RV32I-NEXT: flt.h a0, fa4, fa5609; RV32I-NEXT: xori a0, a0, 1610; RV32I-NEXT: ret611;612; RV64I-LABEL: fcmp_uge:613; RV64I: # %bb.0:614; RV64I-NEXT: fmv.h.x fa5, a1615; RV64I-NEXT: fmv.h.x fa4, a0616; RV64I-NEXT: flt.h a0, fa4, fa5617; RV64I-NEXT: xori a0, a0, 1618; RV64I-NEXT: ret619;620; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_uge:621; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:622; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1623; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0624; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5625; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1626; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret627;628; CHECKIZFHMIN-LABEL: fcmp_uge:629; CHECKIZFHMIN: # %bb.0:630; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0631; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1632; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4633; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5634; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4635; CHECKIZFHMIN-NEXT: xori a0, a0, 1636; CHECKIZFHMIN-NEXT: ret637;638; CHECKIZHINXMIN-LABEL: fcmp_uge:639; CHECKIZHINXMIN: # %bb.0:640; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1641; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0642; CHECKIZHINXMIN-NEXT: flt.s a0, a0, a1643; CHECKIZHINXMIN-NEXT: xori a0, a0, 1644; CHECKIZHINXMIN-NEXT: ret645 %1 = fcmp uge half %a, %b646 %2 = zext i1 %1 to i32647 ret i32 %2648}649 650define i32 @fcmp_ult(half %a, half %b) nounwind {651; CHECKIZFH-LABEL: fcmp_ult:652; CHECKIZFH: # %bb.0:653; CHECKIZFH-NEXT: fle.h a0, fa1, fa0654; CHECKIZFH-NEXT: xori a0, a0, 1655; CHECKIZFH-NEXT: ret656;657; CHECKIZHINX-LABEL: fcmp_ult:658; CHECKIZHINX: # %bb.0:659; CHECKIZHINX-NEXT: fle.h a0, a1, a0660; CHECKIZHINX-NEXT: xori a0, a0, 1661; CHECKIZHINX-NEXT: ret662;663; RV32I-LABEL: fcmp_ult:664; RV32I: # %bb.0:665; RV32I-NEXT: fmv.h.x fa5, a0666; RV32I-NEXT: fmv.h.x fa4, a1667; RV32I-NEXT: fle.h a0, fa4, fa5668; RV32I-NEXT: xori a0, a0, 1669; RV32I-NEXT: ret670;671; RV64I-LABEL: fcmp_ult:672; RV64I: # %bb.0:673; RV64I-NEXT: fmv.h.x fa5, a0674; RV64I-NEXT: fmv.h.x fa4, a1675; RV64I-NEXT: fle.h a0, fa4, fa5676; RV64I-NEXT: xori a0, a0, 1677; RV64I-NEXT: ret678;679; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ult:680; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:681; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0682; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1683; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5684; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1685; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret686;687; CHECKIZFHMIN-LABEL: fcmp_ult:688; CHECKIZFHMIN: # %bb.0:689; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1690; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0691; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4692; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5693; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4694; CHECKIZFHMIN-NEXT: xori a0, a0, 1695; CHECKIZFHMIN-NEXT: ret696;697; CHECKIZHINXMIN-LABEL: fcmp_ult:698; CHECKIZHINXMIN: # %bb.0:699; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0700; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1701; CHECKIZHINXMIN-NEXT: fle.s a0, a1, a0702; CHECKIZHINXMIN-NEXT: xori a0, a0, 1703; CHECKIZHINXMIN-NEXT: ret704 %1 = fcmp ult half %a, %b705 %2 = zext i1 %1 to i32706 ret i32 %2707}708 709define i32 @fcmp_ule(half %a, half %b) nounwind {710; CHECKIZFH-LABEL: fcmp_ule:711; CHECKIZFH: # %bb.0:712; CHECKIZFH-NEXT: flt.h a0, fa1, fa0713; CHECKIZFH-NEXT: xori a0, a0, 1714; CHECKIZFH-NEXT: ret715;716; CHECKIZHINX-LABEL: fcmp_ule:717; CHECKIZHINX: # %bb.0:718; CHECKIZHINX-NEXT: flt.h a0, a1, a0719; CHECKIZHINX-NEXT: xori a0, a0, 1720; CHECKIZHINX-NEXT: ret721;722; RV32I-LABEL: fcmp_ule:723; RV32I: # %bb.0:724; RV32I-NEXT: fmv.h.x fa5, a0725; RV32I-NEXT: fmv.h.x fa4, a1726; RV32I-NEXT: flt.h a0, fa4, fa5727; RV32I-NEXT: xori a0, a0, 1728; RV32I-NEXT: ret729;730; RV64I-LABEL: fcmp_ule:731; RV64I: # %bb.0:732; RV64I-NEXT: fmv.h.x fa5, a0733; RV64I-NEXT: fmv.h.x fa4, a1734; RV64I-NEXT: flt.h a0, fa4, fa5735; RV64I-NEXT: xori a0, a0, 1736; RV64I-NEXT: ret737;738; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ule:739; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:740; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0741; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1742; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5743; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1744; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret745;746; CHECKIZFHMIN-LABEL: fcmp_ule:747; CHECKIZFHMIN: # %bb.0:748; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1749; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0750; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4751; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5752; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4753; CHECKIZFHMIN-NEXT: xori a0, a0, 1754; CHECKIZFHMIN-NEXT: ret755;756; CHECKIZHINXMIN-LABEL: fcmp_ule:757; CHECKIZHINXMIN: # %bb.0:758; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0759; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1760; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0761; CHECKIZHINXMIN-NEXT: xori a0, a0, 1762; CHECKIZHINXMIN-NEXT: ret763 %1 = fcmp ule half %a, %b764 %2 = zext i1 %1 to i32765 ret i32 %2766}767 768define i32 @fcmp_une(half %a, half %b) nounwind {769; CHECKIZFH-LABEL: fcmp_une:770; CHECKIZFH: # %bb.0:771; CHECKIZFH-NEXT: feq.h a0, fa0, fa1772; CHECKIZFH-NEXT: xori a0, a0, 1773; CHECKIZFH-NEXT: ret774;775; CHECKIZHINX-LABEL: fcmp_une:776; CHECKIZHINX: # %bb.0:777; CHECKIZHINX-NEXT: feq.h a0, a0, a1778; CHECKIZHINX-NEXT: xori a0, a0, 1779; CHECKIZHINX-NEXT: ret780;781; RV32I-LABEL: fcmp_une:782; RV32I: # %bb.0:783; RV32I-NEXT: fmv.h.x fa5, a1784; RV32I-NEXT: fmv.h.x fa4, a0785; RV32I-NEXT: feq.h a0, fa4, fa5786; RV32I-NEXT: xori a0, a0, 1787; RV32I-NEXT: ret788;789; RV64I-LABEL: fcmp_une:790; RV64I: # %bb.0:791; RV64I-NEXT: fmv.h.x fa5, a1792; RV64I-NEXT: fmv.h.x fa4, a0793; RV64I-NEXT: feq.h a0, fa4, fa5794; RV64I-NEXT: xori a0, a0, 1795; RV64I-NEXT: ret796;797; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_une:798; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:799; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1800; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0801; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a0, fa4, fa5802; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1803; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret804;805; CHECKIZFHMIN-LABEL: fcmp_une:806; CHECKIZFHMIN: # %bb.0:807; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0808; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1809; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4810; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5811; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa4812; CHECKIZFHMIN-NEXT: xori a0, a0, 1813; CHECKIZFHMIN-NEXT: ret814;815; CHECKIZHINXMIN-LABEL: fcmp_une:816; CHECKIZHINXMIN: # %bb.0:817; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1818; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0819; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a1820; CHECKIZHINXMIN-NEXT: xori a0, a0, 1821; CHECKIZHINXMIN-NEXT: ret822 %1 = fcmp une half %a, %b823 %2 = zext i1 %1 to i32824 ret i32 %2825}826 827define i32 @fcmp_uno(half %a, half %b) nounwind {828; CHECKIZFH-LABEL: fcmp_uno:829; CHECKIZFH: # %bb.0:830; CHECKIZFH-NEXT: feq.h a0, fa1, fa1831; CHECKIZFH-NEXT: feq.h a1, fa0, fa0832; CHECKIZFH-NEXT: and a0, a1, a0833; CHECKIZFH-NEXT: xori a0, a0, 1834; CHECKIZFH-NEXT: ret835;836; CHECKIZHINX-LABEL: fcmp_uno:837; CHECKIZHINX: # %bb.0:838; CHECKIZHINX-NEXT: feq.h a1, a1, a1839; CHECKIZHINX-NEXT: feq.h a0, a0, a0840; CHECKIZHINX-NEXT: and a0, a0, a1841; CHECKIZHINX-NEXT: xori a0, a0, 1842; CHECKIZHINX-NEXT: ret843;844; RV32I-LABEL: fcmp_uno:845; RV32I: # %bb.0:846; RV32I-NEXT: fmv.h.x fa5, a0847; RV32I-NEXT: fmv.h.x fa4, a1848; RV32I-NEXT: feq.h a0, fa4, fa4849; RV32I-NEXT: feq.h a1, fa5, fa5850; RV32I-NEXT: and a0, a1, a0851; RV32I-NEXT: xori a0, a0, 1852; RV32I-NEXT: ret853;854; RV64I-LABEL: fcmp_uno:855; RV64I: # %bb.0:856; RV64I-NEXT: fmv.h.x fa5, a0857; RV64I-NEXT: fmv.h.x fa4, a1858; RV64I-NEXT: feq.h a0, fa4, fa4859; RV64I-NEXT: feq.h a1, fa5, fa5860; RV64I-NEXT: and a0, a1, a0861; RV64I-NEXT: xori a0, a0, 1862; RV64I-NEXT: ret863;864; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_uno:865; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:866; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1867; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0868; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a0, fa5, fa5869; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a1, fa4, fa4870; CHECKIZFHMIN-ILP32F-LP64F-NEXT: and a0, a1, a0871; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1872; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret873;874; CHECKIZFHMIN-LABEL: fcmp_uno:875; CHECKIZFHMIN: # %bb.0:876; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0877; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1878; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4879; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5880; CHECKIZFHMIN-NEXT: feq.s a0, fa4, fa4881; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5882; CHECKIZFHMIN-NEXT: and a0, a1, a0883; CHECKIZFHMIN-NEXT: xori a0, a0, 1884; CHECKIZFHMIN-NEXT: ret885;886; CHECKIZHINXMIN-LABEL: fcmp_uno:887; CHECKIZHINXMIN: # %bb.0:888; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1889; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0890; CHECKIZHINXMIN-NEXT: feq.s a1, a1, a1891; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0892; CHECKIZHINXMIN-NEXT: and a0, a0, a1893; CHECKIZHINXMIN-NEXT: xori a0, a0, 1894; CHECKIZHINXMIN-NEXT: ret895 %1 = fcmp uno half %a, %b896 %2 = zext i1 %1 to i32897 ret i32 %2898}899 900define i32 @fcmp_true(half %a, half %b) nounwind {901; CHECKIZFH-LABEL: fcmp_true:902; CHECKIZFH: # %bb.0:903; CHECKIZFH-NEXT: li a0, 1904; CHECKIZFH-NEXT: ret905;906; CHECKIZHINX-LABEL: fcmp_true:907; CHECKIZHINX: # %bb.0:908; CHECKIZHINX-NEXT: li a0, 1909; CHECKIZHINX-NEXT: ret910;911; RV32I-LABEL: fcmp_true:912; RV32I: # %bb.0:913; RV32I-NEXT: li a0, 1914; RV32I-NEXT: ret915;916; RV64I-LABEL: fcmp_true:917; RV64I: # %bb.0:918; RV64I-NEXT: li a0, 1919; RV64I-NEXT: ret920;921; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_true:922; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0:923; CHECKIZFHMIN-ILP32F-LP64F-NEXT: li a0, 1924; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret925;926; CHECKIZFHMIN-LABEL: fcmp_true:927; CHECKIZFHMIN: # %bb.0:928; CHECKIZFHMIN-NEXT: li a0, 1929; CHECKIZFHMIN-NEXT: ret930;931; CHECKIZHINXMIN-LABEL: fcmp_true:932; CHECKIZHINXMIN: # %bb.0:933; CHECKIZHINXMIN-NEXT: li a0, 1934; CHECKIZHINXMIN-NEXT: ret935 %1 = fcmp true half %a, %b936 %2 = zext i1 %1 to i32937 ret i32 %2938}939