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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \3; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \5; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s6; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \7; RUN: -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \9; RUN: -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s10; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \11; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s12; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \13; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s14; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \15; RUN: -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s16; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \17; RUN: -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s18 19define half @flh(ptr %a) nounwind {20; CHECKIZFH-LABEL: flh:21; CHECKIZFH: # %bb.0:22; CHECKIZFH-NEXT: flh fa5, 0(a0)23; CHECKIZFH-NEXT: flh fa4, 6(a0)24; CHECKIZFH-NEXT: fadd.h fa0, fa5, fa425; CHECKIZFH-NEXT: ret26;27; CHECKIZHINX-LABEL: flh:28; CHECKIZHINX: # %bb.0:29; CHECKIZHINX-NEXT: lh a1, 0(a0)30; CHECKIZHINX-NEXT: lh a0, 6(a0)31; CHECKIZHINX-NEXT: fadd.h a0, a1, a032; CHECKIZHINX-NEXT: ret33;34; CHECKIZFHMIN-LABEL: flh:35; CHECKIZFHMIN: # %bb.0:36; CHECKIZFHMIN-NEXT: flh fa5, 6(a0)37; CHECKIZFHMIN-NEXT: flh fa4, 0(a0)38; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa539; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa440; CHECKIZFHMIN-NEXT: fadd.s fa5, fa4, fa541; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa542; CHECKIZFHMIN-NEXT: ret43;44; CHECKIZHINXMIN-LABEL: flh:45; CHECKIZHINXMIN: # %bb.0:46; CHECKIZHINXMIN-NEXT: lh a1, 6(a0)47; CHECKIZHINXMIN-NEXT: lh a0, 0(a0)48; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a149; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a050; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a151; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a052; CHECKIZHINXMIN-NEXT: ret53 %1 = load half, ptr %a54 %2 = getelementptr half, ptr %a, i32 355 %3 = load half, ptr %256; Use both loaded values in an FP op to ensure an flh is used, even for the57; soft half ABI58 %4 = fadd half %1, %359 ret half %460}61 62define dso_local void @fsh(ptr %a, half %b, half %c) nounwind {63; Use %b and %c in an FP op to ensure half precision floating point registers64; are used, even for the soft half ABI65; CHECKIZFH-LABEL: fsh:66; CHECKIZFH: # %bb.0:67; CHECKIZFH-NEXT: fadd.h fa5, fa0, fa168; CHECKIZFH-NEXT: fsh fa5, 0(a0)69; CHECKIZFH-NEXT: fsh fa5, 16(a0)70; CHECKIZFH-NEXT: ret71;72; CHECKIZHINX-LABEL: fsh:73; CHECKIZHINX: # %bb.0:74; CHECKIZHINX-NEXT: fadd.h a1, a1, a275; CHECKIZHINX-NEXT: sh a1, 0(a0)76; CHECKIZHINX-NEXT: sh a1, 16(a0)77; CHECKIZHINX-NEXT: ret78;79; CHECKIZFHMIN-LABEL: fsh:80; CHECKIZFHMIN: # %bb.0:81; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa182; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa083; CHECKIZFHMIN-NEXT: fadd.s fa5, fa4, fa584; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa585; CHECKIZFHMIN-NEXT: fsh fa5, 0(a0)86; CHECKIZFHMIN-NEXT: fsh fa5, 16(a0)87; CHECKIZFHMIN-NEXT: ret88;89; CHECKIZHINXMIN-LABEL: fsh:90; CHECKIZHINXMIN: # %bb.0:91; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a292; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a193; CHECKIZHINXMIN-NEXT: fadd.s a1, a1, a294; CHECKIZHINXMIN-NEXT: fcvt.h.s a1, a195; CHECKIZHINXMIN-NEXT: sh a1, 0(a0)96; CHECKIZHINXMIN-NEXT: sh a1, 16(a0)97; CHECKIZHINXMIN-NEXT: ret98 %1 = fadd half %b, %c99 store half %1, ptr %a100 %2 = getelementptr half, ptr %a, i32 8101 store half %1, ptr %2102 ret void103}104 105; Check load and store to a global106@G = dso_local global half 0.0107 108define half @flh_fsh_global(half %a, half %b) nounwind {109; Use %a and %b in an FP op to ensure half precision floating point registers110; are used, even for the soft half ABI111; CHECKIZFH-LABEL: flh_fsh_global:112; CHECKIZFH: # %bb.0:113; CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1114; CHECKIZFH-NEXT: lui a0, %hi(G)115; CHECKIZFH-NEXT: addi a0, a0, %lo(G)116; CHECKIZFH-NEXT: flh fa5, 0(a0)117; CHECKIZFH-NEXT: fsh fa0, 0(a0)118; CHECKIZFH-NEXT: flh fa5, 18(a0)119; CHECKIZFH-NEXT: fsh fa0, 18(a0)120; CHECKIZFH-NEXT: ret121;122; CHECKIZHINX-LABEL: flh_fsh_global:123; CHECKIZHINX: # %bb.0:124; CHECKIZHINX-NEXT: fadd.h a0, a0, a1125; CHECKIZHINX-NEXT: lui a1, %hi(G)126; CHECKIZHINX-NEXT: addi a1, a1, %lo(G)127; CHECKIZHINX-NEXT: lh zero, 0(a1)128; CHECKIZHINX-NEXT: sh a0, 0(a1)129; CHECKIZHINX-NEXT: lh zero, 18(a1)130; CHECKIZHINX-NEXT: sh a0, 18(a1)131; CHECKIZHINX-NEXT: ret132;133; CHECKIZFHMIN-LABEL: flh_fsh_global:134; CHECKIZFHMIN: # %bb.0:135; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1136; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0137; CHECKIZFHMIN-NEXT: lui a0, %hi(G)138; CHECKIZFHMIN-NEXT: addi a0, a0, %lo(G)139; CHECKIZFHMIN-NEXT: fadd.s fa5, fa4, fa5140; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5141; CHECKIZFHMIN-NEXT: flh fa5, 0(a0)142; CHECKIZFHMIN-NEXT: fsh fa0, 0(a0)143; CHECKIZFHMIN-NEXT: flh fa5, 18(a0)144; CHECKIZFHMIN-NEXT: fsh fa0, 18(a0)145; CHECKIZFHMIN-NEXT: ret146;147; CHECKIZHINXMIN-LABEL: flh_fsh_global:148; CHECKIZHINXMIN: # %bb.0:149; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1150; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0151; CHECKIZHINXMIN-NEXT: lui a2, %hi(G)152; CHECKIZHINXMIN-NEXT: addi a2, a2, %lo(G)153; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1154; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0155; CHECKIZHINXMIN-NEXT: lh zero, 0(a2)156; CHECKIZHINXMIN-NEXT: sh a0, 0(a2)157; CHECKIZHINXMIN-NEXT: lh zero, 18(a2)158; CHECKIZHINXMIN-NEXT: sh a0, 18(a2)159; CHECKIZHINXMIN-NEXT: ret160 %1 = fadd half %a, %b161 %2 = load volatile half, ptr @G162 store half %1, ptr @G163 %3 = getelementptr half, ptr @G, i32 9164 %4 = load volatile half, ptr %3165 store half %1, ptr %3166 ret half %1167}168 169; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1170define half @flh_fsh_constant(half %a) nounwind {171; RV32IZFH-LABEL: flh_fsh_constant:172; RV32IZFH: # %bb.0:173; RV32IZFH-NEXT: lui a0, 912092174; RV32IZFH-NEXT: flh fa5, -273(a0)175; RV32IZFH-NEXT: fadd.h fa0, fa0, fa5176; RV32IZFH-NEXT: fsh fa0, -273(a0)177; RV32IZFH-NEXT: ret178;179; RV64IZFH-LABEL: flh_fsh_constant:180; RV64IZFH: # %bb.0:181; RV64IZFH-NEXT: lui a0, 228023182; RV64IZFH-NEXT: slli a0, a0, 2183; RV64IZFH-NEXT: flh fa5, -273(a0)184; RV64IZFH-NEXT: fadd.h fa0, fa0, fa5185; RV64IZFH-NEXT: fsh fa0, -273(a0)186; RV64IZFH-NEXT: ret187;188; RV32IZHINX-LABEL: flh_fsh_constant:189; RV32IZHINX: # %bb.0:190; RV32IZHINX-NEXT: lui a1, 912092191; RV32IZHINX-NEXT: lh a2, -273(a1)192; RV32IZHINX-NEXT: fadd.h a0, a0, a2193; RV32IZHINX-NEXT: sh a0, -273(a1)194; RV32IZHINX-NEXT: ret195;196; RV64IZHINX-LABEL: flh_fsh_constant:197; RV64IZHINX: # %bb.0:198; RV64IZHINX-NEXT: lui a1, 228023199; RV64IZHINX-NEXT: slli a1, a1, 2200; RV64IZHINX-NEXT: lh a2, -273(a1)201; RV64IZHINX-NEXT: fadd.h a0, a0, a2202; RV64IZHINX-NEXT: sh a0, -273(a1)203; RV64IZHINX-NEXT: ret204;205; RV32IZFHMIN-LABEL: flh_fsh_constant:206; RV32IZFHMIN: # %bb.0:207; RV32IZFHMIN-NEXT: lui a0, 912092208; RV32IZFHMIN-NEXT: flh fa5, -273(a0)209; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0210; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5211; RV32IZFHMIN-NEXT: fadd.s fa5, fa4, fa5212; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5213; RV32IZFHMIN-NEXT: fsh fa0, -273(a0)214; RV32IZFHMIN-NEXT: ret215;216; RV64IZFHMIN-LABEL: flh_fsh_constant:217; RV64IZFHMIN: # %bb.0:218; RV64IZFHMIN-NEXT: lui a0, 228023219; RV64IZFHMIN-NEXT: slli a0, a0, 2220; RV64IZFHMIN-NEXT: flh fa5, -273(a0)221; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0222; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5223; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5224; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5225; RV64IZFHMIN-NEXT: fsh fa0, -273(a0)226; RV64IZFHMIN-NEXT: ret227;228; RV32IZHINXMIN-LABEL: flh_fsh_constant:229; RV32IZHINXMIN: # %bb.0:230; RV32IZHINXMIN-NEXT: lui a1, 912092231; RV32IZHINXMIN-NEXT: lh a2, -273(a1)232; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0233; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2234; RV32IZHINXMIN-NEXT: fadd.s a0, a0, a2235; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0236; RV32IZHINXMIN-NEXT: sh a0, -273(a1)237; RV32IZHINXMIN-NEXT: ret238;239; RV64IZHINXMIN-LABEL: flh_fsh_constant:240; RV64IZHINXMIN: # %bb.0:241; RV64IZHINXMIN-NEXT: lui a1, 228023242; RV64IZHINXMIN-NEXT: slli a1, a1, 2243; RV64IZHINXMIN-NEXT: lh a2, -273(a1)244; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0245; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2246; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a2247; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0248; RV64IZHINXMIN-NEXT: sh a0, -273(a1)249; RV64IZHINXMIN-NEXT: ret250 %1 = inttoptr i32 3735928559 to ptr251 %2 = load volatile half, ptr %1252 %3 = fadd half %a, %2253 store half %3, ptr %1254 ret half %3255}256 257declare void @notdead(ptr)258 259define half @flh_stack(half %a) nounwind {260; RV32IZFH-LABEL: flh_stack:261; RV32IZFH: # %bb.0:262; RV32IZFH-NEXT: addi sp, sp, -16263; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill264; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill265; RV32IZFH-NEXT: fmv.h fs0, fa0266; RV32IZFH-NEXT: addi a0, sp, 4267; RV32IZFH-NEXT: call notdead268; RV32IZFH-NEXT: flh fa5, 4(sp)269; RV32IZFH-NEXT: fadd.h fa0, fa5, fs0270; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload271; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload272; RV32IZFH-NEXT: addi sp, sp, 16273; RV32IZFH-NEXT: ret274;275; RV64IZFH-LABEL: flh_stack:276; RV64IZFH: # %bb.0:277; RV64IZFH-NEXT: addi sp, sp, -16278; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill279; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill280; RV64IZFH-NEXT: fmv.h fs0, fa0281; RV64IZFH-NEXT: mv a0, sp282; RV64IZFH-NEXT: call notdead283; RV64IZFH-NEXT: flh fa5, 0(sp)284; RV64IZFH-NEXT: fadd.h fa0, fa5, fs0285; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload286; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload287; RV64IZFH-NEXT: addi sp, sp, 16288; RV64IZFH-NEXT: ret289;290; RV32IZHINX-LABEL: flh_stack:291; RV32IZHINX: # %bb.0:292; RV32IZHINX-NEXT: addi sp, sp, -16293; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill294; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill295; RV32IZHINX-NEXT: mv s0, a0296; RV32IZHINX-NEXT: addi a0, sp, 4297; RV32IZHINX-NEXT: call notdead298; RV32IZHINX-NEXT: lh a0, 4(sp)299; RV32IZHINX-NEXT: fadd.h a0, a0, s0300; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload301; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload302; RV32IZHINX-NEXT: addi sp, sp, 16303; RV32IZHINX-NEXT: ret304;305; RV64IZHINX-LABEL: flh_stack:306; RV64IZHINX: # %bb.0:307; RV64IZHINX-NEXT: addi sp, sp, -32308; RV64IZHINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill309; RV64IZHINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill310; RV64IZHINX-NEXT: mv s0, a0311; RV64IZHINX-NEXT: addi a0, sp, 12312; RV64IZHINX-NEXT: call notdead313; RV64IZHINX-NEXT: lh a0, 12(sp)314; RV64IZHINX-NEXT: fadd.h a0, a0, s0315; RV64IZHINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload316; RV64IZHINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload317; RV64IZHINX-NEXT: addi sp, sp, 32318; RV64IZHINX-NEXT: ret319;320; RV32IZFHMIN-LABEL: flh_stack:321; RV32IZFHMIN: # %bb.0:322; RV32IZFHMIN-NEXT: addi sp, sp, -16323; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill324; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill325; RV32IZFHMIN-NEXT: fmv.s fs0, fa0326; RV32IZFHMIN-NEXT: addi a0, sp, 4327; RV32IZFHMIN-NEXT: call notdead328; RV32IZFHMIN-NEXT: flh fa5, 4(sp)329; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fs0330; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5331; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4332; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5333; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload334; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload335; RV32IZFHMIN-NEXT: addi sp, sp, 16336; RV32IZFHMIN-NEXT: ret337;338; RV64IZFHMIN-LABEL: flh_stack:339; RV64IZFHMIN: # %bb.0:340; RV64IZFHMIN-NEXT: addi sp, sp, -16341; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill342; RV64IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill343; RV64IZFHMIN-NEXT: fmv.s fs0, fa0344; RV64IZFHMIN-NEXT: mv a0, sp345; RV64IZFHMIN-NEXT: call notdead346; RV64IZFHMIN-NEXT: flh fa5, 0(sp)347; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fs0348; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5349; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4350; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5351; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload352; RV64IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload353; RV64IZFHMIN-NEXT: addi sp, sp, 16354; RV64IZFHMIN-NEXT: ret355;356; RV32IZHINXMIN-LABEL: flh_stack:357; RV32IZHINXMIN: # %bb.0:358; RV32IZHINXMIN-NEXT: addi sp, sp, -16359; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill360; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill361; RV32IZHINXMIN-NEXT: mv s0, a0362; RV32IZHINXMIN-NEXT: addi a0, sp, 4363; RV32IZHINXMIN-NEXT: call notdead364; RV32IZHINXMIN-NEXT: lh a0, 4(sp)365; RV32IZHINXMIN-NEXT: fcvt.s.h a1, s0366; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0367; RV32IZHINXMIN-NEXT: fadd.s a0, a0, a1368; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0369; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload370; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload371; RV32IZHINXMIN-NEXT: addi sp, sp, 16372; RV32IZHINXMIN-NEXT: ret373;374; RV64IZHINXMIN-LABEL: flh_stack:375; RV64IZHINXMIN: # %bb.0:376; RV64IZHINXMIN-NEXT: addi sp, sp, -32377; RV64IZHINXMIN-NEXT: sd ra, 24(sp) # 8-byte Folded Spill378; RV64IZHINXMIN-NEXT: sd s0, 16(sp) # 8-byte Folded Spill379; RV64IZHINXMIN-NEXT: mv s0, a0380; RV64IZHINXMIN-NEXT: addi a0, sp, 12381; RV64IZHINXMIN-NEXT: call notdead382; RV64IZHINXMIN-NEXT: lh a0, 12(sp)383; RV64IZHINXMIN-NEXT: fcvt.s.h a1, s0384; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0385; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1386; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0387; RV64IZHINXMIN-NEXT: ld ra, 24(sp) # 8-byte Folded Reload388; RV64IZHINXMIN-NEXT: ld s0, 16(sp) # 8-byte Folded Reload389; RV64IZHINXMIN-NEXT: addi sp, sp, 32390; RV64IZHINXMIN-NEXT: ret391 %1 = alloca half, align 4392 call void @notdead(ptr %1)393 %2 = load half, ptr %1394 %3 = fadd half %2, %a ; force load in to FPR16395 ret half %3396}397 398define dso_local void @fsh_stack(half %a, half %b) nounwind {399; RV32IZFH-LABEL: fsh_stack:400; RV32IZFH: # %bb.0:401; RV32IZFH-NEXT: addi sp, sp, -16402; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill403; RV32IZFH-NEXT: fadd.h fa5, fa0, fa1404; RV32IZFH-NEXT: fsh fa5, 8(sp)405; RV32IZFH-NEXT: addi a0, sp, 8406; RV32IZFH-NEXT: call notdead407; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload408; RV32IZFH-NEXT: addi sp, sp, 16409; RV32IZFH-NEXT: ret410;411; RV64IZFH-LABEL: fsh_stack:412; RV64IZFH: # %bb.0:413; RV64IZFH-NEXT: addi sp, sp, -16414; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill415; RV64IZFH-NEXT: fadd.h fa5, fa0, fa1416; RV64IZFH-NEXT: fsh fa5, 4(sp)417; RV64IZFH-NEXT: addi a0, sp, 4418; RV64IZFH-NEXT: call notdead419; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload420; RV64IZFH-NEXT: addi sp, sp, 16421; RV64IZFH-NEXT: ret422;423; RV32IZHINX-LABEL: fsh_stack:424; RV32IZHINX: # %bb.0:425; RV32IZHINX-NEXT: addi sp, sp, -16426; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill427; RV32IZHINX-NEXT: fadd.h a0, a0, a1428; RV32IZHINX-NEXT: sh a0, 8(sp)429; RV32IZHINX-NEXT: addi a0, sp, 8430; RV32IZHINX-NEXT: call notdead431; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload432; RV32IZHINX-NEXT: addi sp, sp, 16433; RV32IZHINX-NEXT: ret434;435; RV64IZHINX-LABEL: fsh_stack:436; RV64IZHINX: # %bb.0:437; RV64IZHINX-NEXT: addi sp, sp, -16438; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill439; RV64IZHINX-NEXT: fadd.h a0, a0, a1440; RV64IZHINX-NEXT: sh a0, 4(sp)441; RV64IZHINX-NEXT: addi a0, sp, 4442; RV64IZHINX-NEXT: call notdead443; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload444; RV64IZHINX-NEXT: addi sp, sp, 16445; RV64IZHINX-NEXT: ret446;447; RV32IZFHMIN-LABEL: fsh_stack:448; RV32IZFHMIN: # %bb.0:449; RV32IZFHMIN-NEXT: addi sp, sp, -16450; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill451; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1452; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0453; RV32IZFHMIN-NEXT: fadd.s fa5, fa4, fa5454; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5455; RV32IZFHMIN-NEXT: fsh fa5, 8(sp)456; RV32IZFHMIN-NEXT: addi a0, sp, 8457; RV32IZFHMIN-NEXT: call notdead458; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload459; RV32IZFHMIN-NEXT: addi sp, sp, 16460; RV32IZFHMIN-NEXT: ret461;462; RV64IZFHMIN-LABEL: fsh_stack:463; RV64IZFHMIN: # %bb.0:464; RV64IZFHMIN-NEXT: addi sp, sp, -16465; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill466; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1467; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0468; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5469; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5470; RV64IZFHMIN-NEXT: fsh fa5, 4(sp)471; RV64IZFHMIN-NEXT: addi a0, sp, 4472; RV64IZFHMIN-NEXT: call notdead473; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload474; RV64IZFHMIN-NEXT: addi sp, sp, 16475; RV64IZFHMIN-NEXT: ret476;477; RV32IZHINXMIN-LABEL: fsh_stack:478; RV32IZHINXMIN: # %bb.0:479; RV32IZHINXMIN-NEXT: addi sp, sp, -16480; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill481; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1482; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0483; RV32IZHINXMIN-NEXT: fadd.s a0, a0, a1484; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0485; RV32IZHINXMIN-NEXT: sh a0, 8(sp)486; RV32IZHINXMIN-NEXT: addi a0, sp, 8487; RV32IZHINXMIN-NEXT: call notdead488; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload489; RV32IZHINXMIN-NEXT: addi sp, sp, 16490; RV32IZHINXMIN-NEXT: ret491;492; RV64IZHINXMIN-LABEL: fsh_stack:493; RV64IZHINXMIN: # %bb.0:494; RV64IZHINXMIN-NEXT: addi sp, sp, -16495; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill496; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1497; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0498; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1499; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0500; RV64IZHINXMIN-NEXT: sh a0, 4(sp)501; RV64IZHINXMIN-NEXT: addi a0, sp, 4502; RV64IZHINXMIN-NEXT: call notdead503; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload504; RV64IZHINXMIN-NEXT: addi sp, sp, 16505; RV64IZHINXMIN-NEXT: ret506 %1 = fadd half %a, %b ; force store from FPR16507 %2 = alloca half, align 4508 store half %1, ptr %2509 call void @notdead(ptr %2)510 ret void511}512