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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+experimental-xqcilia < %s \5; RUN: | FileCheck %s -check-prefix=RV32XQCILIA6 7define i32 @icmp_eq(i32 %a, i32 %b) nounwind {8; RV32I-LABEL: icmp_eq:9; RV32I: # %bb.0:10; RV32I-NEXT: xor a0, a0, a111; RV32I-NEXT: seqz a0, a012; RV32I-NEXT: ret13;14; RV32XQCILIA-LABEL: icmp_eq:15; RV32XQCILIA: # %bb.0:16; RV32XQCILIA-NEXT: xor a0, a0, a117; RV32XQCILIA-NEXT: seqz a0, a018; RV32XQCILIA-NEXT: ret19 %1 = icmp eq i32 %a, %b20 %2 = zext i1 %1 to i3221 ret i32 %222}23 24define i32 @icmp_eq_constant(i32 %a) nounwind {25; RV32I-LABEL: icmp_eq_constant:26; RV32I: # %bb.0:27; RV32I-NEXT: addi a0, a0, -4228; RV32I-NEXT: seqz a0, a029; RV32I-NEXT: ret30;31; RV32XQCILIA-LABEL: icmp_eq_constant:32; RV32XQCILIA: # %bb.0:33; RV32XQCILIA-NEXT: addi a0, a0, -4234; RV32XQCILIA-NEXT: seqz a0, a035; RV32XQCILIA-NEXT: ret36 %1 = icmp eq i32 %a, 4237 %2 = zext i1 %1 to i3238 ret i32 %239}40 41define i32 @icmp_eq_constant_2049(i32 %a) nounwind {42; RV32I-LABEL: icmp_eq_constant_2049:43; RV32I: # %bb.0:44; RV32I-NEXT: lui a1, 145; RV32I-NEXT: addi a1, a1, -204746; RV32I-NEXT: xor a0, a0, a147; RV32I-NEXT: seqz a0, a048; RV32I-NEXT: ret49;50; RV32XQCILIA-LABEL: icmp_eq_constant_2049:51; RV32XQCILIA: # %bb.0:52; RV32XQCILIA-NEXT: qc.e.addi a0, a0, -204953; RV32XQCILIA-NEXT: seqz a0, a054; RV32XQCILIA-NEXT: ret55 %1 = icmp eq i32 %a, 204956 %2 = zext i1 %1 to i3257 ret i32 %258}59 60define i32 @icmp_eq_constant_2048(i32 %a) nounwind {61; RV32I-LABEL: icmp_eq_constant_2048:62; RV32I: # %bb.0:63; RV32I-NEXT: addi a0, a0, -204864; RV32I-NEXT: seqz a0, a065; RV32I-NEXT: ret66;67; RV32XQCILIA-LABEL: icmp_eq_constant_2048:68; RV32XQCILIA: # %bb.0:69; RV32XQCILIA-NEXT: addi a0, a0, -204870; RV32XQCILIA-NEXT: seqz a0, a071; RV32XQCILIA-NEXT: ret72 %1 = icmp eq i32 %a, 204873 %2 = zext i1 %1 to i3274 ret i32 %275}76 77define i32 @icmp_eq_constant_neg_2048(i32 %a) nounwind {78; RV32I-LABEL: icmp_eq_constant_neg_2048:79; RV32I: # %bb.0:80; RV32I-NEXT: xori a0, a0, -204881; RV32I-NEXT: seqz a0, a082; RV32I-NEXT: ret83;84; RV32XQCILIA-LABEL: icmp_eq_constant_neg_2048:85; RV32XQCILIA: # %bb.0:86; RV32XQCILIA-NEXT: xori a0, a0, -204887; RV32XQCILIA-NEXT: seqz a0, a088; RV32XQCILIA-NEXT: ret89 %1 = icmp eq i32 %a, -204890 %2 = zext i1 %1 to i3291 ret i32 %292}93 94define i32 @icmp_eq_constant_neg_2047(i32 %a) nounwind {95; RV32I-LABEL: icmp_eq_constant_neg_2047:96; RV32I: # %bb.0:97; RV32I-NEXT: addi a0, a0, 204798; RV32I-NEXT: seqz a0, a099; RV32I-NEXT: ret100;101; RV32XQCILIA-LABEL: icmp_eq_constant_neg_2047:102; RV32XQCILIA: # %bb.0:103; RV32XQCILIA-NEXT: addi a0, a0, 2047104; RV32XQCILIA-NEXT: seqz a0, a0105; RV32XQCILIA-NEXT: ret106 %1 = icmp eq i32 %a, -2047107 %2 = zext i1 %1 to i32108 ret i32 %2109}110 111define i32 @icmp_eqz(i32 %a) nounwind {112; RV32I-LABEL: icmp_eqz:113; RV32I: # %bb.0:114; RV32I-NEXT: seqz a0, a0115; RV32I-NEXT: ret116;117; RV32XQCILIA-LABEL: icmp_eqz:118; RV32XQCILIA: # %bb.0:119; RV32XQCILIA-NEXT: seqz a0, a0120; RV32XQCILIA-NEXT: ret121 %1 = icmp eq i32 %a, 0122 %2 = zext i1 %1 to i32123 ret i32 %2124}125 126define i32 @icmp_eq_constant_neg_33554431(i32 %a) nounwind {127; RV32I-LABEL: icmp_eq_constant_neg_33554431:128; RV32I: # %bb.0:129; RV32I-NEXT: lui a1, 8192130; RV32I-NEXT: addi a1, a1, -1131; RV32I-NEXT: xor a0, a0, a1132; RV32I-NEXT: seqz a0, a0133; RV32I-NEXT: ret134;135; RV32XQCILIA-LABEL: icmp_eq_constant_neg_33554431:136; RV32XQCILIA: # %bb.0:137; RV32XQCILIA-NEXT: qc.e.addi a0, a0, -33554431138; RV32XQCILIA-NEXT: seqz a0, a0139; RV32XQCILIA-NEXT: ret140 %1 = icmp eq i32 %a, 33554431141 %2 = zext i1 %1 to i32142 ret i32 %2143}144 145define i32 @icmp_eq_constant_33554432(i32 %a) nounwind {146; RV32I-LABEL: icmp_eq_constant_33554432:147; RV32I: # %bb.0:148; RV32I-NEXT: lui a1, 8192149; RV32I-NEXT: xor a0, a0, a1150; RV32I-NEXT: seqz a0, a0151; RV32I-NEXT: ret152;153; RV32XQCILIA-LABEL: icmp_eq_constant_33554432:154; RV32XQCILIA: # %bb.0:155; RV32XQCILIA-NEXT: lui a1, 8192156; RV32XQCILIA-NEXT: xor a0, a0, a1157; RV32XQCILIA-NEXT: seqz a0, a0158; RV32XQCILIA-NEXT: ret159 %1 = icmp eq i32 %a, 33554432160 %2 = zext i1 %1 to i32161 ret i32 %2162}163 164define i32 @icmp_ne(i32 %a, i32 %b) nounwind {165; RV32I-LABEL: icmp_ne:166; RV32I: # %bb.0:167; RV32I-NEXT: xor a0, a0, a1168; RV32I-NEXT: snez a0, a0169; RV32I-NEXT: ret170;171; RV32XQCILIA-LABEL: icmp_ne:172; RV32XQCILIA: # %bb.0:173; RV32XQCILIA-NEXT: xor a0, a0, a1174; RV32XQCILIA-NEXT: snez a0, a0175; RV32XQCILIA-NEXT: ret176 %1 = icmp ne i32 %a, %b177 %2 = zext i1 %1 to i32178 ret i32 %2179}180 181define i32 @icmp_ne_constant(i32 %a) nounwind {182; RV32I-LABEL: icmp_ne_constant:183; RV32I: # %bb.0:184; RV32I-NEXT: addi a0, a0, -42185; RV32I-NEXT: snez a0, a0186; RV32I-NEXT: ret187;188; RV32XQCILIA-LABEL: icmp_ne_constant:189; RV32XQCILIA: # %bb.0:190; RV32XQCILIA-NEXT: addi a0, a0, -42191; RV32XQCILIA-NEXT: snez a0, a0192; RV32XQCILIA-NEXT: ret193 %1 = icmp ne i32 %a, 42194 %2 = zext i1 %1 to i32195 ret i32 %2196}197 198define i32 @icmp_ne_constant_2049(i32 %a) nounwind {199; RV32I-LABEL: icmp_ne_constant_2049:200; RV32I: # %bb.0:201; RV32I-NEXT: lui a1, 1202; RV32I-NEXT: addi a1, a1, -2047203; RV32I-NEXT: xor a0, a0, a1204; RV32I-NEXT: snez a0, a0205; RV32I-NEXT: ret206;207; RV32XQCILIA-LABEL: icmp_ne_constant_2049:208; RV32XQCILIA: # %bb.0:209; RV32XQCILIA-NEXT: qc.e.addi a0, a0, -2049210; RV32XQCILIA-NEXT: snez a0, a0211; RV32XQCILIA-NEXT: ret212 %1 = icmp ne i32 %a, 2049213 %2 = zext i1 %1 to i32214 ret i32 %2215}216 217define i32 @icmp_ne_constant_2048(i32 %a) nounwind {218; RV32I-LABEL: icmp_ne_constant_2048:219; RV32I: # %bb.0:220; RV32I-NEXT: addi a0, a0, -2048221; RV32I-NEXT: snez a0, a0222; RV32I-NEXT: ret223;224; RV32XQCILIA-LABEL: icmp_ne_constant_2048:225; RV32XQCILIA: # %bb.0:226; RV32XQCILIA-NEXT: addi a0, a0, -2048227; RV32XQCILIA-NEXT: snez a0, a0228; RV32XQCILIA-NEXT: ret229 %1 = icmp ne i32 %a, 2048230 %2 = zext i1 %1 to i32231 ret i32 %2232}233 234define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind {235; RV32I-LABEL: icmp_ne_constant_neg_2048:236; RV32I: # %bb.0:237; RV32I-NEXT: xori a0, a0, -2048238; RV32I-NEXT: snez a0, a0239; RV32I-NEXT: ret240;241; RV32XQCILIA-LABEL: icmp_ne_constant_neg_2048:242; RV32XQCILIA: # %bb.0:243; RV32XQCILIA-NEXT: xori a0, a0, -2048244; RV32XQCILIA-NEXT: snez a0, a0245; RV32XQCILIA-NEXT: ret246 %1 = icmp ne i32 %a, -2048247 %2 = zext i1 %1 to i32248 ret i32 %2249}250 251define i32 @icmp_ne_constant_neg_2047(i32 %a) nounwind {252; RV32I-LABEL: icmp_ne_constant_neg_2047:253; RV32I: # %bb.0:254; RV32I-NEXT: addi a0, a0, 2047255; RV32I-NEXT: snez a0, a0256; RV32I-NEXT: ret257;258; RV32XQCILIA-LABEL: icmp_ne_constant_neg_2047:259; RV32XQCILIA: # %bb.0:260; RV32XQCILIA-NEXT: addi a0, a0, 2047261; RV32XQCILIA-NEXT: snez a0, a0262; RV32XQCILIA-NEXT: ret263 %1 = icmp ne i32 %a, -2047264 %2 = zext i1 %1 to i32265 ret i32 %2266}267 268define i32 @icmp_ne_constant_neg_33554431(i32 %a) nounwind {269; RV32I-LABEL: icmp_ne_constant_neg_33554431:270; RV32I: # %bb.0:271; RV32I-NEXT: lui a1, 8192272; RV32I-NEXT: addi a1, a1, -1273; RV32I-NEXT: xor a0, a0, a1274; RV32I-NEXT: snez a0, a0275; RV32I-NEXT: ret276;277; RV32XQCILIA-LABEL: icmp_ne_constant_neg_33554431:278; RV32XQCILIA: # %bb.0:279; RV32XQCILIA-NEXT: qc.e.addi a0, a0, -33554431280; RV32XQCILIA-NEXT: snez a0, a0281; RV32XQCILIA-NEXT: ret282 %1 = icmp ne i32 %a, 33554431283 %2 = zext i1 %1 to i32284 ret i32 %2285}286 287define i32 @icmp_ne_constant_33554432(i32 %a) nounwind {288; RV32I-LABEL: icmp_ne_constant_33554432:289; RV32I: # %bb.0:290; RV32I-NEXT: lui a1, 8192291; RV32I-NEXT: xor a0, a0, a1292; RV32I-NEXT: snez a0, a0293; RV32I-NEXT: ret294;295; RV32XQCILIA-LABEL: icmp_ne_constant_33554432:296; RV32XQCILIA: # %bb.0:297; RV32XQCILIA-NEXT: lui a1, 8192298; RV32XQCILIA-NEXT: xor a0, a0, a1299; RV32XQCILIA-NEXT: snez a0, a0300; RV32XQCILIA-NEXT: ret301 %1 = icmp ne i32 %a, 33554432302 %2 = zext i1 %1 to i32303 ret i32 %2304}305 306define i32 @icmp_nez(i32 %a) nounwind {307; RV32I-LABEL: icmp_nez:308; RV32I: # %bb.0:309; RV32I-NEXT: snez a0, a0310; RV32I-NEXT: ret311;312; RV32XQCILIA-LABEL: icmp_nez:313; RV32XQCILIA: # %bb.0:314; RV32XQCILIA-NEXT: snez a0, a0315; RV32XQCILIA-NEXT: ret316 %1 = icmp ne i32 %a, 0317 %2 = zext i1 %1 to i32318 ret i32 %2319}320 321define i32 @icmp_ne_neg_1(i32 %a) nounwind {322; RV32I-LABEL: icmp_ne_neg_1:323; RV32I: # %bb.0:324; RV32I-NEXT: sltiu a0, a0, -1325; RV32I-NEXT: ret326;327; RV32XQCILIA-LABEL: icmp_ne_neg_1:328; RV32XQCILIA: # %bb.0:329; RV32XQCILIA-NEXT: sltiu a0, a0, -1330; RV32XQCILIA-NEXT: ret331 %1 = icmp ne i32 %a, -1332 %2 = zext i1 %1 to i32333 ret i32 %2334}335 336define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {337; RV32I-LABEL: icmp_ugt:338; RV32I: # %bb.0:339; RV32I-NEXT: sltu a0, a1, a0340; RV32I-NEXT: ret341;342; RV32XQCILIA-LABEL: icmp_ugt:343; RV32XQCILIA: # %bb.0:344; RV32XQCILIA-NEXT: sltu a0, a1, a0345; RV32XQCILIA-NEXT: ret346 %1 = icmp ugt i32 %a, %b347 %2 = zext i1 %1 to i32348 ret i32 %2349}350 351define i32 @icmp_ugt_constant_zero(i32 %a) nounwind {352; RV32I-LABEL: icmp_ugt_constant_zero:353; RV32I: # %bb.0:354; RV32I-NEXT: snez a0, a0355; RV32I-NEXT: ret356;357; RV32XQCILIA-LABEL: icmp_ugt_constant_zero:358; RV32XQCILIA: # %bb.0:359; RV32XQCILIA-NEXT: snez a0, a0360; RV32XQCILIA-NEXT: ret361 %1 = icmp ugt i32 %a, 0362 %2 = zext i1 %1 to i32363 ret i32 %2364}365 366define i32 @icmp_ugt_constant_2047(i32 %a) nounwind {367; RV32I-LABEL: icmp_ugt_constant_2047:368; RV32I: # %bb.0:369; RV32I-NEXT: srli a0, a0, 11370; RV32I-NEXT: snez a0, a0371; RV32I-NEXT: ret372;373; RV32XQCILIA-LABEL: icmp_ugt_constant_2047:374; RV32XQCILIA: # %bb.0:375; RV32XQCILIA-NEXT: srli a0, a0, 11376; RV32XQCILIA-NEXT: snez a0, a0377; RV32XQCILIA-NEXT: ret378 %1 = icmp ugt i32 %a, 2047379 %2 = zext i1 %1 to i32380 ret i32 %2381}382 383define i32 @icmp_ugt_constant_4095(i32 %a) nounwind {384; RV32I-LABEL: icmp_ugt_constant_4095:385; RV32I: # %bb.0:386; RV32I-NEXT: srli a0, a0, 12387; RV32I-NEXT: snez a0, a0388; RV32I-NEXT: ret389;390; RV32XQCILIA-LABEL: icmp_ugt_constant_4095:391; RV32XQCILIA: # %bb.0:392; RV32XQCILIA-NEXT: srli a0, a0, 12393; RV32XQCILIA-NEXT: snez a0, a0394; RV32XQCILIA-NEXT: ret395 %1 = icmp ugt i32 %a, 4095396 %2 = zext i1 %1 to i32397 ret i32 %2398}399 400define i32 @icmp_ugt_constant_2046(i32 %a) nounwind {401; RV32I-LABEL: icmp_ugt_constant_2046:402; RV32I: # %bb.0:403; RV32I-NEXT: sltiu a0, a0, 2047404; RV32I-NEXT: xori a0, a0, 1405; RV32I-NEXT: ret406;407; RV32XQCILIA-LABEL: icmp_ugt_constant_2046:408; RV32XQCILIA: # %bb.0:409; RV32XQCILIA-NEXT: sltiu a0, a0, 2047410; RV32XQCILIA-NEXT: xori a0, a0, 1411; RV32XQCILIA-NEXT: ret412 %1 = icmp ugt i32 %a, 2046413 %2 = zext i1 %1 to i32414 ret i32 %2415}416 417define i32 @icmp_ugt_constant_neg_2049(i32 %a) nounwind {418; RV32I-LABEL: icmp_ugt_constant_neg_2049:419; RV32I: # %bb.0:420; RV32I-NEXT: sltiu a0, a0, -2048421; RV32I-NEXT: xori a0, a0, 1422; RV32I-NEXT: ret423;424; RV32XQCILIA-LABEL: icmp_ugt_constant_neg_2049:425; RV32XQCILIA: # %bb.0:426; RV32XQCILIA-NEXT: sltiu a0, a0, -2048427; RV32XQCILIA-NEXT: xori a0, a0, 1428; RV32XQCILIA-NEXT: ret429; 4294965247 signed extend is -2049430 %1 = icmp ugt i32 %a, 4294965247431 %2 = zext i1 %1 to i32432 ret i32 %2433}434 435define i32 @icmp_ugt_constant_neg_2050(i32 %a) nounwind {436; RV32I-LABEL: icmp_ugt_constant_neg_2050:437; RV32I: # %bb.0:438; RV32I-NEXT: lui a1, 1048575439; RV32I-NEXT: addi a1, a1, 2046440; RV32I-NEXT: sltu a0, a1, a0441; RV32I-NEXT: ret442;443; RV32XQCILIA-LABEL: icmp_ugt_constant_neg_2050:444; RV32XQCILIA: # %bb.0:445; RV32XQCILIA-NEXT: lui a1, 1048575446; RV32XQCILIA-NEXT: addi a1, a1, 2046447; RV32XQCILIA-NEXT: sltu a0, a1, a0448; RV32XQCILIA-NEXT: ret449; 4294965246 signed extend is -2050450 %1 = icmp ugt i32 %a, 4294965246451 %2 = zext i1 %1 to i32452 ret i32 %2453}454 455define i32 @icmp_uge(i32 %a, i32 %b) nounwind {456; RV32I-LABEL: icmp_uge:457; RV32I: # %bb.0:458; RV32I-NEXT: sltu a0, a0, a1459; RV32I-NEXT: xori a0, a0, 1460; RV32I-NEXT: ret461;462; RV32XQCILIA-LABEL: icmp_uge:463; RV32XQCILIA: # %bb.0:464; RV32XQCILIA-NEXT: sltu a0, a0, a1465; RV32XQCILIA-NEXT: xori a0, a0, 1466; RV32XQCILIA-NEXT: ret467 %1 = icmp uge i32 %a, %b468 %2 = zext i1 %1 to i32469 ret i32 %2470}471 472define i32 @icmp_uge_constant_zero(i32 %a) nounwind {473; RV32I-LABEL: icmp_uge_constant_zero:474; RV32I: # %bb.0:475; RV32I-NEXT: li a0, 1476; RV32I-NEXT: ret477;478; RV32XQCILIA-LABEL: icmp_uge_constant_zero:479; RV32XQCILIA: # %bb.0:480; RV32XQCILIA-NEXT: li a0, 1481; RV32XQCILIA-NEXT: ret482 %1 = icmp uge i32 %a, 0483 %2 = zext i1 %1 to i32484 ret i32 %2485}486 487define i32 @icmp_uge_constant_2047(i32 %a) nounwind {488; RV32I-LABEL: icmp_uge_constant_2047:489; RV32I: # %bb.0:490; RV32I-NEXT: sltiu a0, a0, 2047491; RV32I-NEXT: xori a0, a0, 1492; RV32I-NEXT: ret493;494; RV32XQCILIA-LABEL: icmp_uge_constant_2047:495; RV32XQCILIA: # %bb.0:496; RV32XQCILIA-NEXT: sltiu a0, a0, 2047497; RV32XQCILIA-NEXT: xori a0, a0, 1498; RV32XQCILIA-NEXT: ret499 %1 = icmp uge i32 %a, 2047500 %2 = zext i1 %1 to i32501 ret i32 %2502}503 504define i32 @icmp_uge_constant_2048(i32 %a) nounwind {505; RV32I-LABEL: icmp_uge_constant_2048:506; RV32I: # %bb.0:507; RV32I-NEXT: srli a0, a0, 11508; RV32I-NEXT: snez a0, a0509; RV32I-NEXT: ret510;511; RV32XQCILIA-LABEL: icmp_uge_constant_2048:512; RV32XQCILIA: # %bb.0:513; RV32XQCILIA-NEXT: srli a0, a0, 11514; RV32XQCILIA-NEXT: snez a0, a0515; RV32XQCILIA-NEXT: ret516 %1 = icmp uge i32 %a, 2048517 %2 = zext i1 %1 to i32518 ret i32 %2519}520 521define i32 @icmp_uge_constant_neg_2048(i32 %a) nounwind {522; RV32I-LABEL: icmp_uge_constant_neg_2048:523; RV32I: # %bb.0:524; RV32I-NEXT: sltiu a0, a0, -2048525; RV32I-NEXT: xori a0, a0, 1526; RV32I-NEXT: ret527;528; RV32XQCILIA-LABEL: icmp_uge_constant_neg_2048:529; RV32XQCILIA: # %bb.0:530; RV32XQCILIA-NEXT: sltiu a0, a0, -2048531; RV32XQCILIA-NEXT: xori a0, a0, 1532; RV32XQCILIA-NEXT: ret533; 4294965248 signed extend is -2048534 %1 = icmp uge i32 %a, 4294965248535 %2 = zext i1 %1 to i32536 ret i32 %2537}538 539define i32 @icmp_uge_constant_neg_2049(i32 %a) nounwind {540; RV32I-LABEL: icmp_uge_constant_neg_2049:541; RV32I: # %bb.0:542; RV32I-NEXT: lui a1, 1048575543; RV32I-NEXT: addi a1, a1, 2046544; RV32I-NEXT: sltu a0, a1, a0545; RV32I-NEXT: ret546;547; RV32XQCILIA-LABEL: icmp_uge_constant_neg_2049:548; RV32XQCILIA: # %bb.0:549; RV32XQCILIA-NEXT: lui a1, 1048575550; RV32XQCILIA-NEXT: addi a1, a1, 2046551; RV32XQCILIA-NEXT: sltu a0, a1, a0552; RV32XQCILIA-NEXT: ret553; 4294965247 signed extend is -2049554 %1 = icmp uge i32 %a, 4294965247555 %2 = zext i1 %1 to i32556 ret i32 %2557}558 559define i32 @icmp_ult(i32 %a, i32 %b) nounwind {560; RV32I-LABEL: icmp_ult:561; RV32I: # %bb.0:562; RV32I-NEXT: sltu a0, a0, a1563; RV32I-NEXT: ret564;565; RV32XQCILIA-LABEL: icmp_ult:566; RV32XQCILIA: # %bb.0:567; RV32XQCILIA-NEXT: sltu a0, a0, a1568; RV32XQCILIA-NEXT: ret569 %1 = icmp ult i32 %a, %b570 %2 = zext i1 %1 to i32571 ret i32 %2572}573 574define i32 @icmp_ult_constant_zero(i32 %a) nounwind {575; RV32I-LABEL: icmp_ult_constant_zero:576; RV32I: # %bb.0:577; RV32I-NEXT: li a0, 0578; RV32I-NEXT: ret579;580; RV32XQCILIA-LABEL: icmp_ult_constant_zero:581; RV32XQCILIA: # %bb.0:582; RV32XQCILIA-NEXT: li a0, 0583; RV32XQCILIA-NEXT: ret584 %1 = icmp ult i32 %a, 0585 %2 = zext i1 %1 to i32586 ret i32 %2587}588 589define i32 @icmp_ult_constant_2047(i32 %a) nounwind {590; RV32I-LABEL: icmp_ult_constant_2047:591; RV32I: # %bb.0:592; RV32I-NEXT: sltiu a0, a0, 2047593; RV32I-NEXT: ret594;595; RV32XQCILIA-LABEL: icmp_ult_constant_2047:596; RV32XQCILIA: # %bb.0:597; RV32XQCILIA-NEXT: sltiu a0, a0, 2047598; RV32XQCILIA-NEXT: ret599 %1 = icmp ult i32 %a, 2047600 %2 = zext i1 %1 to i32601 ret i32 %2602}603 604define i32 @icmp_ult_constant_2048(i32 %a) nounwind {605; RV32I-LABEL: icmp_ult_constant_2048:606; RV32I: # %bb.0:607; RV32I-NEXT: srli a0, a0, 11608; RV32I-NEXT: seqz a0, a0609; RV32I-NEXT: ret610;611; RV32XQCILIA-LABEL: icmp_ult_constant_2048:612; RV32XQCILIA: # %bb.0:613; RV32XQCILIA-NEXT: srli a0, a0, 11614; RV32XQCILIA-NEXT: seqz a0, a0615; RV32XQCILIA-NEXT: ret616 %1 = icmp ult i32 %a, 2048617 %2 = zext i1 %1 to i32618 ret i32 %2619}620 621define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind {622; RV32I-LABEL: icmp_ult_constant_neg_2048:623; RV32I: # %bb.0:624; RV32I-NEXT: sltiu a0, a0, -2048625; RV32I-NEXT: ret626;627; RV32XQCILIA-LABEL: icmp_ult_constant_neg_2048:628; RV32XQCILIA: # %bb.0:629; RV32XQCILIA-NEXT: sltiu a0, a0, -2048630; RV32XQCILIA-NEXT: ret631; 4294965248 signed extend is -2048632 %1 = icmp ult i32 %a, 4294965248633 %2 = zext i1 %1 to i32634 ret i32 %2635}636 637define i32 @icmp_ult_constant_neg_2049(i32 %a) nounwind {638; RV32I-LABEL: icmp_ult_constant_neg_2049:639; RV32I: # %bb.0:640; RV32I-NEXT: lui a1, 1048575641; RV32I-NEXT: addi a1, a1, 2047642; RV32I-NEXT: sltu a0, a0, a1643; RV32I-NEXT: ret644;645; RV32XQCILIA-LABEL: icmp_ult_constant_neg_2049:646; RV32XQCILIA: # %bb.0:647; RV32XQCILIA-NEXT: lui a1, 1048575648; RV32XQCILIA-NEXT: addi a1, a1, 2047649; RV32XQCILIA-NEXT: sltu a0, a0, a1650; RV32XQCILIA-NEXT: ret651; 4294965247 signed extend is -2049652 %1 = icmp ult i32 %a, 4294965247653 %2 = zext i1 %1 to i32654 ret i32 %2655}656 657define i32 @icmp_ule(i32 %a, i32 %b) nounwind {658; RV32I-LABEL: icmp_ule:659; RV32I: # %bb.0:660; RV32I-NEXT: sltu a0, a1, a0661; RV32I-NEXT: xori a0, a0, 1662; RV32I-NEXT: ret663;664; RV32XQCILIA-LABEL: icmp_ule:665; RV32XQCILIA: # %bb.0:666; RV32XQCILIA-NEXT: sltu a0, a1, a0667; RV32XQCILIA-NEXT: xori a0, a0, 1668; RV32XQCILIA-NEXT: ret669 %1 = icmp ule i32 %a, %b670 %2 = zext i1 %1 to i32671 ret i32 %2672}673 674define i32 @icmp_ule_constant_zero(i32 %a) nounwind {675; RV32I-LABEL: icmp_ule_constant_zero:676; RV32I: # %bb.0:677; RV32I-NEXT: seqz a0, a0678; RV32I-NEXT: ret679;680; RV32XQCILIA-LABEL: icmp_ule_constant_zero:681; RV32XQCILIA: # %bb.0:682; RV32XQCILIA-NEXT: seqz a0, a0683; RV32XQCILIA-NEXT: ret684 %1 = icmp ule i32 %a, 0685 %2 = zext i1 %1 to i32686 ret i32 %2687}688 689define i32 @icmp_ule_constant_2046(i32 %a) nounwind {690; RV32I-LABEL: icmp_ule_constant_2046:691; RV32I: # %bb.0:692; RV32I-NEXT: sltiu a0, a0, 2047693; RV32I-NEXT: ret694;695; RV32XQCILIA-LABEL: icmp_ule_constant_2046:696; RV32XQCILIA: # %bb.0:697; RV32XQCILIA-NEXT: sltiu a0, a0, 2047698; RV32XQCILIA-NEXT: ret699 %1 = icmp ule i32 %a, 2046700 %2 = zext i1 %1 to i32701 ret i32 %2702}703 704define i32 @icmp_ule_constant_2047(i32 %a) nounwind {705; RV32I-LABEL: icmp_ule_constant_2047:706; RV32I: # %bb.0:707; RV32I-NEXT: srli a0, a0, 11708; RV32I-NEXT: seqz a0, a0709; RV32I-NEXT: ret710;711; RV32XQCILIA-LABEL: icmp_ule_constant_2047:712; RV32XQCILIA: # %bb.0:713; RV32XQCILIA-NEXT: srli a0, a0, 11714; RV32XQCILIA-NEXT: seqz a0, a0715; RV32XQCILIA-NEXT: ret716 %1 = icmp ule i32 %a, 2047717 %2 = zext i1 %1 to i32718 ret i32 %2719}720 721define i32 @icmp_ule_constant_neg_2049(i32 %a) nounwind {722; RV32I-LABEL: icmp_ule_constant_neg_2049:723; RV32I: # %bb.0:724; RV32I-NEXT: sltiu a0, a0, -2048725; RV32I-NEXT: ret726;727; RV32XQCILIA-LABEL: icmp_ule_constant_neg_2049:728; RV32XQCILIA: # %bb.0:729; RV32XQCILIA-NEXT: sltiu a0, a0, -2048730; RV32XQCILIA-NEXT: ret731; 4294965247 signed extend is -2049732 %1 = icmp ule i32 %a, 4294965247733 %2 = zext i1 %1 to i32734 ret i32 %2735}736 737define i32 @icmp_ule_constant_neg_2050(i32 %a) nounwind {738; RV32I-LABEL: icmp_ule_constant_neg_2050:739; RV32I: # %bb.0:740; RV32I-NEXT: lui a1, 1048575741; RV32I-NEXT: addi a1, a1, 2047742; RV32I-NEXT: sltu a0, a0, a1743; RV32I-NEXT: ret744;745; RV32XQCILIA-LABEL: icmp_ule_constant_neg_2050:746; RV32XQCILIA: # %bb.0:747; RV32XQCILIA-NEXT: lui a1, 1048575748; RV32XQCILIA-NEXT: addi a1, a1, 2047749; RV32XQCILIA-NEXT: sltu a0, a0, a1750; RV32XQCILIA-NEXT: ret751; 4294965246 signed extend is -2050752 %1 = icmp ule i32 %a, 4294965246753 %2 = zext i1 %1 to i32754 ret i32 %2755}756 757define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {758; RV32I-LABEL: icmp_sgt:759; RV32I: # %bb.0:760; RV32I-NEXT: slt a0, a1, a0761; RV32I-NEXT: ret762;763; RV32XQCILIA-LABEL: icmp_sgt:764; RV32XQCILIA: # %bb.0:765; RV32XQCILIA-NEXT: slt a0, a1, a0766; RV32XQCILIA-NEXT: ret767 %1 = icmp sgt i32 %a, %b768 %2 = zext i1 %1 to i32769 ret i32 %2770}771 772define i32 @icmp_sgt_constant_zero(i32 %a) nounwind {773; RV32I-LABEL: icmp_sgt_constant_zero:774; RV32I: # %bb.0:775; RV32I-NEXT: sgtz a0, a0776; RV32I-NEXT: ret777;778; RV32XQCILIA-LABEL: icmp_sgt_constant_zero:779; RV32XQCILIA: # %bb.0:780; RV32XQCILIA-NEXT: sgtz a0, a0781; RV32XQCILIA-NEXT: ret782 %1 = icmp sgt i32 %a, 0783 %2 = zext i1 %1 to i32784 ret i32 %2785}786 787define i32 @icmp_sgt_constant_2046(i32 %a) nounwind {788; RV32I-LABEL: icmp_sgt_constant_2046:789; RV32I: # %bb.0:790; RV32I-NEXT: slti a0, a0, 2047791; RV32I-NEXT: xori a0, a0, 1792; RV32I-NEXT: ret793;794; RV32XQCILIA-LABEL: icmp_sgt_constant_2046:795; RV32XQCILIA: # %bb.0:796; RV32XQCILIA-NEXT: slti a0, a0, 2047797; RV32XQCILIA-NEXT: xori a0, a0, 1798; RV32XQCILIA-NEXT: ret799 %1 = icmp sgt i32 %a, 2046800 %2 = zext i1 %1 to i32801 ret i32 %2802}803 804define i32 @icmp_sgt_constant_2047(i32 %a) nounwind {805; RV32I-LABEL: icmp_sgt_constant_2047:806; RV32I: # %bb.0:807; RV32I-NEXT: li a1, 2047808; RV32I-NEXT: slt a0, a1, a0809; RV32I-NEXT: ret810;811; RV32XQCILIA-LABEL: icmp_sgt_constant_2047:812; RV32XQCILIA: # %bb.0:813; RV32XQCILIA-NEXT: li a1, 2047814; RV32XQCILIA-NEXT: slt a0, a1, a0815; RV32XQCILIA-NEXT: ret816 %1 = icmp sgt i32 %a, 2047817 %2 = zext i1 %1 to i32818 ret i32 %2819}820 821define i32 @icmp_sgt_constant_neg_2049(i32 %a) nounwind {822; RV32I-LABEL: icmp_sgt_constant_neg_2049:823; RV32I: # %bb.0:824; RV32I-NEXT: slti a0, a0, -2048825; RV32I-NEXT: xori a0, a0, 1826; RV32I-NEXT: ret827;828; RV32XQCILIA-LABEL: icmp_sgt_constant_neg_2049:829; RV32XQCILIA: # %bb.0:830; RV32XQCILIA-NEXT: slti a0, a0, -2048831; RV32XQCILIA-NEXT: xori a0, a0, 1832; RV32XQCILIA-NEXT: ret833 %1 = icmp sgt i32 %a, -2049834 %2 = zext i1 %1 to i32835 ret i32 %2836}837 838define i32 @icmp_sgt_constant_neg_2050(i32 %a) nounwind {839; RV32I-LABEL: icmp_sgt_constant_neg_2050:840; RV32I: # %bb.0:841; RV32I-NEXT: lui a1, 1048575842; RV32I-NEXT: addi a1, a1, 2046843; RV32I-NEXT: slt a0, a1, a0844; RV32I-NEXT: ret845;846; RV32XQCILIA-LABEL: icmp_sgt_constant_neg_2050:847; RV32XQCILIA: # %bb.0:848; RV32XQCILIA-NEXT: lui a1, 1048575849; RV32XQCILIA-NEXT: addi a1, a1, 2046850; RV32XQCILIA-NEXT: slt a0, a1, a0851; RV32XQCILIA-NEXT: ret852 %1 = icmp sgt i32 %a, -2050853 %2 = zext i1 %1 to i32854 ret i32 %2855}856 857define i32 @icmp_sge(i32 %a, i32 %b) nounwind {858; RV32I-LABEL: icmp_sge:859; RV32I: # %bb.0:860; RV32I-NEXT: slt a0, a0, a1861; RV32I-NEXT: xori a0, a0, 1862; RV32I-NEXT: ret863;864; RV32XQCILIA-LABEL: icmp_sge:865; RV32XQCILIA: # %bb.0:866; RV32XQCILIA-NEXT: slt a0, a0, a1867; RV32XQCILIA-NEXT: xori a0, a0, 1868; RV32XQCILIA-NEXT: ret869 %1 = icmp sge i32 %a, %b870 %2 = zext i1 %1 to i32871 ret i32 %2872}873 874define i32 @icmp_sge_constant_zero(i32 %a) nounwind {875; RV32I-LABEL: icmp_sge_constant_zero:876; RV32I: # %bb.0:877; RV32I-NEXT: not a0, a0878; RV32I-NEXT: srli a0, a0, 31879; RV32I-NEXT: ret880;881; RV32XQCILIA-LABEL: icmp_sge_constant_zero:882; RV32XQCILIA: # %bb.0:883; RV32XQCILIA-NEXT: not a0, a0884; RV32XQCILIA-NEXT: srli a0, a0, 31885; RV32XQCILIA-NEXT: ret886 %1 = icmp sge i32 %a, 0887 %2 = zext i1 %1 to i32888 ret i32 %2889}890 891define i32 @icmp_sge_constant_2047(i32 %a) nounwind {892; RV32I-LABEL: icmp_sge_constant_2047:893; RV32I: # %bb.0:894; RV32I-NEXT: slti a0, a0, 2047895; RV32I-NEXT: xori a0, a0, 1896; RV32I-NEXT: ret897;898; RV32XQCILIA-LABEL: icmp_sge_constant_2047:899; RV32XQCILIA: # %bb.0:900; RV32XQCILIA-NEXT: slti a0, a0, 2047901; RV32XQCILIA-NEXT: xori a0, a0, 1902; RV32XQCILIA-NEXT: ret903 %1 = icmp sge i32 %a, 2047904 %2 = zext i1 %1 to i32905 ret i32 %2906}907 908define i32 @icmp_sge_constant_2048(i32 %a) nounwind {909; RV32I-LABEL: icmp_sge_constant_2048:910; RV32I: # %bb.0:911; RV32I-NEXT: li a1, 2047912; RV32I-NEXT: slt a0, a1, a0913; RV32I-NEXT: ret914;915; RV32XQCILIA-LABEL: icmp_sge_constant_2048:916; RV32XQCILIA: # %bb.0:917; RV32XQCILIA-NEXT: li a1, 2047918; RV32XQCILIA-NEXT: slt a0, a1, a0919; RV32XQCILIA-NEXT: ret920 %1 = icmp sge i32 %a, 2048921 %2 = zext i1 %1 to i32922 ret i32 %2923}924 925define i32 @icmp_sge_constant_neg_2047(i32 %a) nounwind {926; RV32I-LABEL: icmp_sge_constant_neg_2047:927; RV32I: # %bb.0:928; RV32I-NEXT: slti a0, a0, -2047929; RV32I-NEXT: xori a0, a0, 1930; RV32I-NEXT: ret931;932; RV32XQCILIA-LABEL: icmp_sge_constant_neg_2047:933; RV32XQCILIA: # %bb.0:934; RV32XQCILIA-NEXT: slti a0, a0, -2047935; RV32XQCILIA-NEXT: xori a0, a0, 1936; RV32XQCILIA-NEXT: ret937 %1 = icmp sge i32 %a, -2047938 %2 = zext i1 %1 to i32939 ret i32 %2940}941 942define i32 @icmp_sge_constant_neg_2048(i32 %a) nounwind {943; RV32I-LABEL: icmp_sge_constant_neg_2048:944; RV32I: # %bb.0:945; RV32I-NEXT: not a0, a0946; RV32I-NEXT: srli a0, a0, 31947; RV32I-NEXT: ret948;949; RV32XQCILIA-LABEL: icmp_sge_constant_neg_2048:950; RV32XQCILIA: # %bb.0:951; RV32XQCILIA-NEXT: not a0, a0952; RV32XQCILIA-NEXT: srli a0, a0, 31953; RV32XQCILIA-NEXT: ret954 %1 = icmp sge i32 %a, 0955 %2 = zext i1 %1 to i32956 ret i32 %2957}958 959define i32 @icmp_slt(i32 %a, i32 %b) nounwind {960; RV32I-LABEL: icmp_slt:961; RV32I: # %bb.0:962; RV32I-NEXT: slt a0, a0, a1963; RV32I-NEXT: ret964;965; RV32XQCILIA-LABEL: icmp_slt:966; RV32XQCILIA: # %bb.0:967; RV32XQCILIA-NEXT: slt a0, a0, a1968; RV32XQCILIA-NEXT: ret969 %1 = icmp slt i32 %a, %b970 %2 = zext i1 %1 to i32971 ret i32 %2972}973 974define i32 @icmp_slt_constant_zero(i32 %a) nounwind {975; RV32I-LABEL: icmp_slt_constant_zero:976; RV32I: # %bb.0:977; RV32I-NEXT: srli a0, a0, 31978; RV32I-NEXT: ret979;980; RV32XQCILIA-LABEL: icmp_slt_constant_zero:981; RV32XQCILIA: # %bb.0:982; RV32XQCILIA-NEXT: srli a0, a0, 31983; RV32XQCILIA-NEXT: ret984 %1 = icmp slt i32 %a, 0985 %2 = zext i1 %1 to i32986 ret i32 %2987}988 989define i32 @icmp_slt_constant_2047(i32 %a) nounwind {990; RV32I-LABEL: icmp_slt_constant_2047:991; RV32I: # %bb.0:992; RV32I-NEXT: slti a0, a0, 2047993; RV32I-NEXT: ret994;995; RV32XQCILIA-LABEL: icmp_slt_constant_2047:996; RV32XQCILIA: # %bb.0:997; RV32XQCILIA-NEXT: slti a0, a0, 2047998; RV32XQCILIA-NEXT: ret999 %1 = icmp slt i32 %a, 20471000 %2 = zext i1 %1 to i321001 ret i32 %21002}1003 1004define i32 @icmp_slt_constant_2048(i32 %a) nounwind {1005; RV32I-LABEL: icmp_slt_constant_2048:1006; RV32I: # %bb.0:1007; RV32I-NEXT: li a1, 11008; RV32I-NEXT: slli a1, a1, 111009; RV32I-NEXT: slt a0, a0, a11010; RV32I-NEXT: ret1011;1012; RV32XQCILIA-LABEL: icmp_slt_constant_2048:1013; RV32XQCILIA: # %bb.0:1014; RV32XQCILIA-NEXT: li a1, 11015; RV32XQCILIA-NEXT: slli a1, a1, 111016; RV32XQCILIA-NEXT: slt a0, a0, a11017; RV32XQCILIA-NEXT: ret1018 %1 = icmp slt i32 %a, 20481019 %2 = zext i1 %1 to i321020 ret i32 %21021}1022 1023define i32 @icmp_slt_constant_neg_2048(i32 %a) nounwind {1024; RV32I-LABEL: icmp_slt_constant_neg_2048:1025; RV32I: # %bb.0:1026; RV32I-NEXT: slti a0, a0, -20481027; RV32I-NEXT: ret1028;1029; RV32XQCILIA-LABEL: icmp_slt_constant_neg_2048:1030; RV32XQCILIA: # %bb.0:1031; RV32XQCILIA-NEXT: slti a0, a0, -20481032; RV32XQCILIA-NEXT: ret1033 %1 = icmp slt i32 %a, -20481034 %2 = zext i1 %1 to i321035 ret i32 %21036}1037 1038define i32 @icmp_slt_constant_neg_2049(i32 %a) nounwind {1039; RV32I-LABEL: icmp_slt_constant_neg_2049:1040; RV32I: # %bb.0:1041; RV32I-NEXT: lui a1, 10485751042; RV32I-NEXT: addi a1, a1, 20471043; RV32I-NEXT: slt a0, a0, a11044; RV32I-NEXT: ret1045;1046; RV32XQCILIA-LABEL: icmp_slt_constant_neg_2049:1047; RV32XQCILIA: # %bb.0:1048; RV32XQCILIA-NEXT: lui a1, 10485751049; RV32XQCILIA-NEXT: addi a1, a1, 20471050; RV32XQCILIA-NEXT: slt a0, a0, a11051; RV32XQCILIA-NEXT: ret1052 %1 = icmp slt i32 %a, -20491053 %2 = zext i1 %1 to i321054 ret i32 %21055}1056 1057define i32 @icmp_sle(i32 %a, i32 %b) nounwind {1058; RV32I-LABEL: icmp_sle:1059; RV32I: # %bb.0:1060; RV32I-NEXT: slt a0, a1, a01061; RV32I-NEXT: xori a0, a0, 11062; RV32I-NEXT: ret1063;1064; RV32XQCILIA-LABEL: icmp_sle:1065; RV32XQCILIA: # %bb.0:1066; RV32XQCILIA-NEXT: slt a0, a1, a01067; RV32XQCILIA-NEXT: xori a0, a0, 11068; RV32XQCILIA-NEXT: ret1069 %1 = icmp sle i32 %a, %b1070 %2 = zext i1 %1 to i321071 ret i32 %21072}1073 1074define i32 @icmp_sle_constant_zero(i32 %a) nounwind {1075; RV32I-LABEL: icmp_sle_constant_zero:1076; RV32I: # %bb.0:1077; RV32I-NEXT: slti a0, a0, 11078; RV32I-NEXT: ret1079;1080; RV32XQCILIA-LABEL: icmp_sle_constant_zero:1081; RV32XQCILIA: # %bb.0:1082; RV32XQCILIA-NEXT: slti a0, a0, 11083; RV32XQCILIA-NEXT: ret1084 %1 = icmp sle i32 %a, 01085 %2 = zext i1 %1 to i321086 ret i32 %21087}1088 1089define i32 @icmp_sle_constant_2046(i32 %a) nounwind {1090; RV32I-LABEL: icmp_sle_constant_2046:1091; RV32I: # %bb.0:1092; RV32I-NEXT: slti a0, a0, 20471093; RV32I-NEXT: ret1094;1095; RV32XQCILIA-LABEL: icmp_sle_constant_2046:1096; RV32XQCILIA: # %bb.0:1097; RV32XQCILIA-NEXT: slti a0, a0, 20471098; RV32XQCILIA-NEXT: ret1099 %1 = icmp sle i32 %a, 20461100 %2 = zext i1 %1 to i321101 ret i32 %21102}1103 1104define i32 @icmp_sle_constant_2047(i32 %a) nounwind {1105; RV32I-LABEL: icmp_sle_constant_2047:1106; RV32I: # %bb.0:1107; RV32I-NEXT: li a1, 11108; RV32I-NEXT: slli a1, a1, 111109; RV32I-NEXT: slt a0, a0, a11110; RV32I-NEXT: ret1111;1112; RV32XQCILIA-LABEL: icmp_sle_constant_2047:1113; RV32XQCILIA: # %bb.0:1114; RV32XQCILIA-NEXT: li a1, 11115; RV32XQCILIA-NEXT: slli a1, a1, 111116; RV32XQCILIA-NEXT: slt a0, a0, a11117; RV32XQCILIA-NEXT: ret1118 %1 = icmp sle i32 %a, 20471119 %2 = zext i1 %1 to i321120 ret i32 %21121}1122 1123define i32 @icmp_sle_constant_neg_2049(i32 %a) nounwind {1124; RV32I-LABEL: icmp_sle_constant_neg_2049:1125; RV32I: # %bb.0:1126; RV32I-NEXT: slti a0, a0, -20481127; RV32I-NEXT: ret1128;1129; RV32XQCILIA-LABEL: icmp_sle_constant_neg_2049:1130; RV32XQCILIA: # %bb.0:1131; RV32XQCILIA-NEXT: slti a0, a0, -20481132; RV32XQCILIA-NEXT: ret1133 %1 = icmp sle i32 %a, -20491134 %2 = zext i1 %1 to i321135 ret i32 %21136}1137 1138define i32 @icmp_sle_constant_neg_2050(i32 %a) nounwind {1139; RV32I-LABEL: icmp_sle_constant_neg_2050:1140; RV32I: # %bb.0:1141; RV32I-NEXT: lui a1, 10485751142; RV32I-NEXT: addi a1, a1, 20471143; RV32I-NEXT: slt a0, a0, a11144; RV32I-NEXT: ret1145;1146; RV32XQCILIA-LABEL: icmp_sle_constant_neg_2050:1147; RV32XQCILIA: # %bb.0:1148; RV32XQCILIA-NEXT: lui a1, 10485751149; RV32XQCILIA-NEXT: addi a1, a1, 20471150; RV32XQCILIA-NEXT: slt a0, a0, a11151; RV32XQCILIA-NEXT: ret1152 %1 = icmp sle i32 %a, -20501153 %2 = zext i1 %1 to i321154 ret i32 %21155}1156 1157define i32 @mask_test_eq(i32 %x) nounwind {1158; RV32I-LABEL: mask_test_eq:1159; RV32I: # %bb.0:1160; RV32I-NEXT: slli a0, a0, 121161; RV32I-NEXT: seqz a0, a01162; RV32I-NEXT: ret1163;1164; RV32XQCILIA-LABEL: mask_test_eq:1165; RV32XQCILIA: # %bb.0:1166; RV32XQCILIA-NEXT: slli a0, a0, 121167; RV32XQCILIA-NEXT: seqz a0, a01168; RV32XQCILIA-NEXT: ret1169 %y = and i32 %x, 10485751170 %cmp = icmp eq i32 %y, 01171 %ext = zext i1 %cmp to i321172 ret i32 %ext1173}1174 1175define i32 @mask_test_ne(i32 %x) nounwind {1176; RV32I-LABEL: mask_test_ne:1177; RV32I: # %bb.0:1178; RV32I-NEXT: slli a0, a0, 121179; RV32I-NEXT: snez a0, a01180; RV32I-NEXT: ret1181;1182; RV32XQCILIA-LABEL: mask_test_ne:1183; RV32XQCILIA: # %bb.0:1184; RV32XQCILIA-NEXT: slli a0, a0, 121185; RV32XQCILIA-NEXT: snez a0, a01186; RV32XQCILIA-NEXT: ret1187 %y = and i32 %x, 10485751188 %cmp = icmp ne i32 %y, 01189 %ext = zext i1 %cmp to i321190 ret i32 %ext1191}1192 1193define i32 @mask_test_eq_simm12(i32 %x) nounwind {1194; RV32I-LABEL: mask_test_eq_simm12:1195; RV32I: # %bb.0:1196; RV32I-NEXT: andi a0, a0, 31197; RV32I-NEXT: seqz a0, a01198; RV32I-NEXT: ret1199;1200; RV32XQCILIA-LABEL: mask_test_eq_simm12:1201; RV32XQCILIA: # %bb.0:1202; RV32XQCILIA-NEXT: andi a0, a0, 31203; RV32XQCILIA-NEXT: seqz a0, a01204; RV32XQCILIA-NEXT: ret1205 %y = and i32 %x, 31206 %cmp = icmp eq i32 %y, 01207 %ext = zext i1 %cmp to i321208 ret i32 %ext1209}1210