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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64I4 5define i64 @icmp_eq(i64 %a, i64 %b) nounwind {6; RV64I-LABEL: icmp_eq:7; RV64I: # %bb.0:8; RV64I-NEXT: xor a0, a0, a19; RV64I-NEXT: seqz a0, a010; RV64I-NEXT: ret11 %1 = icmp eq i64 %a, %b12 %2 = zext i1 %1 to i6413 ret i64 %214}15 16define i64 @icmp_eq_constant(i64 %a) nounwind {17; RV64I-LABEL: icmp_eq_constant:18; RV64I: # %bb.0:19; RV64I-NEXT: addi a0, a0, -4220; RV64I-NEXT: seqz a0, a021; RV64I-NEXT: ret22 %1 = icmp eq i64 %a, 4223 %2 = zext i1 %1 to i6424 ret i64 %225}26 27define i64 @icmp_eq_constant_2049(i64 %a) nounwind {28; RV64I-LABEL: icmp_eq_constant_2049:29; RV64I: # %bb.0:30; RV64I-NEXT: lui a1, 131; RV64I-NEXT: addi a1, a1, -204732; RV64I-NEXT: xor a0, a0, a133; RV64I-NEXT: seqz a0, a034; RV64I-NEXT: ret35 %1 = icmp eq i64 %a, 204936 %2 = zext i1 %1 to i6437 ret i64 %238}39 40define i64 @icmp_eq_constant_2048(i64 %a) nounwind {41; RV64I-LABEL: icmp_eq_constant_2048:42; RV64I: # %bb.0:43; RV64I-NEXT: addi a0, a0, -204844; RV64I-NEXT: seqz a0, a045; RV64I-NEXT: ret46 %1 = icmp eq i64 %a, 204847 %2 = zext i1 %1 to i6448 ret i64 %249}50 51define i64 @icmp_eq_constant_neg_2048(i64 %a) nounwind {52; RV64I-LABEL: icmp_eq_constant_neg_2048:53; RV64I: # %bb.0:54; RV64I-NEXT: xori a0, a0, -204855; RV64I-NEXT: seqz a0, a056; RV64I-NEXT: ret57 %1 = icmp eq i64 %a, -204858 %2 = zext i1 %1 to i6459 ret i64 %260}61 62define i64 @icmp_eq_constant_neg_2047(i64 %a) nounwind {63; RV64I-LABEL: icmp_eq_constant_neg_2047:64; RV64I: # %bb.0:65; RV64I-NEXT: addi a0, a0, 204766; RV64I-NEXT: seqz a0, a067; RV64I-NEXT: ret68 %1 = icmp eq i64 %a, -204769 %2 = zext i1 %1 to i6470 ret i64 %271}72 73define i64 @icmp_eqz(i64 %a) nounwind {74; RV64I-LABEL: icmp_eqz:75; RV64I: # %bb.0:76; RV64I-NEXT: seqz a0, a077; RV64I-NEXT: ret78 %1 = icmp eq i64 %a, 079 %2 = zext i1 %1 to i6480 ret i64 %281}82 83define i64 @icmp_ne(i64 %a, i64 %b) nounwind {84; RV64I-LABEL: icmp_ne:85; RV64I: # %bb.0:86; RV64I-NEXT: xor a0, a0, a187; RV64I-NEXT: snez a0, a088; RV64I-NEXT: ret89 %1 = icmp ne i64 %a, %b90 %2 = zext i1 %1 to i6491 ret i64 %292}93 94define i64 @icmp_ne_constant(i64 %a) nounwind {95; RV64I-LABEL: icmp_ne_constant:96; RV64I: # %bb.0:97; RV64I-NEXT: addi a0, a0, -4298; RV64I-NEXT: snez a0, a099; RV64I-NEXT: ret100 %1 = icmp ne i64 %a, 42101 %2 = zext i1 %1 to i64102 ret i64 %2103}104 105define i64 @icmp_ne_constant_2049(i64 %a) nounwind {106; RV64I-LABEL: icmp_ne_constant_2049:107; RV64I: # %bb.0:108; RV64I-NEXT: lui a1, 1109; RV64I-NEXT: addi a1, a1, -2047110; RV64I-NEXT: xor a0, a0, a1111; RV64I-NEXT: snez a0, a0112; RV64I-NEXT: ret113 %1 = icmp ne i64 %a, 2049114 %2 = zext i1 %1 to i64115 ret i64 %2116}117 118define i64 @icmp_ne_constant_2048(i64 %a) nounwind {119; RV64I-LABEL: icmp_ne_constant_2048:120; RV64I: # %bb.0:121; RV64I-NEXT: addi a0, a0, -2048122; RV64I-NEXT: snez a0, a0123; RV64I-NEXT: ret124 %1 = icmp ne i64 %a, 2048125 %2 = zext i1 %1 to i64126 ret i64 %2127}128 129define i64 @icmp_ne_constant_neg_2048(i64 %a) nounwind {130; RV64I-LABEL: icmp_ne_constant_neg_2048:131; RV64I: # %bb.0:132; RV64I-NEXT: xori a0, a0, -2048133; RV64I-NEXT: snez a0, a0134; RV64I-NEXT: ret135 %1 = icmp ne i64 %a, -2048136 %2 = zext i1 %1 to i64137 ret i64 %2138}139 140define i64 @icmp_ne_constant_neg_2047(i64 %a) nounwind {141; RV64I-LABEL: icmp_ne_constant_neg_2047:142; RV64I: # %bb.0:143; RV64I-NEXT: addi a0, a0, 2047144; RV64I-NEXT: snez a0, a0145; RV64I-NEXT: ret146 %1 = icmp ne i64 %a, -2047147 %2 = zext i1 %1 to i64148 ret i64 %2149}150 151define i64 @icmp_nez(i64 %a) nounwind {152; RV64I-LABEL: icmp_nez:153; RV64I: # %bb.0:154; RV64I-NEXT: snez a0, a0155; RV64I-NEXT: ret156 %1 = icmp ne i64 %a, 0157 %2 = zext i1 %1 to i64158 ret i64 %2159}160 161define i64 @icmp_ne_neg_1(i64 %a) nounwind {162; RV64I-LABEL: icmp_ne_neg_1:163; RV64I: # %bb.0:164; RV64I-NEXT: sltiu a0, a0, -1165; RV64I-NEXT: ret166 %1 = icmp ne i64 %a, -1167 %2 = zext i1 %1 to i64168 ret i64 %2169}170 171define i64 @icmp_ugt(i64 %a, i64 %b) nounwind {172; RV64I-LABEL: icmp_ugt:173; RV64I: # %bb.0:174; RV64I-NEXT: sltu a0, a1, a0175; RV64I-NEXT: ret176 %1 = icmp ugt i64 %a, %b177 %2 = zext i1 %1 to i64178 ret i64 %2179}180 181define i64 @icmp_ugt_constant_zero(i64 %a) nounwind {182; RV64I-LABEL: icmp_ugt_constant_zero:183; RV64I: # %bb.0:184; RV64I-NEXT: snez a0, a0185; RV64I-NEXT: ret186 %1 = icmp ugt i64 %a, 0187 %2 = zext i1 %1 to i64188 ret i64 %2189}190 191define i64 @icmp_ugt_constant_2047(i64 %a) nounwind {192; RV64I-LABEL: icmp_ugt_constant_2047:193; RV64I: # %bb.0:194; RV64I-NEXT: srli a0, a0, 11195; RV64I-NEXT: snez a0, a0196; RV64I-NEXT: ret197 %1 = icmp ugt i64 %a, 2047198 %2 = zext i1 %1 to i64199 ret i64 %2200}201 202define i64 @icmp_ugt_constant_4095(i64 %a) nounwind {203; RV64I-LABEL: icmp_ugt_constant_4095:204; RV64I: # %bb.0:205; RV64I-NEXT: srli a0, a0, 12206; RV64I-NEXT: snez a0, a0207; RV64I-NEXT: ret208 %1 = icmp ugt i64 %a, 4095209 %2 = zext i1 %1 to i64210 ret i64 %2211}212 213define i64 @icmp_ugt_constant_2046(i64 %a) nounwind {214; RV64I-LABEL: icmp_ugt_constant_2046:215; RV64I: # %bb.0:216; RV64I-NEXT: sltiu a0, a0, 2047217; RV64I-NEXT: xori a0, a0, 1218; RV64I-NEXT: ret219 %1 = icmp ugt i64 %a, 2046220 %2 = zext i1 %1 to i64221 ret i64 %2222}223 224define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind {225; RV64I-LABEL: icmp_ugt_constant_neg_2049:226; RV64I: # %bb.0:227; RV64I-NEXT: sltiu a0, a0, -2048228; RV64I-NEXT: xori a0, a0, 1229; RV64I-NEXT: ret230; 18446744073709549567 signed extend is -2049231 %1 = icmp ugt i64 %a, 18446744073709549567232 %2 = zext i1 %1 to i64233 ret i64 %2234}235 236define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind {237; RV64I-LABEL: icmp_ugt_constant_neg_2050:238; RV64I: # %bb.0:239; RV64I-NEXT: lui a1, 1048575240; RV64I-NEXT: addi a1, a1, 2046241; RV64I-NEXT: sltu a0, a1, a0242; RV64I-NEXT: ret243; 18446744073709549566 signed extend is -2050244 %1 = icmp ugt i64 %a, 18446744073709549566245 %2 = zext i1 %1 to i64246 ret i64 %2247}248 249define i64 @icmp_uge(i64 %a, i64 %b) nounwind {250; RV64I-LABEL: icmp_uge:251; RV64I: # %bb.0:252; RV64I-NEXT: sltu a0, a0, a1253; RV64I-NEXT: xori a0, a0, 1254; RV64I-NEXT: ret255 %1 = icmp uge i64 %a, %b256 %2 = zext i1 %1 to i64257 ret i64 %2258}259 260define i64 @icmp_uge_constant_zero(i64 %a) nounwind {261; RV64I-LABEL: icmp_uge_constant_zero:262; RV64I: # %bb.0:263; RV64I-NEXT: li a0, 1264; RV64I-NEXT: ret265 %1 = icmp uge i64 %a, 0266 %2 = zext i1 %1 to i64267 ret i64 %2268}269 270define i64 @icmp_uge_constant_2047(i64 %a) nounwind {271; RV64I-LABEL: icmp_uge_constant_2047:272; RV64I: # %bb.0:273; RV64I-NEXT: sltiu a0, a0, 2047274; RV64I-NEXT: xori a0, a0, 1275; RV64I-NEXT: ret276 %1 = icmp uge i64 %a, 2047277 %2 = zext i1 %1 to i64278 ret i64 %2279}280 281define i64 @icmp_uge_constant_2048(i64 %a) nounwind {282; RV64I-LABEL: icmp_uge_constant_2048:283; RV64I: # %bb.0:284; RV64I-NEXT: srli a0, a0, 11285; RV64I-NEXT: snez a0, a0286; RV64I-NEXT: ret287 %1 = icmp uge i64 %a, 2048288 %2 = zext i1 %1 to i64289 ret i64 %2290}291 292define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind {293; RV64I-LABEL: icmp_uge_constant_neg_2048:294; RV64I: # %bb.0:295; RV64I-NEXT: sltiu a0, a0, -2048296; RV64I-NEXT: xori a0, a0, 1297; RV64I-NEXT: ret298; 18446744073709549568 signed extend is -2048299 %1 = icmp uge i64 %a, 18446744073709549568300 %2 = zext i1 %1 to i64301 ret i64 %2302}303 304define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind {305; RV64I-LABEL: icmp_uge_constant_neg_2049:306; RV64I: # %bb.0:307; RV64I-NEXT: lui a1, 1048575308; RV64I-NEXT: addi a1, a1, 2046309; RV64I-NEXT: sltu a0, a1, a0310; RV64I-NEXT: ret311; 18446744073709549567 signed extend is -2049312 %1 = icmp uge i64 %a, 18446744073709549567313 %2 = zext i1 %1 to i64314 ret i64 %2315}316 317define i64 @icmp_ult(i64 %a, i64 %b) nounwind {318; RV64I-LABEL: icmp_ult:319; RV64I: # %bb.0:320; RV64I-NEXT: sltu a0, a0, a1321; RV64I-NEXT: ret322 %1 = icmp ult i64 %a, %b323 %2 = zext i1 %1 to i64324 ret i64 %2325}326 327define i64 @icmp_ult_constant_zero(i64 %a) nounwind {328; RV64I-LABEL: icmp_ult_constant_zero:329; RV64I: # %bb.0:330; RV64I-NEXT: li a0, 0331; RV64I-NEXT: ret332 %1 = icmp ult i64 %a, 0333 %2 = zext i1 %1 to i64334 ret i64 %2335}336 337define i64 @icmp_ult_constant_2047(i64 %a) nounwind {338; RV64I-LABEL: icmp_ult_constant_2047:339; RV64I: # %bb.0:340; RV64I-NEXT: sltiu a0, a0, 2047341; RV64I-NEXT: ret342 %1 = icmp ult i64 %a, 2047343 %2 = zext i1 %1 to i64344 ret i64 %2345}346 347define i64 @icmp_ult_constant_2048(i64 %a) nounwind {348; RV64I-LABEL: icmp_ult_constant_2048:349; RV64I: # %bb.0:350; RV64I-NEXT: srli a0, a0, 11351; RV64I-NEXT: seqz a0, a0352; RV64I-NEXT: ret353 %1 = icmp ult i64 %a, 2048354 %2 = zext i1 %1 to i64355 ret i64 %2356}357 358define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind {359; RV64I-LABEL: icmp_ult_constant_neg_2048:360; RV64I: # %bb.0:361; RV64I-NEXT: sltiu a0, a0, -2048362; RV64I-NEXT: ret363; 18446744073709549568 signed extend is -2048364 %1 = icmp ult i64 %a, 18446744073709549568365 %2 = zext i1 %1 to i64366 ret i64 %2367}368 369define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind {370; RV64I-LABEL: icmp_ult_constant_neg_2049:371; RV64I: # %bb.0:372; RV64I-NEXT: lui a1, 1048575373; RV64I-NEXT: addi a1, a1, 2047374; RV64I-NEXT: sltu a0, a0, a1375; RV64I-NEXT: ret376; 18446744073709549567 signed extend is -2049377 %1 = icmp ult i64 %a, 18446744073709549567378 %2 = zext i1 %1 to i64379 ret i64 %2380}381 382define i64 @icmp_ule(i64 %a, i64 %b) nounwind {383; RV64I-LABEL: icmp_ule:384; RV64I: # %bb.0:385; RV64I-NEXT: sltu a0, a1, a0386; RV64I-NEXT: xori a0, a0, 1387; RV64I-NEXT: ret388 %1 = icmp ule i64 %a, %b389 %2 = zext i1 %1 to i64390 ret i64 %2391}392 393define i64 @icmp_ule_constant_zero(i64 %a) nounwind {394; RV64I-LABEL: icmp_ule_constant_zero:395; RV64I: # %bb.0:396; RV64I-NEXT: seqz a0, a0397; RV64I-NEXT: ret398 %1 = icmp ule i64 %a, 0399 %2 = zext i1 %1 to i64400 ret i64 %2401}402 403define i64 @icmp_ule_constant_2046(i64 %a) nounwind {404; RV64I-LABEL: icmp_ule_constant_2046:405; RV64I: # %bb.0:406; RV64I-NEXT: sltiu a0, a0, 2047407; RV64I-NEXT: ret408 %1 = icmp ule i64 %a, 2046409 %2 = zext i1 %1 to i64410 ret i64 %2411}412 413define i64 @icmp_ule_constant_2047(i64 %a) nounwind {414; RV64I-LABEL: icmp_ule_constant_2047:415; RV64I: # %bb.0:416; RV64I-NEXT: srli a0, a0, 11417; RV64I-NEXT: seqz a0, a0418; RV64I-NEXT: ret419 %1 = icmp ule i64 %a, 2047420 %2 = zext i1 %1 to i64421 ret i64 %2422}423 424define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind {425; RV64I-LABEL: icmp_ule_constant_neg_2049:426; RV64I: # %bb.0:427; RV64I-NEXT: sltiu a0, a0, -2048428; RV64I-NEXT: ret429; 18446744073709549567 signed extend is -2049430 %1 = icmp ule i64 %a, 18446744073709549567431 %2 = zext i1 %1 to i64432 ret i64 %2433}434 435define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind {436; RV64I-LABEL: icmp_ule_constant_neg_2050:437; RV64I: # %bb.0:438; RV64I-NEXT: lui a1, 1048575439; RV64I-NEXT: addi a1, a1, 2047440; RV64I-NEXT: sltu a0, a0, a1441; RV64I-NEXT: ret442; 18446744073709549566 signed extend is -2050443 %1 = icmp ule i64 %a, 18446744073709549566444 %2 = zext i1 %1 to i64445 ret i64 %2446}447 448define i64 @icmp_sgt(i64 %a, i64 %b) nounwind {449; RV64I-LABEL: icmp_sgt:450; RV64I: # %bb.0:451; RV64I-NEXT: slt a0, a1, a0452; RV64I-NEXT: ret453 %1 = icmp sgt i64 %a, %b454 %2 = zext i1 %1 to i64455 ret i64 %2456}457 458define i64 @icmp_sgt_constant_zero(i64 %a) nounwind {459; RV64I-LABEL: icmp_sgt_constant_zero:460; RV64I: # %bb.0:461; RV64I-NEXT: sgtz a0, a0462; RV64I-NEXT: ret463 %1 = icmp sgt i64 %a, 0464 %2 = zext i1 %1 to i64465 ret i64 %2466}467 468define i64 @icmp_sgt_constant_2046(i64 %a) nounwind {469; RV64I-LABEL: icmp_sgt_constant_2046:470; RV64I: # %bb.0:471; RV64I-NEXT: slti a0, a0, 2047472; RV64I-NEXT: xori a0, a0, 1473; RV64I-NEXT: ret474 %1 = icmp sgt i64 %a, 2046475 %2 = zext i1 %1 to i64476 ret i64 %2477}478 479define i64 @icmp_sgt_constant_2047(i64 %a) nounwind {480; RV64I-LABEL: icmp_sgt_constant_2047:481; RV64I: # %bb.0:482; RV64I-NEXT: li a1, 2047483; RV64I-NEXT: slt a0, a1, a0484; RV64I-NEXT: ret485 %1 = icmp sgt i64 %a, 2047486 %2 = zext i1 %1 to i64487 ret i64 %2488}489 490define i64 @icmp_sgt_constant_neg_2049(i64 %a) nounwind {491; RV64I-LABEL: icmp_sgt_constant_neg_2049:492; RV64I: # %bb.0:493; RV64I-NEXT: slti a0, a0, -2048494; RV64I-NEXT: xori a0, a0, 1495; RV64I-NEXT: ret496 %1 = icmp sgt i64 %a, -2049497 %2 = zext i1 %1 to i64498 ret i64 %2499}500 501define i64 @icmp_sgt_constant_neg_2050(i64 %a) nounwind {502; RV64I-LABEL: icmp_sgt_constant_neg_2050:503; RV64I: # %bb.0:504; RV64I-NEXT: lui a1, 1048575505; RV64I-NEXT: addi a1, a1, 2046506; RV64I-NEXT: slt a0, a1, a0507; RV64I-NEXT: ret508 %1 = icmp sgt i64 %a, -2050509 %2 = zext i1 %1 to i64510 ret i64 %2511}512 513define i64 @icmp_sge(i64 %a, i64 %b) nounwind {514; RV64I-LABEL: icmp_sge:515; RV64I: # %bb.0:516; RV64I-NEXT: slt a0, a0, a1517; RV64I-NEXT: xori a0, a0, 1518; RV64I-NEXT: ret519 %1 = icmp sge i64 %a, %b520 %2 = zext i1 %1 to i64521 ret i64 %2522}523 524define i64 @icmp_sge_constant_zero(i64 %a) nounwind {525; RV64I-LABEL: icmp_sge_constant_zero:526; RV64I: # %bb.0:527; RV64I-NEXT: not a0, a0528; RV64I-NEXT: srli a0, a0, 63529; RV64I-NEXT: ret530 %1 = icmp sge i64 %a, 0531 %2 = zext i1 %1 to i64532 ret i64 %2533}534 535define i64 @icmp_sge_constant_2047(i64 %a) nounwind {536; RV64I-LABEL: icmp_sge_constant_2047:537; RV64I: # %bb.0:538; RV64I-NEXT: slti a0, a0, 2047539; RV64I-NEXT: xori a0, a0, 1540; RV64I-NEXT: ret541 %1 = icmp sge i64 %a, 2047542 %2 = zext i1 %1 to i64543 ret i64 %2544}545 546define i64 @icmp_sge_constant_2048(i64 %a) nounwind {547; RV64I-LABEL: icmp_sge_constant_2048:548; RV64I: # %bb.0:549; RV64I-NEXT: li a1, 2047550; RV64I-NEXT: slt a0, a1, a0551; RV64I-NEXT: ret552 %1 = icmp sge i64 %a, 2048553 %2 = zext i1 %1 to i64554 ret i64 %2555}556 557define i64 @icmp_sge_constant_neg_2047(i64 %a) nounwind {558; RV64I-LABEL: icmp_sge_constant_neg_2047:559; RV64I: # %bb.0:560; RV64I-NEXT: slti a0, a0, -2047561; RV64I-NEXT: xori a0, a0, 1562; RV64I-NEXT: ret563 %1 = icmp sge i64 %a, -2047564 %2 = zext i1 %1 to i64565 ret i64 %2566}567 568define i64 @icmp_sge_constant_neg_2048(i64 %a) nounwind {569; RV64I-LABEL: icmp_sge_constant_neg_2048:570; RV64I: # %bb.0:571; RV64I-NEXT: not a0, a0572; RV64I-NEXT: srli a0, a0, 63573; RV64I-NEXT: ret574 %1 = icmp sge i64 %a, 0575 %2 = zext i1 %1 to i64576 ret i64 %2577}578 579define i64 @icmp_slt(i64 %a, i64 %b) nounwind {580; RV64I-LABEL: icmp_slt:581; RV64I: # %bb.0:582; RV64I-NEXT: slt a0, a0, a1583; RV64I-NEXT: ret584 %1 = icmp slt i64 %a, %b585 %2 = zext i1 %1 to i64586 ret i64 %2587}588 589define i64 @icmp_slt_constant_zero(i64 %a) nounwind {590; RV64I-LABEL: icmp_slt_constant_zero:591; RV64I: # %bb.0:592; RV64I-NEXT: srli a0, a0, 63593; RV64I-NEXT: ret594 %1 = icmp slt i64 %a, 0595 %2 = zext i1 %1 to i64596 ret i64 %2597}598 599define i64 @icmp_slt_constant_2047(i64 %a) nounwind {600; RV64I-LABEL: icmp_slt_constant_2047:601; RV64I: # %bb.0:602; RV64I-NEXT: slti a0, a0, 2047603; RV64I-NEXT: ret604 %1 = icmp slt i64 %a, 2047605 %2 = zext i1 %1 to i64606 ret i64 %2607}608 609define i64 @icmp_slt_constant_2048(i64 %a) nounwind {610; RV64I-LABEL: icmp_slt_constant_2048:611; RV64I: # %bb.0:612; RV64I-NEXT: li a1, 1613; RV64I-NEXT: slli a1, a1, 11614; RV64I-NEXT: slt a0, a0, a1615; RV64I-NEXT: ret616 %1 = icmp slt i64 %a, 2048617 %2 = zext i1 %1 to i64618 ret i64 %2619}620 621define i64 @icmp_slt_constant_neg_2048(i64 %a) nounwind {622; RV64I-LABEL: icmp_slt_constant_neg_2048:623; RV64I: # %bb.0:624; RV64I-NEXT: slti a0, a0, -2048625; RV64I-NEXT: ret626 %1 = icmp slt i64 %a, -2048627 %2 = zext i1 %1 to i64628 ret i64 %2629}630 631define i64 @icmp_slt_constant_neg_2049(i64 %a) nounwind {632; RV64I-LABEL: icmp_slt_constant_neg_2049:633; RV64I: # %bb.0:634; RV64I-NEXT: lui a1, 1048575635; RV64I-NEXT: addi a1, a1, 2047636; RV64I-NEXT: slt a0, a0, a1637; RV64I-NEXT: ret638 %1 = icmp slt i64 %a, -2049639 %2 = zext i1 %1 to i64640 ret i64 %2641}642 643define i64 @icmp_sle(i64 %a, i64 %b) nounwind {644; RV64I-LABEL: icmp_sle:645; RV64I: # %bb.0:646; RV64I-NEXT: slt a0, a1, a0647; RV64I-NEXT: xori a0, a0, 1648; RV64I-NEXT: ret649 %1 = icmp sle i64 %a, %b650 %2 = zext i1 %1 to i64651 ret i64 %2652}653 654define i64 @icmp_sle_constant_zero(i64 %a) nounwind {655; RV64I-LABEL: icmp_sle_constant_zero:656; RV64I: # %bb.0:657; RV64I-NEXT: slti a0, a0, 1658; RV64I-NEXT: ret659 %1 = icmp sle i64 %a, 0660 %2 = zext i1 %1 to i64661 ret i64 %2662}663 664define i64 @icmp_sle_constant_2046(i64 %a) nounwind {665; RV64I-LABEL: icmp_sle_constant_2046:666; RV64I: # %bb.0:667; RV64I-NEXT: slti a0, a0, 2047668; RV64I-NEXT: ret669 %1 = icmp sle i64 %a, 2046670 %2 = zext i1 %1 to i64671 ret i64 %2672}673 674define i64 @icmp_sle_constant_2047(i64 %a) nounwind {675; RV64I-LABEL: icmp_sle_constant_2047:676; RV64I: # %bb.0:677; RV64I-NEXT: li a1, 1678; RV64I-NEXT: slli a1, a1, 11679; RV64I-NEXT: slt a0, a0, a1680; RV64I-NEXT: ret681 %1 = icmp sle i64 %a, 2047682 %2 = zext i1 %1 to i64683 ret i64 %2684}685 686define i64 @icmp_sle_constant_neg_2049(i64 %a) nounwind {687; RV64I-LABEL: icmp_sle_constant_neg_2049:688; RV64I: # %bb.0:689; RV64I-NEXT: slti a0, a0, -2048690; RV64I-NEXT: ret691 %1 = icmp sle i64 %a, -2049692 %2 = zext i1 %1 to i64693 ret i64 %2694}695 696define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind {697; RV64I-LABEL: icmp_sle_constant_neg_2050:698; RV64I: # %bb.0:699; RV64I-NEXT: lui a1, 1048575700; RV64I-NEXT: addi a1, a1, 2047701; RV64I-NEXT: slt a0, a0, a1702; RV64I-NEXT: ret703 %1 = icmp sle i64 %a, -2050704 %2 = zext i1 %1 to i64705 ret i64 %2706}707 708define i64 @icmp_eq_zext_inreg_small_constant(i64 %a) nounwind {709; RV64I-LABEL: icmp_eq_zext_inreg_small_constant:710; RV64I: # %bb.0:711; RV64I-NEXT: addiw a0, a0, -123712; RV64I-NEXT: seqz a0, a0713; RV64I-NEXT: ret714 %1 = and i64 %a, 4294967295715 %2 = icmp eq i64 %1, 123716 %3 = zext i1 %2 to i64717 ret i64 %3718}719 720define i64 @icmp_eq_zext_inreg_large_constant(i64 %a) nounwind {721; RV64I-LABEL: icmp_eq_zext_inreg_large_constant:722; RV64I: # %bb.0:723; RV64I-NEXT: sext.w a0, a0724; RV64I-NEXT: lui a1, 563901725; RV64I-NEXT: addi a1, a1, -529726; RV64I-NEXT: xor a0, a0, a1727; RV64I-NEXT: seqz a0, a0728; RV64I-NEXT: ret729 %1 = and i64 %a, 4294967295730 %2 = icmp eq i64 %1, 2309737967731 %3 = zext i1 %2 to i64732 ret i64 %3733}734 735define i64 @icmp_ne_zext_inreg_small_constant(i64 %a) nounwind {736; RV64I-LABEL: icmp_ne_zext_inreg_small_constant:737; RV64I: # %bb.0:738; RV64I-NEXT: sext.w a0, a0739; RV64I-NEXT: snez a0, a0740; RV64I-NEXT: ret741 %1 = and i64 %a, 4294967295742 %2 = icmp ne i64 %1, 0743 %3 = zext i1 %2 to i64744 ret i64 %3745}746 747define i64 @icmp_ne_zext_inreg_large_constant(i64 %a) nounwind {748; RV64I-LABEL: icmp_ne_zext_inreg_large_constant:749; RV64I: # %bb.0:750; RV64I-NEXT: addiw a0, a0, 2751; RV64I-NEXT: snez a0, a0752; RV64I-NEXT: ret753 %1 = and i64 %a, 4294967295754 %2 = icmp ne i64 %1, 4294967294755 %3 = zext i1 %2 to i64756 ret i64 %3757}758 759; This used to trigger an infinite loop where we toggled between 'and' and760; 'sext_inreg'.761define i64 @icmp_ne_zext_inreg_umin(i64 %a) nounwind {762; RV64I-LABEL: icmp_ne_zext_inreg_umin:763; RV64I: # %bb.0:764; RV64I-NEXT: lui a1, 30141765; RV64I-NEXT: addi a1, a1, -747766; RV64I-NEXT: bltu a0, a1, .LBB68_2767; RV64I-NEXT: # %bb.1:768; RV64I-NEXT: mv a0, a1769; RV64I-NEXT: .LBB68_2:770; RV64I-NEXT: addi a0, a0, -123771; RV64I-NEXT: snez a0, a0772; RV64I-NEXT: ret773 %1 = call i64 @llvm.umin.i64(i64 %a, i64 123456789)774 %2 = and i64 %1, 4294967295775 %3 = icmp ne i64 %2, 123776 %4 = zext i1 %3 to i64777 ret i64 %4778}779 780define i64 @mask_test_eq(i64 %x) nounwind {781; RV64I-LABEL: mask_test_eq:782; RV64I: # %bb.0:783; RV64I-NEXT: slli a0, a0, 2784; RV64I-NEXT: seqz a0, a0785; RV64I-NEXT: ret786 %y = and i64 %x, 4611686018427387903787 %cmp = icmp eq i64 %y, 0788 %ext = zext i1 %cmp to i64789 ret i64 %ext790}791 792define i64 @mask_test_ne(i64 %x) nounwind {793; RV64I-LABEL: mask_test_ne:794; RV64I: # %bb.0:795; RV64I-NEXT: slli a0, a0, 2796; RV64I-NEXT: snez a0, a0797; RV64I-NEXT: ret798 %y = and i64 %x, 4611686018427387903799 %cmp = icmp ne i64 %y, 0800 %ext = zext i1 %cmp to i64801 ret i64 %ext802}803 804define i64 @mask_test_eq_simm12(i64 %x) nounwind {805; RV64I-LABEL: mask_test_eq_simm12:806; RV64I: # %bb.0:807; RV64I-NEXT: andi a0, a0, 3808; RV64I-NEXT: seqz a0, a0809; RV64I-NEXT: ret810 %y = and i64 %x, 3811 %cmp = icmp eq i64 %y, 0812 %ext = zext i1 %cmp to i64813 ret i64 %ext814}815 816define i64 @mask_test_eq_multiuse(i64 %x, ptr %p) nounwind {817; RV64I-LABEL: mask_test_eq_multiuse:818; RV64I: # %bb.0:819; RV64I-NEXT: slli a0, a0, 2820; RV64I-NEXT: srli a2, a0, 2821; RV64I-NEXT: seqz a0, a0822; RV64I-NEXT: sd a2, 0(a1)823; RV64I-NEXT: ret824 %y = and i64 %x, 4611686018427387903825 store i64 %y, ptr %p, align 8826 %cmp = icmp eq i64 %y, 0827 %ext = zext i1 %cmp to i64828 ret i64 %ext829}830 831