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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefix=RV32I4; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefix=RV32ZBB6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefix=RV64I8; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \9; RUN: | FileCheck %s --check-prefix=RV64ZBB10 11define i8 @abs8(i8 %x) {12; RV32I-LABEL: abs8:13; RV32I: # %bb.0:14; RV32I-NEXT: slli a1, a0, 2415; RV32I-NEXT: srai a1, a1, 3116; RV32I-NEXT: xor a0, a0, a117; RV32I-NEXT: sub a0, a0, a118; RV32I-NEXT: ret19;20; RV32ZBB-LABEL: abs8:21; RV32ZBB: # %bb.0:22; RV32ZBB-NEXT: sext.b a0, a023; RV32ZBB-NEXT: neg a1, a024; RV32ZBB-NEXT: max a0, a0, a125; RV32ZBB-NEXT: ret26;27; RV64I-LABEL: abs8:28; RV64I: # %bb.0:29; RV64I-NEXT: slli a1, a0, 5630; RV64I-NEXT: srai a1, a1, 6331; RV64I-NEXT: xor a0, a0, a132; RV64I-NEXT: sub a0, a0, a133; RV64I-NEXT: ret34;35; RV64ZBB-LABEL: abs8:36; RV64ZBB: # %bb.0:37; RV64ZBB-NEXT: sext.b a0, a038; RV64ZBB-NEXT: neg a1, a039; RV64ZBB-NEXT: max a0, a0, a140; RV64ZBB-NEXT: ret41 %abs = tail call i8 @llvm.abs.i8(i8 %x, i1 true)42 ret i8 %abs43}44 45define i8 @select_abs8(i8 %x) {46; RV32I-LABEL: select_abs8:47; RV32I: # %bb.0:48; RV32I-NEXT: slli a1, a0, 2449; RV32I-NEXT: srai a1, a1, 3150; RV32I-NEXT: xor a0, a0, a151; RV32I-NEXT: sub a0, a0, a152; RV32I-NEXT: ret53;54; RV32ZBB-LABEL: select_abs8:55; RV32ZBB: # %bb.0:56; RV32ZBB-NEXT: sext.b a0, a057; RV32ZBB-NEXT: neg a1, a058; RV32ZBB-NEXT: max a0, a0, a159; RV32ZBB-NEXT: ret60;61; RV64I-LABEL: select_abs8:62; RV64I: # %bb.0:63; RV64I-NEXT: slli a1, a0, 5664; RV64I-NEXT: srai a1, a1, 6365; RV64I-NEXT: xor a0, a0, a166; RV64I-NEXT: sub a0, a0, a167; RV64I-NEXT: ret68;69; RV64ZBB-LABEL: select_abs8:70; RV64ZBB: # %bb.0:71; RV64ZBB-NEXT: sext.b a0, a072; RV64ZBB-NEXT: neg a1, a073; RV64ZBB-NEXT: max a0, a0, a174; RV64ZBB-NEXT: ret75 %1 = icmp slt i8 %x, 076 %2 = sub nsw i8 0, %x77 %3 = select i1 %1, i8 %2, i8 %x78 ret i8 %379}80 81define i16 @abs16(i16 %x) {82; RV32I-LABEL: abs16:83; RV32I: # %bb.0:84; RV32I-NEXT: slli a1, a0, 1685; RV32I-NEXT: srai a1, a1, 3186; RV32I-NEXT: xor a0, a0, a187; RV32I-NEXT: sub a0, a0, a188; RV32I-NEXT: ret89;90; RV32ZBB-LABEL: abs16:91; RV32ZBB: # %bb.0:92; RV32ZBB-NEXT: sext.h a0, a093; RV32ZBB-NEXT: neg a1, a094; RV32ZBB-NEXT: max a0, a0, a195; RV32ZBB-NEXT: ret96;97; RV64I-LABEL: abs16:98; RV64I: # %bb.0:99; RV64I-NEXT: slli a1, a0, 48100; RV64I-NEXT: srai a1, a1, 63101; RV64I-NEXT: xor a0, a0, a1102; RV64I-NEXT: sub a0, a0, a1103; RV64I-NEXT: ret104;105; RV64ZBB-LABEL: abs16:106; RV64ZBB: # %bb.0:107; RV64ZBB-NEXT: sext.h a0, a0108; RV64ZBB-NEXT: neg a1, a0109; RV64ZBB-NEXT: max a0, a0, a1110; RV64ZBB-NEXT: ret111 %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)112 ret i16 %abs113}114 115define i16 @select_abs16(i16 %x) {116; RV32I-LABEL: select_abs16:117; RV32I: # %bb.0:118; RV32I-NEXT: slli a1, a0, 16119; RV32I-NEXT: srai a1, a1, 31120; RV32I-NEXT: xor a0, a0, a1121; RV32I-NEXT: sub a0, a0, a1122; RV32I-NEXT: ret123;124; RV32ZBB-LABEL: select_abs16:125; RV32ZBB: # %bb.0:126; RV32ZBB-NEXT: sext.h a0, a0127; RV32ZBB-NEXT: neg a1, a0128; RV32ZBB-NEXT: max a0, a0, a1129; RV32ZBB-NEXT: ret130;131; RV64I-LABEL: select_abs16:132; RV64I: # %bb.0:133; RV64I-NEXT: slli a1, a0, 48134; RV64I-NEXT: srai a1, a1, 63135; RV64I-NEXT: xor a0, a0, a1136; RV64I-NEXT: sub a0, a0, a1137; RV64I-NEXT: ret138;139; RV64ZBB-LABEL: select_abs16:140; RV64ZBB: # %bb.0:141; RV64ZBB-NEXT: sext.h a0, a0142; RV64ZBB-NEXT: neg a1, a0143; RV64ZBB-NEXT: max a0, a0, a1144; RV64ZBB-NEXT: ret145 %1 = icmp slt i16 %x, 0146 %2 = sub nsw i16 0, %x147 %3 = select i1 %1, i16 %2, i16 %x148 ret i16 %3149}150 151define i32 @abs32(i32 %x) {152; RV32I-LABEL: abs32:153; RV32I: # %bb.0:154; RV32I-NEXT: srai a1, a0, 31155; RV32I-NEXT: xor a0, a0, a1156; RV32I-NEXT: sub a0, a0, a1157; RV32I-NEXT: ret158;159; RV32ZBB-LABEL: abs32:160; RV32ZBB: # %bb.0:161; RV32ZBB-NEXT: neg a1, a0162; RV32ZBB-NEXT: max a0, a0, a1163; RV32ZBB-NEXT: ret164;165; RV64I-LABEL: abs32:166; RV64I: # %bb.0:167; RV64I-NEXT: sraiw a1, a0, 31168; RV64I-NEXT: xor a0, a0, a1169; RV64I-NEXT: subw a0, a0, a1170; RV64I-NEXT: ret171;172; RV64ZBB-LABEL: abs32:173; RV64ZBB: # %bb.0:174; RV64ZBB-NEXT: sext.w a0, a0175; RV64ZBB-NEXT: negw a1, a0176; RV64ZBB-NEXT: max a0, a0, a1177; RV64ZBB-NEXT: ret178 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)179 ret i32 %abs180}181 182define i32 @select_abs32(i32 %x) {183; RV32I-LABEL: select_abs32:184; RV32I: # %bb.0:185; RV32I-NEXT: srai a1, a0, 31186; RV32I-NEXT: xor a0, a0, a1187; RV32I-NEXT: sub a0, a0, a1188; RV32I-NEXT: ret189;190; RV32ZBB-LABEL: select_abs32:191; RV32ZBB: # %bb.0:192; RV32ZBB-NEXT: neg a1, a0193; RV32ZBB-NEXT: max a0, a0, a1194; RV32ZBB-NEXT: ret195;196; RV64I-LABEL: select_abs32:197; RV64I: # %bb.0:198; RV64I-NEXT: sraiw a1, a0, 31199; RV64I-NEXT: xor a0, a0, a1200; RV64I-NEXT: subw a0, a0, a1201; RV64I-NEXT: ret202;203; RV64ZBB-LABEL: select_abs32:204; RV64ZBB: # %bb.0:205; RV64ZBB-NEXT: sext.w a0, a0206; RV64ZBB-NEXT: negw a1, a0207; RV64ZBB-NEXT: max a0, a0, a1208; RV64ZBB-NEXT: ret209 %1 = icmp slt i32 %x, 0210 %2 = sub nsw i32 0, %x211 %3 = select i1 %1, i32 %2, i32 %x212 ret i32 %3213}214 215define i64 @abs64(i64 %x) {216; RV32I-LABEL: abs64:217; RV32I: # %bb.0:218; RV32I-NEXT: bgez a1, .LBB6_2219; RV32I-NEXT: # %bb.1:220; RV32I-NEXT: snez a2, a0221; RV32I-NEXT: neg a0, a0222; RV32I-NEXT: neg a1, a1223; RV32I-NEXT: sub a1, a1, a2224; RV32I-NEXT: .LBB6_2:225; RV32I-NEXT: ret226;227; RV32ZBB-LABEL: abs64:228; RV32ZBB: # %bb.0:229; RV32ZBB-NEXT: bgez a1, .LBB6_2230; RV32ZBB-NEXT: # %bb.1:231; RV32ZBB-NEXT: snez a2, a0232; RV32ZBB-NEXT: neg a0, a0233; RV32ZBB-NEXT: neg a1, a1234; RV32ZBB-NEXT: sub a1, a1, a2235; RV32ZBB-NEXT: .LBB6_2:236; RV32ZBB-NEXT: ret237;238; RV64I-LABEL: abs64:239; RV64I: # %bb.0:240; RV64I-NEXT: srai a1, a0, 63241; RV64I-NEXT: xor a0, a0, a1242; RV64I-NEXT: sub a0, a0, a1243; RV64I-NEXT: ret244;245; RV64ZBB-LABEL: abs64:246; RV64ZBB: # %bb.0:247; RV64ZBB-NEXT: neg a1, a0248; RV64ZBB-NEXT: max a0, a0, a1249; RV64ZBB-NEXT: ret250 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)251 ret i64 %abs252}253 254define i64 @select_abs64(i64 %x) {255; RV32I-LABEL: select_abs64:256; RV32I: # %bb.0:257; RV32I-NEXT: bgez a1, .LBB7_2258; RV32I-NEXT: # %bb.1:259; RV32I-NEXT: snez a2, a0260; RV32I-NEXT: neg a0, a0261; RV32I-NEXT: neg a1, a1262; RV32I-NEXT: sub a1, a1, a2263; RV32I-NEXT: .LBB7_2:264; RV32I-NEXT: ret265;266; RV32ZBB-LABEL: select_abs64:267; RV32ZBB: # %bb.0:268; RV32ZBB-NEXT: bgez a1, .LBB7_2269; RV32ZBB-NEXT: # %bb.1:270; RV32ZBB-NEXT: snez a2, a0271; RV32ZBB-NEXT: neg a0, a0272; RV32ZBB-NEXT: neg a1, a1273; RV32ZBB-NEXT: sub a1, a1, a2274; RV32ZBB-NEXT: .LBB7_2:275; RV32ZBB-NEXT: ret276;277; RV64I-LABEL: select_abs64:278; RV64I: # %bb.0:279; RV64I-NEXT: srai a1, a0, 63280; RV64I-NEXT: xor a0, a0, a1281; RV64I-NEXT: sub a0, a0, a1282; RV64I-NEXT: ret283;284; RV64ZBB-LABEL: select_abs64:285; RV64ZBB: # %bb.0:286; RV64ZBB-NEXT: neg a1, a0287; RV64ZBB-NEXT: max a0, a0, a1288; RV64ZBB-NEXT: ret289 %1 = icmp slt i64 %x, 0290 %2 = sub nsw i64 0, %x291 %3 = select i1 %1, i64 %2, i64 %x292 ret i64 %3293}294 295define i128 @abs128(i128 %x) {296; RV32I-LABEL: abs128:297; RV32I: # %bb.0:298; RV32I-NEXT: lw a2, 12(a1)299; RV32I-NEXT: lw a3, 0(a1)300; RV32I-NEXT: lw a4, 4(a1)301; RV32I-NEXT: lw a1, 8(a1)302; RV32I-NEXT: bgez a2, .LBB8_2303; RV32I-NEXT: # %bb.1:304; RV32I-NEXT: neg a5, a1305; RV32I-NEXT: snez a6, a4306; RV32I-NEXT: snez a7, a3307; RV32I-NEXT: snez a1, a1308; RV32I-NEXT: neg a4, a4309; RV32I-NEXT: or a6, a7, a6310; RV32I-NEXT: add a1, a2, a1311; RV32I-NEXT: sub a4, a4, a7312; RV32I-NEXT: sltu a2, a5, a6313; RV32I-NEXT: neg a7, a1314; RV32I-NEXT: sub a1, a5, a6315; RV32I-NEXT: sub a2, a7, a2316; RV32I-NEXT: neg a3, a3317; RV32I-NEXT: .LBB8_2:318; RV32I-NEXT: sw a3, 0(a0)319; RV32I-NEXT: sw a4, 4(a0)320; RV32I-NEXT: sw a1, 8(a0)321; RV32I-NEXT: sw a2, 12(a0)322; RV32I-NEXT: ret323;324; RV32ZBB-LABEL: abs128:325; RV32ZBB: # %bb.0:326; RV32ZBB-NEXT: lw a2, 12(a1)327; RV32ZBB-NEXT: lw a3, 0(a1)328; RV32ZBB-NEXT: lw a4, 4(a1)329; RV32ZBB-NEXT: lw a1, 8(a1)330; RV32ZBB-NEXT: bgez a2, .LBB8_2331; RV32ZBB-NEXT: # %bb.1:332; RV32ZBB-NEXT: neg a5, a1333; RV32ZBB-NEXT: snez a6, a4334; RV32ZBB-NEXT: snez a7, a3335; RV32ZBB-NEXT: snez a1, a1336; RV32ZBB-NEXT: neg a4, a4337; RV32ZBB-NEXT: or a6, a7, a6338; RV32ZBB-NEXT: add a1, a2, a1339; RV32ZBB-NEXT: sub a4, a4, a7340; RV32ZBB-NEXT: sltu a2, a5, a6341; RV32ZBB-NEXT: neg a7, a1342; RV32ZBB-NEXT: sub a1, a5, a6343; RV32ZBB-NEXT: sub a2, a7, a2344; RV32ZBB-NEXT: neg a3, a3345; RV32ZBB-NEXT: .LBB8_2:346; RV32ZBB-NEXT: sw a3, 0(a0)347; RV32ZBB-NEXT: sw a4, 4(a0)348; RV32ZBB-NEXT: sw a1, 8(a0)349; RV32ZBB-NEXT: sw a2, 12(a0)350; RV32ZBB-NEXT: ret351;352; RV64I-LABEL: abs128:353; RV64I: # %bb.0:354; RV64I-NEXT: bgez a1, .LBB8_2355; RV64I-NEXT: # %bb.1:356; RV64I-NEXT: snez a2, a0357; RV64I-NEXT: neg a0, a0358; RV64I-NEXT: neg a1, a1359; RV64I-NEXT: sub a1, a1, a2360; RV64I-NEXT: .LBB8_2:361; RV64I-NEXT: ret362;363; RV64ZBB-LABEL: abs128:364; RV64ZBB: # %bb.0:365; RV64ZBB-NEXT: bgez a1, .LBB8_2366; RV64ZBB-NEXT: # %bb.1:367; RV64ZBB-NEXT: snez a2, a0368; RV64ZBB-NEXT: neg a0, a0369; RV64ZBB-NEXT: neg a1, a1370; RV64ZBB-NEXT: sub a1, a1, a2371; RV64ZBB-NEXT: .LBB8_2:372; RV64ZBB-NEXT: ret373 %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)374 ret i128 %abs375}376 377define i128 @select_abs128(i128 %x) {378; RV32I-LABEL: select_abs128:379; RV32I: # %bb.0:380; RV32I-NEXT: lw a2, 12(a1)381; RV32I-NEXT: lw a3, 0(a1)382; RV32I-NEXT: lw a4, 4(a1)383; RV32I-NEXT: lw a1, 8(a1)384; RV32I-NEXT: bgez a2, .LBB9_2385; RV32I-NEXT: # %bb.1:386; RV32I-NEXT: neg a5, a1387; RV32I-NEXT: snez a6, a4388; RV32I-NEXT: snez a7, a3389; RV32I-NEXT: snez a1, a1390; RV32I-NEXT: neg a4, a4391; RV32I-NEXT: or a6, a7, a6392; RV32I-NEXT: add a1, a2, a1393; RV32I-NEXT: sub a4, a4, a7394; RV32I-NEXT: sltu a2, a5, a6395; RV32I-NEXT: neg a7, a1396; RV32I-NEXT: sub a1, a5, a6397; RV32I-NEXT: sub a2, a7, a2398; RV32I-NEXT: neg a3, a3399; RV32I-NEXT: .LBB9_2:400; RV32I-NEXT: sw a3, 0(a0)401; RV32I-NEXT: sw a4, 4(a0)402; RV32I-NEXT: sw a1, 8(a0)403; RV32I-NEXT: sw a2, 12(a0)404; RV32I-NEXT: ret405;406; RV32ZBB-LABEL: select_abs128:407; RV32ZBB: # %bb.0:408; RV32ZBB-NEXT: lw a2, 12(a1)409; RV32ZBB-NEXT: lw a3, 0(a1)410; RV32ZBB-NEXT: lw a4, 4(a1)411; RV32ZBB-NEXT: lw a1, 8(a1)412; RV32ZBB-NEXT: bgez a2, .LBB9_2413; RV32ZBB-NEXT: # %bb.1:414; RV32ZBB-NEXT: neg a5, a1415; RV32ZBB-NEXT: snez a6, a4416; RV32ZBB-NEXT: snez a7, a3417; RV32ZBB-NEXT: snez a1, a1418; RV32ZBB-NEXT: neg a4, a4419; RV32ZBB-NEXT: or a6, a7, a6420; RV32ZBB-NEXT: add a1, a2, a1421; RV32ZBB-NEXT: sub a4, a4, a7422; RV32ZBB-NEXT: sltu a2, a5, a6423; RV32ZBB-NEXT: neg a7, a1424; RV32ZBB-NEXT: sub a1, a5, a6425; RV32ZBB-NEXT: sub a2, a7, a2426; RV32ZBB-NEXT: neg a3, a3427; RV32ZBB-NEXT: .LBB9_2:428; RV32ZBB-NEXT: sw a3, 0(a0)429; RV32ZBB-NEXT: sw a4, 4(a0)430; RV32ZBB-NEXT: sw a1, 8(a0)431; RV32ZBB-NEXT: sw a2, 12(a0)432; RV32ZBB-NEXT: ret433;434; RV64I-LABEL: select_abs128:435; RV64I: # %bb.0:436; RV64I-NEXT: bgez a1, .LBB9_2437; RV64I-NEXT: # %bb.1:438; RV64I-NEXT: snez a2, a0439; RV64I-NEXT: neg a0, a0440; RV64I-NEXT: neg a1, a1441; RV64I-NEXT: sub a1, a1, a2442; RV64I-NEXT: .LBB9_2:443; RV64I-NEXT: ret444;445; RV64ZBB-LABEL: select_abs128:446; RV64ZBB: # %bb.0:447; RV64ZBB-NEXT: bgez a1, .LBB9_2448; RV64ZBB-NEXT: # %bb.1:449; RV64ZBB-NEXT: snez a2, a0450; RV64ZBB-NEXT: neg a0, a0451; RV64ZBB-NEXT: neg a1, a1452; RV64ZBB-NEXT: sub a1, a1, a2453; RV64ZBB-NEXT: .LBB9_2:454; RV64ZBB-NEXT: ret455 %1 = icmp slt i128 %x, 0456 %2 = sub nsw i128 0, %x457 %3 = select i1 %1, i128 %2, i128 %x458 ret i128 %3459}460 461define i64 @zext_abs32(i32 %x) {462; RV32I-LABEL: zext_abs32:463; RV32I: # %bb.0:464; RV32I-NEXT: srai a1, a0, 31465; RV32I-NEXT: xor a0, a0, a1466; RV32I-NEXT: sub a0, a0, a1467; RV32I-NEXT: li a1, 0468; RV32I-NEXT: ret469;470; RV32ZBB-LABEL: zext_abs32:471; RV32ZBB: # %bb.0:472; RV32ZBB-NEXT: neg a1, a0473; RV32ZBB-NEXT: max a0, a0, a1474; RV32ZBB-NEXT: li a1, 0475; RV32ZBB-NEXT: ret476;477; RV64I-LABEL: zext_abs32:478; RV64I: # %bb.0:479; RV64I-NEXT: sraiw a1, a0, 31480; RV64I-NEXT: xor a0, a0, a1481; RV64I-NEXT: subw a0, a0, a1482; RV64I-NEXT: ret483;484; RV64ZBB-LABEL: zext_abs32:485; RV64ZBB: # %bb.0:486; RV64ZBB-NEXT: sext.w a0, a0487; RV64ZBB-NEXT: negw a1, a0488; RV64ZBB-NEXT: max a0, a0, a1489; RV64ZBB-NEXT: ret490 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)491 %zext = zext nneg i32 %abs to i64492 ret i64 %zext493}494 495define signext i32 @zext_abs8(i8 signext %x) {496; RV32I-LABEL: zext_abs8:497; RV32I: # %bb.0:498; RV32I-NEXT: srai a1, a0, 31499; RV32I-NEXT: xor a0, a0, a1500; RV32I-NEXT: sub a0, a0, a1501; RV32I-NEXT: ret502;503; RV32ZBB-LABEL: zext_abs8:504; RV32ZBB: # %bb.0:505; RV32ZBB-NEXT: neg a1, a0506; RV32ZBB-NEXT: max a0, a0, a1507; RV32ZBB-NEXT: ret508;509; RV64I-LABEL: zext_abs8:510; RV64I: # %bb.0:511; RV64I-NEXT: srai a1, a0, 63512; RV64I-NEXT: xor a0, a0, a1513; RV64I-NEXT: sub a0, a0, a1514; RV64I-NEXT: ret515;516; RV64ZBB-LABEL: zext_abs8:517; RV64ZBB: # %bb.0:518; RV64ZBB-NEXT: neg a1, a0519; RV64ZBB-NEXT: max a0, a0, a1520; RV64ZBB-NEXT: ret521 %a = call i8 @llvm.abs.i8(i8 %x, i1 false)522 %b = zext i8 %a to i32523 ret i32 %b524}525 526define signext i32 @zext_abs16(i16 signext %x) {527; RV32I-LABEL: zext_abs16:528; RV32I: # %bb.0:529; RV32I-NEXT: srai a1, a0, 31530; RV32I-NEXT: xor a0, a0, a1531; RV32I-NEXT: sub a0, a0, a1532; RV32I-NEXT: ret533;534; RV32ZBB-LABEL: zext_abs16:535; RV32ZBB: # %bb.0:536; RV32ZBB-NEXT: neg a1, a0537; RV32ZBB-NEXT: max a0, a0, a1538; RV32ZBB-NEXT: ret539;540; RV64I-LABEL: zext_abs16:541; RV64I: # %bb.0:542; RV64I-NEXT: srai a1, a0, 63543; RV64I-NEXT: xor a0, a0, a1544; RV64I-NEXT: sub a0, a0, a1545; RV64I-NEXT: ret546;547; RV64ZBB-LABEL: zext_abs16:548; RV64ZBB: # %bb.0:549; RV64ZBB-NEXT: neg a1, a0550; RV64ZBB-NEXT: max a0, a0, a1551; RV64ZBB-NEXT: ret552 %a = call i16 @llvm.abs.i16(i16 %x, i1 false)553 %b = zext i16 %a to i32554 ret i32 %b555}556 557define i64 @zext64_abs8(i8 signext %x) {558; RV32I-LABEL: zext64_abs8:559; RV32I: # %bb.0:560; RV32I-NEXT: srai a1, a0, 31561; RV32I-NEXT: xor a0, a0, a1562; RV32I-NEXT: sub a0, a0, a1563; RV32I-NEXT: li a1, 0564; RV32I-NEXT: ret565;566; RV32ZBB-LABEL: zext64_abs8:567; RV32ZBB: # %bb.0:568; RV32ZBB-NEXT: neg a1, a0569; RV32ZBB-NEXT: max a0, a0, a1570; RV32ZBB-NEXT: li a1, 0571; RV32ZBB-NEXT: ret572;573; RV64I-LABEL: zext64_abs8:574; RV64I: # %bb.0:575; RV64I-NEXT: srai a1, a0, 63576; RV64I-NEXT: xor a0, a0, a1577; RV64I-NEXT: sub a0, a0, a1578; RV64I-NEXT: ret579;580; RV64ZBB-LABEL: zext64_abs8:581; RV64ZBB: # %bb.0:582; RV64ZBB-NEXT: neg a1, a0583; RV64ZBB-NEXT: max a0, a0, a1584; RV64ZBB-NEXT: ret585 %a = call i8 @llvm.abs.i8(i8 %x, i1 false)586 %b = zext i8 %a to i64587 ret i64 %b588}589 590define i64 @zext64_abs16(i16 signext %x) {591; RV32I-LABEL: zext64_abs16:592; RV32I: # %bb.0:593; RV32I-NEXT: srai a1, a0, 31594; RV32I-NEXT: xor a0, a0, a1595; RV32I-NEXT: sub a0, a0, a1596; RV32I-NEXT: li a1, 0597; RV32I-NEXT: ret598;599; RV32ZBB-LABEL: zext64_abs16:600; RV32ZBB: # %bb.0:601; RV32ZBB-NEXT: neg a1, a0602; RV32ZBB-NEXT: max a0, a0, a1603; RV32ZBB-NEXT: li a1, 0604; RV32ZBB-NEXT: ret605;606; RV64I-LABEL: zext64_abs16:607; RV64I: # %bb.0:608; RV64I-NEXT: srai a1, a0, 63609; RV64I-NEXT: xor a0, a0, a1610; RV64I-NEXT: sub a0, a0, a1611; RV64I-NEXT: ret612;613; RV64ZBB-LABEL: zext64_abs16:614; RV64ZBB: # %bb.0:615; RV64ZBB-NEXT: neg a1, a0616; RV64ZBB-NEXT: max a0, a0, a1617; RV64ZBB-NEXT: ret618 %a = call i16 @llvm.abs.i16(i16 %x, i1 false)619 %b = zext i16 %a to i64620 ret i64 %b621}622 623define void @zext16_abs8(i8 %x, ptr %p) {624; RV32I-LABEL: zext16_abs8:625; RV32I: # %bb.0:626; RV32I-NEXT: slli a0, a0, 24627; RV32I-NEXT: srai a2, a0, 31628; RV32I-NEXT: srai a0, a0, 24629; RV32I-NEXT: xor a0, a0, a2630; RV32I-NEXT: sub a0, a0, a2631; RV32I-NEXT: sh a0, 0(a1)632; RV32I-NEXT: ret633;634; RV32ZBB-LABEL: zext16_abs8:635; RV32ZBB: # %bb.0:636; RV32ZBB-NEXT: sext.b a0, a0637; RV32ZBB-NEXT: neg a2, a0638; RV32ZBB-NEXT: max a0, a0, a2639; RV32ZBB-NEXT: sh a0, 0(a1)640; RV32ZBB-NEXT: ret641;642; RV64I-LABEL: zext16_abs8:643; RV64I: # %bb.0:644; RV64I-NEXT: slli a0, a0, 56645; RV64I-NEXT: srai a2, a0, 63646; RV64I-NEXT: srai a0, a0, 56647; RV64I-NEXT: xor a0, a0, a2648; RV64I-NEXT: sub a0, a0, a2649; RV64I-NEXT: sh a0, 0(a1)650; RV64I-NEXT: ret651;652; RV64ZBB-LABEL: zext16_abs8:653; RV64ZBB: # %bb.0:654; RV64ZBB-NEXT: sext.b a0, a0655; RV64ZBB-NEXT: neg a2, a0656; RV64ZBB-NEXT: max a0, a0, a2657; RV64ZBB-NEXT: sh a0, 0(a1)658; RV64ZBB-NEXT: ret659 %a = call i8 @llvm.abs.i8(i8 %x, i1 false)660 %b = zext i8 %a to i16661 store i16 %b, ptr %p662 ret void663}664