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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs -no-integrated-as < %s \3; RUN: | FileCheck -check-prefix=RV32I %s4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -no-integrated-as < %s \5; RUN: | FileCheck -check-prefix=RV64I %s6 7; These test that we can use both the architectural names (x*) and the ABI names8; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each9; case, the named register should be used for the source register of the `addi`.10; It is very likely that `a0` will be chosen as the designation register, but11; this is left to the compiler to choose.12;13; The inline assembly will, by default, contain the ABI names for the registers.14;15; Parenthesised registers in comments are the other aliases for this register.16 17; NOTE: This test has to pass in 0 to the inline asm, because that's the only18; value `x0` (`zero`) can take.19define i32 @explicit_register_x0() nounwind {20; RV32I-LABEL: explicit_register_x0:21; RV32I: # %bb.0:22; RV32I-NEXT: #APP23; RV32I-NEXT: addi a0, zero, 024; RV32I-NEXT: #NO_APP25; RV32I-NEXT: ret26;27; RV64I-LABEL: explicit_register_x0:28; RV64I: # %bb.0:29; RV64I-NEXT: #APP30; RV64I-NEXT: addi a0, zero, 031; RV64I-NEXT: #NO_APP32; RV64I-NEXT: ret33 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x0}"(i32 0)34 ret i32 %135}36 37; NOTE: This test has to pass in 0 to the inline asm, because that's the only38; value that `zero` (`x0`) can take.39define i32 @explicit_register_zero() nounwind {40; RV32I-LABEL: explicit_register_zero:41; RV32I: # %bb.0:42; RV32I-NEXT: #APP43; RV32I-NEXT: addi a0, zero, 044; RV32I-NEXT: #NO_APP45; RV32I-NEXT: ret46;47; RV64I-LABEL: explicit_register_zero:48; RV64I: # %bb.0:49; RV64I-NEXT: #APP50; RV64I-NEXT: addi a0, zero, 051; RV64I-NEXT: #NO_APP52; RV64I-NEXT: ret53 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{zero}"(i32 0)54 ret i32 %155}56 57; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved.58define i32 @explicit_register_x1(i32 %a) nounwind {59; RV32I-LABEL: explicit_register_x1:60; RV32I: # %bb.0:61; RV32I-NEXT: addi sp, sp, -1662; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill63; RV32I-NEXT: mv ra, a064; RV32I-NEXT: #APP65; RV32I-NEXT: addi a0, ra, 066; RV32I-NEXT: #NO_APP67; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload68; RV32I-NEXT: addi sp, sp, 1669; RV32I-NEXT: ret70;71; RV64I-LABEL: explicit_register_x1:72; RV64I: # %bb.0:73; RV64I-NEXT: addi sp, sp, -1674; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill75; RV64I-NEXT: mv ra, a076; RV64I-NEXT: #APP77; RV64I-NEXT: addi a0, ra, 078; RV64I-NEXT: #NO_APP79; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload80; RV64I-NEXT: addi sp, sp, 1681; RV64I-NEXT: ret82 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a)83 ret i32 %184}85 86; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved.87define i32 @explicit_register_ra(i32 %a) nounwind {88; RV32I-LABEL: explicit_register_ra:89; RV32I: # %bb.0:90; RV32I-NEXT: addi sp, sp, -1691; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill92; RV32I-NEXT: mv ra, a093; RV32I-NEXT: #APP94; RV32I-NEXT: addi a0, ra, 095; RV32I-NEXT: #NO_APP96; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload97; RV32I-NEXT: addi sp, sp, 1698; RV32I-NEXT: ret99;100; RV64I-LABEL: explicit_register_ra:101; RV64I: # %bb.0:102; RV64I-NEXT: addi sp, sp, -16103; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill104; RV64I-NEXT: mv ra, a0105; RV64I-NEXT: #APP106; RV64I-NEXT: addi a0, ra, 0107; RV64I-NEXT: #NO_APP108; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload109; RV64I-NEXT: addi sp, sp, 16110; RV64I-NEXT: ret111 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a)112 ret i32 %1113}114 115define i32 @explicit_register_x2(i32 %a) nounwind {116; RV32I-LABEL: explicit_register_x2:117; RV32I: # %bb.0:118; RV32I-NEXT: mv sp, a0119; RV32I-NEXT: #APP120; RV32I-NEXT: addi a0, sp, 0121; RV32I-NEXT: #NO_APP122; RV32I-NEXT: ret123;124; RV64I-LABEL: explicit_register_x2:125; RV64I: # %bb.0:126; RV64I-NEXT: mv sp, a0127; RV64I-NEXT: #APP128; RV64I-NEXT: addi a0, sp, 0129; RV64I-NEXT: #NO_APP130; RV64I-NEXT: ret131 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x2}"(i32 %a)132 ret i32 %1133}134 135define i32 @explicit_register_sp(i32 %a) nounwind {136; RV32I-LABEL: explicit_register_sp:137; RV32I: # %bb.0:138; RV32I-NEXT: mv sp, a0139; RV32I-NEXT: #APP140; RV32I-NEXT: addi a0, sp, 0141; RV32I-NEXT: #NO_APP142; RV32I-NEXT: ret143;144; RV64I-LABEL: explicit_register_sp:145; RV64I: # %bb.0:146; RV64I-NEXT: mv sp, a0147; RV64I-NEXT: #APP148; RV64I-NEXT: addi a0, sp, 0149; RV64I-NEXT: #NO_APP150; RV64I-NEXT: ret151 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{sp}"(i32 %a)152 ret i32 %1153}154 155; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved.156define i32 @explicit_register_x3(i32 %a) nounwind {157; RV32I-LABEL: explicit_register_x3:158; RV32I: # %bb.0:159; RV32I-NEXT: mv gp, a0160; RV32I-NEXT: #APP161; RV32I-NEXT: addi a0, gp, 0162; RV32I-NEXT: #NO_APP163; RV32I-NEXT: ret164;165; RV64I-LABEL: explicit_register_x3:166; RV64I: # %bb.0:167; RV64I-NEXT: mv gp, a0168; RV64I-NEXT: #APP169; RV64I-NEXT: addi a0, gp, 0170; RV64I-NEXT: #NO_APP171; RV64I-NEXT: ret172 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a)173 ret i32 %1174}175 176; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved.177define i32 @explicit_register_gp(i32 %a) nounwind {178; RV32I-LABEL: explicit_register_gp:179; RV32I: # %bb.0:180; RV32I-NEXT: mv gp, a0181; RV32I-NEXT: #APP182; RV32I-NEXT: addi a0, gp, 0183; RV32I-NEXT: #NO_APP184; RV32I-NEXT: ret185;186; RV64I-LABEL: explicit_register_gp:187; RV64I: # %bb.0:188; RV64I-NEXT: mv gp, a0189; RV64I-NEXT: #APP190; RV64I-NEXT: addi a0, gp, 0191; RV64I-NEXT: #NO_APP192; RV64I-NEXT: ret193 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a)194 ret i32 %1195}196 197; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved.198define i32 @explicit_register_x4(i32 %a) nounwind {199; RV32I-LABEL: explicit_register_x4:200; RV32I: # %bb.0:201; RV32I-NEXT: mv tp, a0202; RV32I-NEXT: #APP203; RV32I-NEXT: addi a0, tp, 0204; RV32I-NEXT: #NO_APP205; RV32I-NEXT: ret206;207; RV64I-LABEL: explicit_register_x4:208; RV64I: # %bb.0:209; RV64I-NEXT: mv tp, a0210; RV64I-NEXT: #APP211; RV64I-NEXT: addi a0, tp, 0212; RV64I-NEXT: #NO_APP213; RV64I-NEXT: ret214 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a)215 ret i32 %1216}217 218; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved.219define i32 @explicit_register_tp(i32 %a) nounwind {220; RV32I-LABEL: explicit_register_tp:221; RV32I: # %bb.0:222; RV32I-NEXT: mv tp, a0223; RV32I-NEXT: #APP224; RV32I-NEXT: addi a0, tp, 0225; RV32I-NEXT: #NO_APP226; RV32I-NEXT: ret227;228; RV64I-LABEL: explicit_register_tp:229; RV64I: # %bb.0:230; RV64I-NEXT: mv tp, a0231; RV64I-NEXT: #APP232; RV64I-NEXT: addi a0, tp, 0233; RV64I-NEXT: #NO_APP234; RV64I-NEXT: ret235 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a)236 ret i32 %1237}238 239define i32 @explicit_register_x5(i32 %a) nounwind {240; RV32I-LABEL: explicit_register_x5:241; RV32I: # %bb.0:242; RV32I-NEXT: mv t0, a0243; RV32I-NEXT: #APP244; RV32I-NEXT: addi a0, t0, 0245; RV32I-NEXT: #NO_APP246; RV32I-NEXT: ret247;248; RV64I-LABEL: explicit_register_x5:249; RV64I: # %bb.0:250; RV64I-NEXT: mv t0, a0251; RV64I-NEXT: #APP252; RV64I-NEXT: addi a0, t0, 0253; RV64I-NEXT: #NO_APP254; RV64I-NEXT: ret255 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x5}"(i32 %a)256 ret i32 %1257}258 259define i32 @explicit_register_t0(i32 %a) nounwind {260; RV32I-LABEL: explicit_register_t0:261; RV32I: # %bb.0:262; RV32I-NEXT: mv t0, a0263; RV32I-NEXT: #APP264; RV32I-NEXT: addi a0, t0, 0265; RV32I-NEXT: #NO_APP266; RV32I-NEXT: ret267;268; RV64I-LABEL: explicit_register_t0:269; RV64I: # %bb.0:270; RV64I-NEXT: mv t0, a0271; RV64I-NEXT: #APP272; RV64I-NEXT: addi a0, t0, 0273; RV64I-NEXT: #NO_APP274; RV64I-NEXT: ret275 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t0}"(i32 %a)276 ret i32 %1277}278 279define i32 @explicit_register_x6(i32 %a) nounwind {280; RV32I-LABEL: explicit_register_x6:281; RV32I: # %bb.0:282; RV32I-NEXT: mv t1, a0283; RV32I-NEXT: #APP284; RV32I-NEXT: addi a0, t1, 0285; RV32I-NEXT: #NO_APP286; RV32I-NEXT: ret287;288; RV64I-LABEL: explicit_register_x6:289; RV64I: # %bb.0:290; RV64I-NEXT: mv t1, a0291; RV64I-NEXT: #APP292; RV64I-NEXT: addi a0, t1, 0293; RV64I-NEXT: #NO_APP294; RV64I-NEXT: ret295 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x6}"(i32 %a)296 ret i32 %1297}298 299define i32 @explicit_register_t1(i32 %a) nounwind {300; RV32I-LABEL: explicit_register_t1:301; RV32I: # %bb.0:302; RV32I-NEXT: mv t1, a0303; RV32I-NEXT: #APP304; RV32I-NEXT: addi a0, t1, 0305; RV32I-NEXT: #NO_APP306; RV32I-NEXT: ret307;308; RV64I-LABEL: explicit_register_t1:309; RV64I: # %bb.0:310; RV64I-NEXT: mv t1, a0311; RV64I-NEXT: #APP312; RV64I-NEXT: addi a0, t1, 0313; RV64I-NEXT: #NO_APP314; RV64I-NEXT: ret315 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t1}"(i32 %a)316 ret i32 %1317}318 319define i32 @explicit_register_x7(i32 %a) nounwind {320; RV32I-LABEL: explicit_register_x7:321; RV32I: # %bb.0:322; RV32I-NEXT: mv t2, a0323; RV32I-NEXT: #APP324; RV32I-NEXT: addi a0, t2, 0325; RV32I-NEXT: #NO_APP326; RV32I-NEXT: ret327;328; RV64I-LABEL: explicit_register_x7:329; RV64I: # %bb.0:330; RV64I-NEXT: mv t2, a0331; RV64I-NEXT: #APP332; RV64I-NEXT: addi a0, t2, 0333; RV64I-NEXT: #NO_APP334; RV64I-NEXT: ret335 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x7}"(i32 %a)336 ret i32 %1337}338 339define i32 @explicit_register_t2(i32 %a) nounwind {340; RV32I-LABEL: explicit_register_t2:341; RV32I: # %bb.0:342; RV32I-NEXT: mv t2, a0343; RV32I-NEXT: #APP344; RV32I-NEXT: addi a0, t2, 0345; RV32I-NEXT: #NO_APP346; RV32I-NEXT: ret347;348; RV64I-LABEL: explicit_register_t2:349; RV64I: # %bb.0:350; RV64I-NEXT: mv t2, a0351; RV64I-NEXT: #APP352; RV64I-NEXT: addi a0, t2, 0353; RV64I-NEXT: #NO_APP354; RV64I-NEXT: ret355 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t2}"(i32 %a)356 ret i32 %1357}358 359; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved.360define i32 @explicit_register_x8(i32 %a) nounwind {361; RV32I-LABEL: explicit_register_x8:362; RV32I: # %bb.0:363; RV32I-NEXT: addi sp, sp, -16364; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill365; RV32I-NEXT: mv s0, a0366; RV32I-NEXT: #APP367; RV32I-NEXT: addi a0, s0, 0368; RV32I-NEXT: #NO_APP369; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload370; RV32I-NEXT: addi sp, sp, 16371; RV32I-NEXT: ret372;373; RV64I-LABEL: explicit_register_x8:374; RV64I: # %bb.0:375; RV64I-NEXT: addi sp, sp, -16376; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill377; RV64I-NEXT: mv s0, a0378; RV64I-NEXT: #APP379; RV64I-NEXT: addi a0, s0, 0380; RV64I-NEXT: #NO_APP381; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload382; RV64I-NEXT: addi sp, sp, 16383; RV64I-NEXT: ret384 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a)385 ret i32 %1386}387 388; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved.389define i32 @explicit_register_s0(i32 %a) nounwind {390; RV32I-LABEL: explicit_register_s0:391; RV32I: # %bb.0:392; RV32I-NEXT: addi sp, sp, -16393; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill394; RV32I-NEXT: mv s0, a0395; RV32I-NEXT: #APP396; RV32I-NEXT: addi a0, s0, 0397; RV32I-NEXT: #NO_APP398; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload399; RV32I-NEXT: addi sp, sp, 16400; RV32I-NEXT: ret401;402; RV64I-LABEL: explicit_register_s0:403; RV64I: # %bb.0:404; RV64I-NEXT: addi sp, sp, -16405; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill406; RV64I-NEXT: mv s0, a0407; RV64I-NEXT: #APP408; RV64I-NEXT: addi a0, s0, 0409; RV64I-NEXT: #NO_APP410; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload411; RV64I-NEXT: addi sp, sp, 16412; RV64I-NEXT: ret413 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a)414 ret i32 %1415}416 417; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved.418define i32 @explicit_register_fp(i32 %a) nounwind {419; RV32I-LABEL: explicit_register_fp:420; RV32I: # %bb.0:421; RV32I-NEXT: addi sp, sp, -16422; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill423; RV32I-NEXT: mv s0, a0424; RV32I-NEXT: #APP425; RV32I-NEXT: addi a0, s0, 0426; RV32I-NEXT: #NO_APP427; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload428; RV32I-NEXT: addi sp, sp, 16429; RV32I-NEXT: ret430;431; RV64I-LABEL: explicit_register_fp:432; RV64I: # %bb.0:433; RV64I-NEXT: addi sp, sp, -16434; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill435; RV64I-NEXT: mv s0, a0436; RV64I-NEXT: #APP437; RV64I-NEXT: addi a0, s0, 0438; RV64I-NEXT: #NO_APP439; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload440; RV64I-NEXT: addi sp, sp, 16441; RV64I-NEXT: ret442 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a)443 ret i32 %1444}445 446; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved.447define i32 @explicit_register_x9(i32 %a) nounwind {448; RV32I-LABEL: explicit_register_x9:449; RV32I: # %bb.0:450; RV32I-NEXT: addi sp, sp, -16451; RV32I-NEXT: sw s1, 12(sp) # 4-byte Folded Spill452; RV32I-NEXT: mv s1, a0453; RV32I-NEXT: #APP454; RV32I-NEXT: addi a0, s1, 0455; RV32I-NEXT: #NO_APP456; RV32I-NEXT: lw s1, 12(sp) # 4-byte Folded Reload457; RV32I-NEXT: addi sp, sp, 16458; RV32I-NEXT: ret459;460; RV64I-LABEL: explicit_register_x9:461; RV64I: # %bb.0:462; RV64I-NEXT: addi sp, sp, -16463; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill464; RV64I-NEXT: mv s1, a0465; RV64I-NEXT: #APP466; RV64I-NEXT: addi a0, s1, 0467; RV64I-NEXT: #NO_APP468; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload469; RV64I-NEXT: addi sp, sp, 16470; RV64I-NEXT: ret471 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a)472 ret i32 %1473}474 475; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved.476define i32 @explicit_register_s1(i32 %a) nounwind {477; RV32I-LABEL: explicit_register_s1:478; RV32I: # %bb.0:479; RV32I-NEXT: addi sp, sp, -16480; RV32I-NEXT: sw s1, 12(sp) # 4-byte Folded Spill481; RV32I-NEXT: mv s1, a0482; RV32I-NEXT: #APP483; RV32I-NEXT: addi a0, s1, 0484; RV32I-NEXT: #NO_APP485; RV32I-NEXT: lw s1, 12(sp) # 4-byte Folded Reload486; RV32I-NEXT: addi sp, sp, 16487; RV32I-NEXT: ret488;489; RV64I-LABEL: explicit_register_s1:490; RV64I: # %bb.0:491; RV64I-NEXT: addi sp, sp, -16492; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill493; RV64I-NEXT: mv s1, a0494; RV64I-NEXT: #APP495; RV64I-NEXT: addi a0, s1, 0496; RV64I-NEXT: #NO_APP497; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload498; RV64I-NEXT: addi sp, sp, 16499; RV64I-NEXT: ret500 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a)501 ret i32 %1502}503 504define i32 @explicit_register_x10(i32 %a) nounwind {505; RV32I-LABEL: explicit_register_x10:506; RV32I: # %bb.0:507; RV32I-NEXT: #APP508; RV32I-NEXT: addi a0, a0, 0509; RV32I-NEXT: #NO_APP510; RV32I-NEXT: ret511;512; RV64I-LABEL: explicit_register_x10:513; RV64I: # %bb.0:514; RV64I-NEXT: #APP515; RV64I-NEXT: addi a0, a0, 0516; RV64I-NEXT: #NO_APP517; RV64I-NEXT: ret518 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x10}"(i32 %a)519 ret i32 %1520}521 522define i32 @explicit_register_a0(i32 %a) nounwind {523; RV32I-LABEL: explicit_register_a0:524; RV32I: # %bb.0:525; RV32I-NEXT: #APP526; RV32I-NEXT: addi a0, a0, 0527; RV32I-NEXT: #NO_APP528; RV32I-NEXT: ret529;530; RV64I-LABEL: explicit_register_a0:531; RV64I: # %bb.0:532; RV64I-NEXT: #APP533; RV64I-NEXT: addi a0, a0, 0534; RV64I-NEXT: #NO_APP535; RV64I-NEXT: ret536 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a0}"(i32 %a)537 ret i32 %1538}539 540define i32 @explicit_register_x11(i32 %a) nounwind {541; RV32I-LABEL: explicit_register_x11:542; RV32I: # %bb.0:543; RV32I-NEXT: mv a1, a0544; RV32I-NEXT: #APP545; RV32I-NEXT: addi a0, a1, 0546; RV32I-NEXT: #NO_APP547; RV32I-NEXT: ret548;549; RV64I-LABEL: explicit_register_x11:550; RV64I: # %bb.0:551; RV64I-NEXT: mv a1, a0552; RV64I-NEXT: #APP553; RV64I-NEXT: addi a0, a1, 0554; RV64I-NEXT: #NO_APP555; RV64I-NEXT: ret556 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x11}"(i32 %a)557 ret i32 %1558}559 560define i32 @explicit_register_a1(i32 %a) nounwind {561; RV32I-LABEL: explicit_register_a1:562; RV32I: # %bb.0:563; RV32I-NEXT: mv a1, a0564; RV32I-NEXT: #APP565; RV32I-NEXT: addi a0, a1, 0566; RV32I-NEXT: #NO_APP567; RV32I-NEXT: ret568;569; RV64I-LABEL: explicit_register_a1:570; RV64I: # %bb.0:571; RV64I-NEXT: mv a1, a0572; RV64I-NEXT: #APP573; RV64I-NEXT: addi a0, a1, 0574; RV64I-NEXT: #NO_APP575; RV64I-NEXT: ret576 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a1}"(i32 %a)577 ret i32 %1578}579 580define i32 @explicit_register_x12(i32 %a) nounwind {581; RV32I-LABEL: explicit_register_x12:582; RV32I: # %bb.0:583; RV32I-NEXT: mv a2, a0584; RV32I-NEXT: #APP585; RV32I-NEXT: addi a0, a2, 0586; RV32I-NEXT: #NO_APP587; RV32I-NEXT: ret588;589; RV64I-LABEL: explicit_register_x12:590; RV64I: # %bb.0:591; RV64I-NEXT: mv a2, a0592; RV64I-NEXT: #APP593; RV64I-NEXT: addi a0, a2, 0594; RV64I-NEXT: #NO_APP595; RV64I-NEXT: ret596 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x12}"(i32 %a)597 ret i32 %1598}599 600define i32 @explicit_register_a2(i32 %a) nounwind {601; RV32I-LABEL: explicit_register_a2:602; RV32I: # %bb.0:603; RV32I-NEXT: mv a2, a0604; RV32I-NEXT: #APP605; RV32I-NEXT: addi a0, a2, 0606; RV32I-NEXT: #NO_APP607; RV32I-NEXT: ret608;609; RV64I-LABEL: explicit_register_a2:610; RV64I: # %bb.0:611; RV64I-NEXT: mv a2, a0612; RV64I-NEXT: #APP613; RV64I-NEXT: addi a0, a2, 0614; RV64I-NEXT: #NO_APP615; RV64I-NEXT: ret616 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a2}"(i32 %a)617 ret i32 %1618}619 620define i32 @explicit_register_x13(i32 %a) nounwind {621; RV32I-LABEL: explicit_register_x13:622; RV32I: # %bb.0:623; RV32I-NEXT: mv a3, a0624; RV32I-NEXT: #APP625; RV32I-NEXT: addi a0, a3, 0626; RV32I-NEXT: #NO_APP627; RV32I-NEXT: ret628;629; RV64I-LABEL: explicit_register_x13:630; RV64I: # %bb.0:631; RV64I-NEXT: mv a3, a0632; RV64I-NEXT: #APP633; RV64I-NEXT: addi a0, a3, 0634; RV64I-NEXT: #NO_APP635; RV64I-NEXT: ret636 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x13}"(i32 %a)637 ret i32 %1638}639 640define i32 @explicit_register_a3(i32 %a) nounwind {641; RV32I-LABEL: explicit_register_a3:642; RV32I: # %bb.0:643; RV32I-NEXT: mv a3, a0644; RV32I-NEXT: #APP645; RV32I-NEXT: addi a0, a3, 0646; RV32I-NEXT: #NO_APP647; RV32I-NEXT: ret648;649; RV64I-LABEL: explicit_register_a3:650; RV64I: # %bb.0:651; RV64I-NEXT: mv a3, a0652; RV64I-NEXT: #APP653; RV64I-NEXT: addi a0, a3, 0654; RV64I-NEXT: #NO_APP655; RV64I-NEXT: ret656 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a3}"(i32 %a)657 ret i32 %1658}659 660define i32 @explicit_register_x14(i32 %a) nounwind {661; RV32I-LABEL: explicit_register_x14:662; RV32I: # %bb.0:663; RV32I-NEXT: mv a4, a0664; RV32I-NEXT: #APP665; RV32I-NEXT: addi a0, a4, 0666; RV32I-NEXT: #NO_APP667; RV32I-NEXT: ret668;669; RV64I-LABEL: explicit_register_x14:670; RV64I: # %bb.0:671; RV64I-NEXT: mv a4, a0672; RV64I-NEXT: #APP673; RV64I-NEXT: addi a0, a4, 0674; RV64I-NEXT: #NO_APP675; RV64I-NEXT: ret676 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x14}"(i32 %a)677 ret i32 %1678}679 680define i32 @explicit_register_a4(i32 %a) nounwind {681; RV32I-LABEL: explicit_register_a4:682; RV32I: # %bb.0:683; RV32I-NEXT: mv a4, a0684; RV32I-NEXT: #APP685; RV32I-NEXT: addi a0, a4, 0686; RV32I-NEXT: #NO_APP687; RV32I-NEXT: ret688;689; RV64I-LABEL: explicit_register_a4:690; RV64I: # %bb.0:691; RV64I-NEXT: mv a4, a0692; RV64I-NEXT: #APP693; RV64I-NEXT: addi a0, a4, 0694; RV64I-NEXT: #NO_APP695; RV64I-NEXT: ret696 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a4}"(i32 %a)697 ret i32 %1698}699 700define i32 @explicit_register_x15(i32 %a) nounwind {701; RV32I-LABEL: explicit_register_x15:702; RV32I: # %bb.0:703; RV32I-NEXT: mv a5, a0704; RV32I-NEXT: #APP705; RV32I-NEXT: addi a0, a5, 0706; RV32I-NEXT: #NO_APP707; RV32I-NEXT: ret708;709; RV64I-LABEL: explicit_register_x15:710; RV64I: # %bb.0:711; RV64I-NEXT: mv a5, a0712; RV64I-NEXT: #APP713; RV64I-NEXT: addi a0, a5, 0714; RV64I-NEXT: #NO_APP715; RV64I-NEXT: ret716 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x15}"(i32 %a)717 ret i32 %1718}719 720define i32 @explicit_register_a5(i32 %a) nounwind {721; RV32I-LABEL: explicit_register_a5:722; RV32I: # %bb.0:723; RV32I-NEXT: mv a5, a0724; RV32I-NEXT: #APP725; RV32I-NEXT: addi a0, a5, 0726; RV32I-NEXT: #NO_APP727; RV32I-NEXT: ret728;729; RV64I-LABEL: explicit_register_a5:730; RV64I: # %bb.0:731; RV64I-NEXT: mv a5, a0732; RV64I-NEXT: #APP733; RV64I-NEXT: addi a0, a5, 0734; RV64I-NEXT: #NO_APP735; RV64I-NEXT: ret736 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a5}"(i32 %a)737 ret i32 %1738}739 740define i32 @explicit_register_x16(i32 %a) nounwind {741; RV32I-LABEL: explicit_register_x16:742; RV32I: # %bb.0:743; RV32I-NEXT: mv a6, a0744; RV32I-NEXT: #APP745; RV32I-NEXT: addi a0, a6, 0746; RV32I-NEXT: #NO_APP747; RV32I-NEXT: ret748;749; RV64I-LABEL: explicit_register_x16:750; RV64I: # %bb.0:751; RV64I-NEXT: mv a6, a0752; RV64I-NEXT: #APP753; RV64I-NEXT: addi a0, a6, 0754; RV64I-NEXT: #NO_APP755; RV64I-NEXT: ret756 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x16}"(i32 %a)757 ret i32 %1758}759 760define i32 @explicit_register_a6(i32 %a) nounwind {761; RV32I-LABEL: explicit_register_a6:762; RV32I: # %bb.0:763; RV32I-NEXT: mv a6, a0764; RV32I-NEXT: #APP765; RV32I-NEXT: addi a0, a6, 0766; RV32I-NEXT: #NO_APP767; RV32I-NEXT: ret768;769; RV64I-LABEL: explicit_register_a6:770; RV64I: # %bb.0:771; RV64I-NEXT: mv a6, a0772; RV64I-NEXT: #APP773; RV64I-NEXT: addi a0, a6, 0774; RV64I-NEXT: #NO_APP775; RV64I-NEXT: ret776 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a6}"(i32 %a)777 ret i32 %1778}779 780define i32 @explicit_register_x17(i32 %a) nounwind {781; RV32I-LABEL: explicit_register_x17:782; RV32I: # %bb.0:783; RV32I-NEXT: mv a7, a0784; RV32I-NEXT: #APP785; RV32I-NEXT: addi a0, a7, 0786; RV32I-NEXT: #NO_APP787; RV32I-NEXT: ret788;789; RV64I-LABEL: explicit_register_x17:790; RV64I: # %bb.0:791; RV64I-NEXT: mv a7, a0792; RV64I-NEXT: #APP793; RV64I-NEXT: addi a0, a7, 0794; RV64I-NEXT: #NO_APP795; RV64I-NEXT: ret796 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x17}"(i32 %a)797 ret i32 %1798}799 800define i32 @explicit_register_a7(i32 %a) nounwind {801; RV32I-LABEL: explicit_register_a7:802; RV32I: # %bb.0:803; RV32I-NEXT: mv a7, a0804; RV32I-NEXT: #APP805; RV32I-NEXT: addi a0, a7, 0806; RV32I-NEXT: #NO_APP807; RV32I-NEXT: ret808;809; RV64I-LABEL: explicit_register_a7:810; RV64I: # %bb.0:811; RV64I-NEXT: mv a7, a0812; RV64I-NEXT: #APP813; RV64I-NEXT: addi a0, a7, 0814; RV64I-NEXT: #NO_APP815; RV64I-NEXT: ret816 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a7}"(i32 %a)817 ret i32 %1818}819 820; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved.821define i32 @explicit_register_x18(i32 %a) nounwind {822; RV32I-LABEL: explicit_register_x18:823; RV32I: # %bb.0:824; RV32I-NEXT: addi sp, sp, -16825; RV32I-NEXT: sw s2, 12(sp) # 4-byte Folded Spill826; RV32I-NEXT: mv s2, a0827; RV32I-NEXT: #APP828; RV32I-NEXT: addi a0, s2, 0829; RV32I-NEXT: #NO_APP830; RV32I-NEXT: lw s2, 12(sp) # 4-byte Folded Reload831; RV32I-NEXT: addi sp, sp, 16832; RV32I-NEXT: ret833;834; RV64I-LABEL: explicit_register_x18:835; RV64I: # %bb.0:836; RV64I-NEXT: addi sp, sp, -16837; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill838; RV64I-NEXT: mv s2, a0839; RV64I-NEXT: #APP840; RV64I-NEXT: addi a0, s2, 0841; RV64I-NEXT: #NO_APP842; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload843; RV64I-NEXT: addi sp, sp, 16844; RV64I-NEXT: ret845 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a)846 ret i32 %1847}848 849; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved.850define i32 @explicit_register_s2(i32 %a) nounwind {851; RV32I-LABEL: explicit_register_s2:852; RV32I: # %bb.0:853; RV32I-NEXT: addi sp, sp, -16854; RV32I-NEXT: sw s2, 12(sp) # 4-byte Folded Spill855; RV32I-NEXT: mv s2, a0856; RV32I-NEXT: #APP857; RV32I-NEXT: addi a0, s2, 0858; RV32I-NEXT: #NO_APP859; RV32I-NEXT: lw s2, 12(sp) # 4-byte Folded Reload860; RV32I-NEXT: addi sp, sp, 16861; RV32I-NEXT: ret862;863; RV64I-LABEL: explicit_register_s2:864; RV64I: # %bb.0:865; RV64I-NEXT: addi sp, sp, -16866; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill867; RV64I-NEXT: mv s2, a0868; RV64I-NEXT: #APP869; RV64I-NEXT: addi a0, s2, 0870; RV64I-NEXT: #NO_APP871; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload872; RV64I-NEXT: addi sp, sp, 16873; RV64I-NEXT: ret874 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a)875 ret i32 %1876}877 878; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved.879define i32 @explicit_register_x19(i32 %a) nounwind {880; RV32I-LABEL: explicit_register_x19:881; RV32I: # %bb.0:882; RV32I-NEXT: addi sp, sp, -16883; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill884; RV32I-NEXT: mv s3, a0885; RV32I-NEXT: #APP886; RV32I-NEXT: addi a0, s3, 0887; RV32I-NEXT: #NO_APP888; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload889; RV32I-NEXT: addi sp, sp, 16890; RV32I-NEXT: ret891;892; RV64I-LABEL: explicit_register_x19:893; RV64I: # %bb.0:894; RV64I-NEXT: addi sp, sp, -16895; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill896; RV64I-NEXT: mv s3, a0897; RV64I-NEXT: #APP898; RV64I-NEXT: addi a0, s3, 0899; RV64I-NEXT: #NO_APP900; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload901; RV64I-NEXT: addi sp, sp, 16902; RV64I-NEXT: ret903 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a)904 ret i32 %1905}906 907; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved.908define i32 @explicit_register_s3(i32 %a) nounwind {909; RV32I-LABEL: explicit_register_s3:910; RV32I: # %bb.0:911; RV32I-NEXT: addi sp, sp, -16912; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill913; RV32I-NEXT: mv s3, a0914; RV32I-NEXT: #APP915; RV32I-NEXT: addi a0, s3, 0916; RV32I-NEXT: #NO_APP917; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload918; RV32I-NEXT: addi sp, sp, 16919; RV32I-NEXT: ret920;921; RV64I-LABEL: explicit_register_s3:922; RV64I: # %bb.0:923; RV64I-NEXT: addi sp, sp, -16924; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill925; RV64I-NEXT: mv s3, a0926; RV64I-NEXT: #APP927; RV64I-NEXT: addi a0, s3, 0928; RV64I-NEXT: #NO_APP929; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload930; RV64I-NEXT: addi sp, sp, 16931; RV64I-NEXT: ret932 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a)933 ret i32 %1934}935 936; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved.937define i32 @explicit_register_x20(i32 %a) nounwind {938; RV32I-LABEL: explicit_register_x20:939; RV32I: # %bb.0:940; RV32I-NEXT: addi sp, sp, -16941; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill942; RV32I-NEXT: mv s4, a0943; RV32I-NEXT: #APP944; RV32I-NEXT: addi a0, s4, 0945; RV32I-NEXT: #NO_APP946; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload947; RV32I-NEXT: addi sp, sp, 16948; RV32I-NEXT: ret949;950; RV64I-LABEL: explicit_register_x20:951; RV64I: # %bb.0:952; RV64I-NEXT: addi sp, sp, -16953; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill954; RV64I-NEXT: mv s4, a0955; RV64I-NEXT: #APP956; RV64I-NEXT: addi a0, s4, 0957; RV64I-NEXT: #NO_APP958; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload959; RV64I-NEXT: addi sp, sp, 16960; RV64I-NEXT: ret961 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a)962 ret i32 %1963}964 965; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved.966define i32 @explicit_register_s4(i32 %a) nounwind {967; RV32I-LABEL: explicit_register_s4:968; RV32I: # %bb.0:969; RV32I-NEXT: addi sp, sp, -16970; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill971; RV32I-NEXT: mv s4, a0972; RV32I-NEXT: #APP973; RV32I-NEXT: addi a0, s4, 0974; RV32I-NEXT: #NO_APP975; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload976; RV32I-NEXT: addi sp, sp, 16977; RV32I-NEXT: ret978;979; RV64I-LABEL: explicit_register_s4:980; RV64I: # %bb.0:981; RV64I-NEXT: addi sp, sp, -16982; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill983; RV64I-NEXT: mv s4, a0984; RV64I-NEXT: #APP985; RV64I-NEXT: addi a0, s4, 0986; RV64I-NEXT: #NO_APP987; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload988; RV64I-NEXT: addi sp, sp, 16989; RV64I-NEXT: ret990 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a)991 ret i32 %1992}993 994; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved.995define i32 @explicit_register_x21(i32 %a) nounwind {996; RV32I-LABEL: explicit_register_x21:997; RV32I: # %bb.0:998; RV32I-NEXT: addi sp, sp, -16999; RV32I-NEXT: sw s5, 12(sp) # 4-byte Folded Spill1000; RV32I-NEXT: mv s5, a01001; RV32I-NEXT: #APP1002; RV32I-NEXT: addi a0, s5, 01003; RV32I-NEXT: #NO_APP1004; RV32I-NEXT: lw s5, 12(sp) # 4-byte Folded Reload1005; RV32I-NEXT: addi sp, sp, 161006; RV32I-NEXT: ret1007;1008; RV64I-LABEL: explicit_register_x21:1009; RV64I: # %bb.0:1010; RV64I-NEXT: addi sp, sp, -161011; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill1012; RV64I-NEXT: mv s5, a01013; RV64I-NEXT: #APP1014; RV64I-NEXT: addi a0, s5, 01015; RV64I-NEXT: #NO_APP1016; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload1017; RV64I-NEXT: addi sp, sp, 161018; RV64I-NEXT: ret1019 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a)1020 ret i32 %11021}1022 1023; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved.1024define i32 @explicit_register_s5(i32 %a) nounwind {1025; RV32I-LABEL: explicit_register_s5:1026; RV32I: # %bb.0:1027; RV32I-NEXT: addi sp, sp, -161028; RV32I-NEXT: sw s5, 12(sp) # 4-byte Folded Spill1029; RV32I-NEXT: mv s5, a01030; RV32I-NEXT: #APP1031; RV32I-NEXT: addi a0, s5, 01032; RV32I-NEXT: #NO_APP1033; RV32I-NEXT: lw s5, 12(sp) # 4-byte Folded Reload1034; RV32I-NEXT: addi sp, sp, 161035; RV32I-NEXT: ret1036;1037; RV64I-LABEL: explicit_register_s5:1038; RV64I: # %bb.0:1039; RV64I-NEXT: addi sp, sp, -161040; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill1041; RV64I-NEXT: mv s5, a01042; RV64I-NEXT: #APP1043; RV64I-NEXT: addi a0, s5, 01044; RV64I-NEXT: #NO_APP1045; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload1046; RV64I-NEXT: addi sp, sp, 161047; RV64I-NEXT: ret1048 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a)1049 ret i32 %11050}1051 1052; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved.1053define i32 @explicit_register_x22(i32 %a) nounwind {1054; RV32I-LABEL: explicit_register_x22:1055; RV32I: # %bb.0:1056; RV32I-NEXT: addi sp, sp, -161057; RV32I-NEXT: sw s6, 12(sp) # 4-byte Folded Spill1058; RV32I-NEXT: mv s6, a01059; RV32I-NEXT: #APP1060; RV32I-NEXT: addi a0, s6, 01061; RV32I-NEXT: #NO_APP1062; RV32I-NEXT: lw s6, 12(sp) # 4-byte Folded Reload1063; RV32I-NEXT: addi sp, sp, 161064; RV32I-NEXT: ret1065;1066; RV64I-LABEL: explicit_register_x22:1067; RV64I: # %bb.0:1068; RV64I-NEXT: addi sp, sp, -161069; RV64I-NEXT: sd s6, 8(sp) # 8-byte Folded Spill1070; RV64I-NEXT: mv s6, a01071; RV64I-NEXT: #APP1072; RV64I-NEXT: addi a0, s6, 01073; RV64I-NEXT: #NO_APP1074; RV64I-NEXT: ld s6, 8(sp) # 8-byte Folded Reload1075; RV64I-NEXT: addi sp, sp, 161076; RV64I-NEXT: ret1077 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a)1078 ret i32 %11079}1080 1081; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved.1082define i32 @explicit_register_s6(i32 %a) nounwind {1083; RV32I-LABEL: explicit_register_s6:1084; RV32I: # %bb.0:1085; RV32I-NEXT: addi sp, sp, -161086; RV32I-NEXT: sw s6, 12(sp) # 4-byte Folded Spill1087; RV32I-NEXT: mv s6, a01088; RV32I-NEXT: #APP1089; RV32I-NEXT: addi a0, s6, 01090; RV32I-NEXT: #NO_APP1091; RV32I-NEXT: lw s6, 12(sp) # 4-byte Folded Reload1092; RV32I-NEXT: addi sp, sp, 161093; RV32I-NEXT: ret1094;1095; RV64I-LABEL: explicit_register_s6:1096; RV64I: # %bb.0:1097; RV64I-NEXT: addi sp, sp, -161098; RV64I-NEXT: sd s6, 8(sp) # 8-byte Folded Spill1099; RV64I-NEXT: mv s6, a01100; RV64I-NEXT: #APP1101; RV64I-NEXT: addi a0, s6, 01102; RV64I-NEXT: #NO_APP1103; RV64I-NEXT: ld s6, 8(sp) # 8-byte Folded Reload1104; RV64I-NEXT: addi sp, sp, 161105; RV64I-NEXT: ret1106 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a)1107 ret i32 %11108}1109 1110; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved.1111define i32 @explicit_register_x23(i32 %a) nounwind {1112; RV32I-LABEL: explicit_register_x23:1113; RV32I: # %bb.0:1114; RV32I-NEXT: addi sp, sp, -161115; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill1116; RV32I-NEXT: mv s7, a01117; RV32I-NEXT: #APP1118; RV32I-NEXT: addi a0, s7, 01119; RV32I-NEXT: #NO_APP1120; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload1121; RV32I-NEXT: addi sp, sp, 161122; RV32I-NEXT: ret1123;1124; RV64I-LABEL: explicit_register_x23:1125; RV64I: # %bb.0:1126; RV64I-NEXT: addi sp, sp, -161127; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill1128; RV64I-NEXT: mv s7, a01129; RV64I-NEXT: #APP1130; RV64I-NEXT: addi a0, s7, 01131; RV64I-NEXT: #NO_APP1132; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload1133; RV64I-NEXT: addi sp, sp, 161134; RV64I-NEXT: ret1135 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a)1136 ret i32 %11137}1138 1139; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved.1140define i32 @explicit_register_s7(i32 %a) nounwind {1141; RV32I-LABEL: explicit_register_s7:1142; RV32I: # %bb.0:1143; RV32I-NEXT: addi sp, sp, -161144; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill1145; RV32I-NEXT: mv s7, a01146; RV32I-NEXT: #APP1147; RV32I-NEXT: addi a0, s7, 01148; RV32I-NEXT: #NO_APP1149; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload1150; RV32I-NEXT: addi sp, sp, 161151; RV32I-NEXT: ret1152;1153; RV64I-LABEL: explicit_register_s7:1154; RV64I: # %bb.0:1155; RV64I-NEXT: addi sp, sp, -161156; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill1157; RV64I-NEXT: mv s7, a01158; RV64I-NEXT: #APP1159; RV64I-NEXT: addi a0, s7, 01160; RV64I-NEXT: #NO_APP1161; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload1162; RV64I-NEXT: addi sp, sp, 161163; RV64I-NEXT: ret1164 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a)1165 ret i32 %11166}1167 1168; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved.1169define i32 @explicit_register_x24(i32 %a) nounwind {1170; RV32I-LABEL: explicit_register_x24:1171; RV32I: # %bb.0:1172; RV32I-NEXT: addi sp, sp, -161173; RV32I-NEXT: sw s8, 12(sp) # 4-byte Folded Spill1174; RV32I-NEXT: mv s8, a01175; RV32I-NEXT: #APP1176; RV32I-NEXT: addi a0, s8, 01177; RV32I-NEXT: #NO_APP1178; RV32I-NEXT: lw s8, 12(sp) # 4-byte Folded Reload1179; RV32I-NEXT: addi sp, sp, 161180; RV32I-NEXT: ret1181;1182; RV64I-LABEL: explicit_register_x24:1183; RV64I: # %bb.0:1184; RV64I-NEXT: addi sp, sp, -161185; RV64I-NEXT: sd s8, 8(sp) # 8-byte Folded Spill1186; RV64I-NEXT: mv s8, a01187; RV64I-NEXT: #APP1188; RV64I-NEXT: addi a0, s8, 01189; RV64I-NEXT: #NO_APP1190; RV64I-NEXT: ld s8, 8(sp) # 8-byte Folded Reload1191; RV64I-NEXT: addi sp, sp, 161192; RV64I-NEXT: ret1193 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a)1194 ret i32 %11195}1196 1197; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved.1198define i32 @explicit_register_s8(i32 %a) nounwind {1199; RV32I-LABEL: explicit_register_s8:1200; RV32I: # %bb.0:1201; RV32I-NEXT: addi sp, sp, -161202; RV32I-NEXT: sw s8, 12(sp) # 4-byte Folded Spill1203; RV32I-NEXT: mv s8, a01204; RV32I-NEXT: #APP1205; RV32I-NEXT: addi a0, s8, 01206; RV32I-NEXT: #NO_APP1207; RV32I-NEXT: lw s8, 12(sp) # 4-byte Folded Reload1208; RV32I-NEXT: addi sp, sp, 161209; RV32I-NEXT: ret1210;1211; RV64I-LABEL: explicit_register_s8:1212; RV64I: # %bb.0:1213; RV64I-NEXT: addi sp, sp, -161214; RV64I-NEXT: sd s8, 8(sp) # 8-byte Folded Spill1215; RV64I-NEXT: mv s8, a01216; RV64I-NEXT: #APP1217; RV64I-NEXT: addi a0, s8, 01218; RV64I-NEXT: #NO_APP1219; RV64I-NEXT: ld s8, 8(sp) # 8-byte Folded Reload1220; RV64I-NEXT: addi sp, sp, 161221; RV64I-NEXT: ret1222 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a)1223 ret i32 %11224}1225 1226; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved.1227define i32 @explicit_register_x25(i32 %a) nounwind {1228; RV32I-LABEL: explicit_register_x25:1229; RV32I: # %bb.0:1230; RV32I-NEXT: addi sp, sp, -161231; RV32I-NEXT: sw s9, 12(sp) # 4-byte Folded Spill1232; RV32I-NEXT: mv s9, a01233; RV32I-NEXT: #APP1234; RV32I-NEXT: addi a0, s9, 01235; RV32I-NEXT: #NO_APP1236; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload1237; RV32I-NEXT: addi sp, sp, 161238; RV32I-NEXT: ret1239;1240; RV64I-LABEL: explicit_register_x25:1241; RV64I: # %bb.0:1242; RV64I-NEXT: addi sp, sp, -161243; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill1244; RV64I-NEXT: mv s9, a01245; RV64I-NEXT: #APP1246; RV64I-NEXT: addi a0, s9, 01247; RV64I-NEXT: #NO_APP1248; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload1249; RV64I-NEXT: addi sp, sp, 161250; RV64I-NEXT: ret1251 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a)1252 ret i32 %11253}1254 1255; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved.1256define i32 @explicit_register_s9(i32 %a) nounwind {1257; RV32I-LABEL: explicit_register_s9:1258; RV32I: # %bb.0:1259; RV32I-NEXT: addi sp, sp, -161260; RV32I-NEXT: sw s9, 12(sp) # 4-byte Folded Spill1261; RV32I-NEXT: mv s9, a01262; RV32I-NEXT: #APP1263; RV32I-NEXT: addi a0, s9, 01264; RV32I-NEXT: #NO_APP1265; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload1266; RV32I-NEXT: addi sp, sp, 161267; RV32I-NEXT: ret1268;1269; RV64I-LABEL: explicit_register_s9:1270; RV64I: # %bb.0:1271; RV64I-NEXT: addi sp, sp, -161272; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill1273; RV64I-NEXT: mv s9, a01274; RV64I-NEXT: #APP1275; RV64I-NEXT: addi a0, s9, 01276; RV64I-NEXT: #NO_APP1277; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload1278; RV64I-NEXT: addi sp, sp, 161279; RV64I-NEXT: ret1280 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a)1281 ret i32 %11282}1283 1284; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved.1285define i32 @explicit_register_x26(i32 %a) nounwind {1286; RV32I-LABEL: explicit_register_x26:1287; RV32I: # %bb.0:1288; RV32I-NEXT: addi sp, sp, -161289; RV32I-NEXT: sw s10, 12(sp) # 4-byte Folded Spill1290; RV32I-NEXT: mv s10, a01291; RV32I-NEXT: #APP1292; RV32I-NEXT: addi a0, s10, 01293; RV32I-NEXT: #NO_APP1294; RV32I-NEXT: lw s10, 12(sp) # 4-byte Folded Reload1295; RV32I-NEXT: addi sp, sp, 161296; RV32I-NEXT: ret1297;1298; RV64I-LABEL: explicit_register_x26:1299; RV64I: # %bb.0:1300; RV64I-NEXT: addi sp, sp, -161301; RV64I-NEXT: sd s10, 8(sp) # 8-byte Folded Spill1302; RV64I-NEXT: mv s10, a01303; RV64I-NEXT: #APP1304; RV64I-NEXT: addi a0, s10, 01305; RV64I-NEXT: #NO_APP1306; RV64I-NEXT: ld s10, 8(sp) # 8-byte Folded Reload1307; RV64I-NEXT: addi sp, sp, 161308; RV64I-NEXT: ret1309 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a)1310 ret i32 %11311}1312 1313; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved.1314define i32 @explicit_register_s10(i32 %a) nounwind {1315; RV32I-LABEL: explicit_register_s10:1316; RV32I: # %bb.0:1317; RV32I-NEXT: addi sp, sp, -161318; RV32I-NEXT: sw s10, 12(sp) # 4-byte Folded Spill1319; RV32I-NEXT: mv s10, a01320; RV32I-NEXT: #APP1321; RV32I-NEXT: addi a0, s10, 01322; RV32I-NEXT: #NO_APP1323; RV32I-NEXT: lw s10, 12(sp) # 4-byte Folded Reload1324; RV32I-NEXT: addi sp, sp, 161325; RV32I-NEXT: ret1326;1327; RV64I-LABEL: explicit_register_s10:1328; RV64I: # %bb.0:1329; RV64I-NEXT: addi sp, sp, -161330; RV64I-NEXT: sd s10, 8(sp) # 8-byte Folded Spill1331; RV64I-NEXT: mv s10, a01332; RV64I-NEXT: #APP1333; RV64I-NEXT: addi a0, s10, 01334; RV64I-NEXT: #NO_APP1335; RV64I-NEXT: ld s10, 8(sp) # 8-byte Folded Reload1336; RV64I-NEXT: addi sp, sp, 161337; RV64I-NEXT: ret1338 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a)1339 ret i32 %11340}1341 1342; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved.1343define i32 @explicit_register_x27(i32 %a) nounwind {1344; RV32I-LABEL: explicit_register_x27:1345; RV32I: # %bb.0:1346; RV32I-NEXT: addi sp, sp, -161347; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill1348; RV32I-NEXT: mv s11, a01349; RV32I-NEXT: #APP1350; RV32I-NEXT: addi a0, s11, 01351; RV32I-NEXT: #NO_APP1352; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload1353; RV32I-NEXT: addi sp, sp, 161354; RV32I-NEXT: ret1355;1356; RV64I-LABEL: explicit_register_x27:1357; RV64I: # %bb.0:1358; RV64I-NEXT: addi sp, sp, -161359; RV64I-NEXT: sd s11, 8(sp) # 8-byte Folded Spill1360; RV64I-NEXT: mv s11, a01361; RV64I-NEXT: #APP1362; RV64I-NEXT: addi a0, s11, 01363; RV64I-NEXT: #NO_APP1364; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload1365; RV64I-NEXT: addi sp, sp, 161366; RV64I-NEXT: ret1367 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a)1368 ret i32 %11369}1370 1371; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved.1372define i32 @explicit_register_s11(i32 %a) nounwind {1373; RV32I-LABEL: explicit_register_s11:1374; RV32I: # %bb.0:1375; RV32I-NEXT: addi sp, sp, -161376; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill1377; RV32I-NEXT: mv s11, a01378; RV32I-NEXT: #APP1379; RV32I-NEXT: addi a0, s11, 01380; RV32I-NEXT: #NO_APP1381; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload1382; RV32I-NEXT: addi sp, sp, 161383; RV32I-NEXT: ret1384;1385; RV64I-LABEL: explicit_register_s11:1386; RV64I: # %bb.0:1387; RV64I-NEXT: addi sp, sp, -161388; RV64I-NEXT: sd s11, 8(sp) # 8-byte Folded Spill1389; RV64I-NEXT: mv s11, a01390; RV64I-NEXT: #APP1391; RV64I-NEXT: addi a0, s11, 01392; RV64I-NEXT: #NO_APP1393; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload1394; RV64I-NEXT: addi sp, sp, 161395; RV64I-NEXT: ret1396 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a)1397 ret i32 %11398}1399 1400define i32 @explicit_register_x28(i32 %a) nounwind {1401; RV32I-LABEL: explicit_register_x28:1402; RV32I: # %bb.0:1403; RV32I-NEXT: mv t3, a01404; RV32I-NEXT: #APP1405; RV32I-NEXT: addi a0, t3, 01406; RV32I-NEXT: #NO_APP1407; RV32I-NEXT: ret1408;1409; RV64I-LABEL: explicit_register_x28:1410; RV64I: # %bb.0:1411; RV64I-NEXT: mv t3, a01412; RV64I-NEXT: #APP1413; RV64I-NEXT: addi a0, t3, 01414; RV64I-NEXT: #NO_APP1415; RV64I-NEXT: ret1416 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x28}"(i32 %a)1417 ret i32 %11418}1419 1420define i32 @explicit_register_t3(i32 %a) nounwind {1421; RV32I-LABEL: explicit_register_t3:1422; RV32I: # %bb.0:1423; RV32I-NEXT: mv t3, a01424; RV32I-NEXT: #APP1425; RV32I-NEXT: addi a0, t3, 01426; RV32I-NEXT: #NO_APP1427; RV32I-NEXT: ret1428;1429; RV64I-LABEL: explicit_register_t3:1430; RV64I: # %bb.0:1431; RV64I-NEXT: mv t3, a01432; RV64I-NEXT: #APP1433; RV64I-NEXT: addi a0, t3, 01434; RV64I-NEXT: #NO_APP1435; RV64I-NEXT: ret1436 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t3}"(i32 %a)1437 ret i32 %11438}1439 1440define i32 @explicit_register_x29(i32 %a) nounwind {1441; RV32I-LABEL: explicit_register_x29:1442; RV32I: # %bb.0:1443; RV32I-NEXT: mv t4, a01444; RV32I-NEXT: #APP1445; RV32I-NEXT: addi a0, t4, 01446; RV32I-NEXT: #NO_APP1447; RV32I-NEXT: ret1448;1449; RV64I-LABEL: explicit_register_x29:1450; RV64I: # %bb.0:1451; RV64I-NEXT: mv t4, a01452; RV64I-NEXT: #APP1453; RV64I-NEXT: addi a0, t4, 01454; RV64I-NEXT: #NO_APP1455; RV64I-NEXT: ret1456 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x29}"(i32 %a)1457 ret i32 %11458}1459 1460define i32 @explicit_register_t4(i32 %a) nounwind {1461; RV32I-LABEL: explicit_register_t4:1462; RV32I: # %bb.0:1463; RV32I-NEXT: mv t4, a01464; RV32I-NEXT: #APP1465; RV32I-NEXT: addi a0, t4, 01466; RV32I-NEXT: #NO_APP1467; RV32I-NEXT: ret1468;1469; RV64I-LABEL: explicit_register_t4:1470; RV64I: # %bb.0:1471; RV64I-NEXT: mv t4, a01472; RV64I-NEXT: #APP1473; RV64I-NEXT: addi a0, t4, 01474; RV64I-NEXT: #NO_APP1475; RV64I-NEXT: ret1476 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t4}"(i32 %a)1477 ret i32 %11478}1479 1480define i32 @explicit_register_x30(i32 %a) nounwind {1481; RV32I-LABEL: explicit_register_x30:1482; RV32I: # %bb.0:1483; RV32I-NEXT: mv t5, a01484; RV32I-NEXT: #APP1485; RV32I-NEXT: addi a0, t5, 01486; RV32I-NEXT: #NO_APP1487; RV32I-NEXT: ret1488;1489; RV64I-LABEL: explicit_register_x30:1490; RV64I: # %bb.0:1491; RV64I-NEXT: mv t5, a01492; RV64I-NEXT: #APP1493; RV64I-NEXT: addi a0, t5, 01494; RV64I-NEXT: #NO_APP1495; RV64I-NEXT: ret1496 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x30}"(i32 %a)1497 ret i32 %11498}1499 1500define i32 @explicit_register_t5(i32 %a) nounwind {1501; RV32I-LABEL: explicit_register_t5:1502; RV32I: # %bb.0:1503; RV32I-NEXT: mv t5, a01504; RV32I-NEXT: #APP1505; RV32I-NEXT: addi a0, t5, 01506; RV32I-NEXT: #NO_APP1507; RV32I-NEXT: ret1508;1509; RV64I-LABEL: explicit_register_t5:1510; RV64I: # %bb.0:1511; RV64I-NEXT: mv t5, a01512; RV64I-NEXT: #APP1513; RV64I-NEXT: addi a0, t5, 01514; RV64I-NEXT: #NO_APP1515; RV64I-NEXT: ret1516 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t5}"(i32 %a)1517 ret i32 %11518}1519 1520define i32 @explicit_register_x31(i32 %a) nounwind {1521; RV32I-LABEL: explicit_register_x31:1522; RV32I: # %bb.0:1523; RV32I-NEXT: mv t6, a01524; RV32I-NEXT: #APP1525; RV32I-NEXT: addi a0, t6, 01526; RV32I-NEXT: #NO_APP1527; RV32I-NEXT: ret1528;1529; RV64I-LABEL: explicit_register_x31:1530; RV64I: # %bb.0:1531; RV64I-NEXT: mv t6, a01532; RV64I-NEXT: #APP1533; RV64I-NEXT: addi a0, t6, 01534; RV64I-NEXT: #NO_APP1535; RV64I-NEXT: ret1536 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x31}"(i32 %a)1537 ret i32 %11538}1539 1540define i32 @explicit_register_t6(i32 %a) nounwind {1541; RV32I-LABEL: explicit_register_t6:1542; RV32I: # %bb.0:1543; RV32I-NEXT: mv t6, a01544; RV32I-NEXT: #APP1545; RV32I-NEXT: addi a0, t6, 01546; RV32I-NEXT: #NO_APP1547; RV32I-NEXT: ret1548;1549; RV64I-LABEL: explicit_register_t6:1550; RV64I: # %bb.0:1551; RV64I-NEXT: mv t6, a01552; RV64I-NEXT: #APP1553; RV64I-NEXT: addi a0, t6, 01554; RV64I-NEXT: #NO_APP1555; RV64I-NEXT: ret1556 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t6}"(i32 %a)1557 ret i32 %11558}1559