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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \3; RUN: | FileCheck -check-prefix=RV32F %s4; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \5; RUN: | FileCheck -check-prefix=RV64F %s6 7;; `.insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is8;; the raw encoding for `fadd.d`9 10@gd = external global double11 12define double @constraint_f_double(double %a) nounwind {13; RV32F-LABEL: constraint_f_double:14; RV32F: # %bb.0:15; RV32F-NEXT: addi sp, sp, -1616; RV32F-NEXT: sw a0, 8(sp)17; RV32F-NEXT: sw a1, 12(sp)18; RV32F-NEXT: lui a0, %hi(gd)19; RV32F-NEXT: fld fa5, 8(sp)20; RV32F-NEXT: fld fa4, %lo(gd)(a0)21; RV32F-NEXT: #APP22; RV32F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (15 << 15) | (14 << 20)23; RV32F-NEXT: #NO_APP24; RV32F-NEXT: fsd fa5, 8(sp)25; RV32F-NEXT: lw a0, 8(sp)26; RV32F-NEXT: lw a1, 12(sp)27; RV32F-NEXT: addi sp, sp, 1628; RV32F-NEXT: ret29;30; RV64F-LABEL: constraint_f_double:31; RV64F: # %bb.0:32; RV64F-NEXT: lui a1, %hi(gd)33; RV64F-NEXT: fld fa5, %lo(gd)(a1)34; RV64F-NEXT: fmv.d.x fa4, a035; RV64F-NEXT: #APP36; RV64F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (14 << 15) | (15 << 20)37; RV64F-NEXT: #NO_APP38; RV64F-NEXT: fmv.x.d a0, fa539; RV64F-NEXT: ret40 %1 = load double, ptr @gd41 %2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=f,f,f"(double %a, double %1)42 ret double %243}44 45define double @constraint_cf_double(double %a) nounwind {46; RV32F-LABEL: constraint_cf_double:47; RV32F: # %bb.0:48; RV32F-NEXT: addi sp, sp, -1649; RV32F-NEXT: sw a0, 8(sp)50; RV32F-NEXT: sw a1, 12(sp)51; RV32F-NEXT: lui a0, %hi(gd)52; RV32F-NEXT: fld fa5, 8(sp)53; RV32F-NEXT: fld fa4, %lo(gd)(a0)54; RV32F-NEXT: #APP55; RV32F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (15 << 15) | (14 << 20)56; RV32F-NEXT: #NO_APP57; RV32F-NEXT: fsd fa5, 8(sp)58; RV32F-NEXT: lw a0, 8(sp)59; RV32F-NEXT: lw a1, 12(sp)60; RV32F-NEXT: addi sp, sp, 1661; RV32F-NEXT: ret62;63; RV64F-LABEL: constraint_cf_double:64; RV64F: # %bb.0:65; RV64F-NEXT: lui a1, %hi(gd)66; RV64F-NEXT: fld fa5, %lo(gd)(a1)67; RV64F-NEXT: fmv.d.x fa4, a068; RV64F-NEXT: #APP69; RV64F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (14 << 15) | (15 << 20)70; RV64F-NEXT: #NO_APP71; RV64F-NEXT: fmv.x.d a0, fa572; RV64F-NEXT: ret73 %1 = load double, ptr @gd74 %2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=^cf,^cf,^cf"(double %a, double %1)75 ret double %276}77 78define double @constraint_f_double_abi_name(double %a) nounwind {79; RV32F-LABEL: constraint_f_double_abi_name:80; RV32F: # %bb.0:81; RV32F-NEXT: addi sp, sp, -1682; RV32F-NEXT: sw a0, 8(sp)83; RV32F-NEXT: sw a1, 12(sp)84; RV32F-NEXT: lui a0, %hi(gd)85; RV32F-NEXT: fld fa1, 8(sp)86; RV32F-NEXT: fld fs0, %lo(gd)(a0)87; RV32F-NEXT: #APP88; RV32F-NEXT: .insn 0x4, 0x02000053 | (0 << 7) | (11 << 15) | (8 << 20)89; RV32F-NEXT: #NO_APP90; RV32F-NEXT: fsd ft0, 8(sp)91; RV32F-NEXT: lw a0, 8(sp)92; RV32F-NEXT: lw a1, 12(sp)93; RV32F-NEXT: addi sp, sp, 1694; RV32F-NEXT: ret95;96; RV64F-LABEL: constraint_f_double_abi_name:97; RV64F: # %bb.0:98; RV64F-NEXT: lui a1, %hi(gd)99; RV64F-NEXT: fld fs0, %lo(gd)(a1)100; RV64F-NEXT: fmv.d.x fa1, a0101; RV64F-NEXT: #APP102; RV64F-NEXT: .insn 0x4, 0x02000053 | (0 << 7) | (11 << 15) | (8 << 20)103; RV64F-NEXT: #NO_APP104; RV64F-NEXT: fmv.x.d a0, ft0105; RV64F-NEXT: ret106 %1 = load double, ptr @gd107 %2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "={ft0},{fa1},{fs0}"(double %a, double %1)108 ret double %2109}110