1510 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32IF %s4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64IF %s6 7; These test that we can use both the architectural names (x*) and the ABI names8; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each9; case, the named register should be used for the source register of the `addi`.10; It is very likely that `a0` will be chosen as the designation register, but11; this is left to the compiler to choose.12;13; The inline assembly will, by default, contain the ABI names for the registers.14;15; Parenthesised registers in comments are the other aliases for this register.16 17 18define i32 @explicit_register_f0(float %a) nounwind {19; RV32IF-LABEL: explicit_register_f0:20; RV32IF: # %bb.0:21; RV32IF-NEXT: fmv.s ft0, fa022; RV32IF-NEXT: #APP23; RV32IF-NEXT: fcvt.w.s a0, ft024; RV32IF-NEXT: #NO_APP25; RV32IF-NEXT: ret26;27; RV64IF-LABEL: explicit_register_f0:28; RV64IF: # %bb.0:29; RV64IF-NEXT: fmv.s ft0, fa030; RV64IF-NEXT: #APP31; RV64IF-NEXT: fcvt.w.s a0, ft032; RV64IF-NEXT: #NO_APP33; RV64IF-NEXT: ret34 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f0}"(float %a)35 ret i32 %136}37 38define i32 @explicit_register_ft0(float %a) nounwind {39; RV32IF-LABEL: explicit_register_ft0:40; RV32IF: # %bb.0:41; RV32IF-NEXT: fmv.s ft0, fa042; RV32IF-NEXT: #APP43; RV32IF-NEXT: fcvt.w.s a0, ft044; RV32IF-NEXT: #NO_APP45; RV32IF-NEXT: ret46;47; RV64IF-LABEL: explicit_register_ft0:48; RV64IF: # %bb.0:49; RV64IF-NEXT: fmv.s ft0, fa050; RV64IF-NEXT: #APP51; RV64IF-NEXT: fcvt.w.s a0, ft052; RV64IF-NEXT: #NO_APP53; RV64IF-NEXT: ret54 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft0}"(float %a)55 ret i32 %156}57 58define i32 @explicit_register_f1(float %a) nounwind {59; RV32IF-LABEL: explicit_register_f1:60; RV32IF: # %bb.0:61; RV32IF-NEXT: fmv.s ft1, fa062; RV32IF-NEXT: #APP63; RV32IF-NEXT: fcvt.w.s a0, ft164; RV32IF-NEXT: #NO_APP65; RV32IF-NEXT: ret66;67; RV64IF-LABEL: explicit_register_f1:68; RV64IF: # %bb.0:69; RV64IF-NEXT: fmv.s ft1, fa070; RV64IF-NEXT: #APP71; RV64IF-NEXT: fcvt.w.s a0, ft172; RV64IF-NEXT: #NO_APP73; RV64IF-NEXT: ret74 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f1}"(float %a)75 ret i32 %176}77 78define i32 @explicit_register_ft1(float %a) nounwind {79; RV32IF-LABEL: explicit_register_ft1:80; RV32IF: # %bb.0:81; RV32IF-NEXT: fmv.s ft1, fa082; RV32IF-NEXT: #APP83; RV32IF-NEXT: fcvt.w.s a0, ft184; RV32IF-NEXT: #NO_APP85; RV32IF-NEXT: ret86;87; RV64IF-LABEL: explicit_register_ft1:88; RV64IF: # %bb.0:89; RV64IF-NEXT: fmv.s ft1, fa090; RV64IF-NEXT: #APP91; RV64IF-NEXT: fcvt.w.s a0, ft192; RV64IF-NEXT: #NO_APP93; RV64IF-NEXT: ret94 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft1}"(float %a)95 ret i32 %196}97 98define i32 @explicit_register_f2(float %a) nounwind {99; RV32IF-LABEL: explicit_register_f2:100; RV32IF: # %bb.0:101; RV32IF-NEXT: fmv.s ft2, fa0102; RV32IF-NEXT: #APP103; RV32IF-NEXT: fcvt.w.s a0, ft2104; RV32IF-NEXT: #NO_APP105; RV32IF-NEXT: ret106;107; RV64IF-LABEL: explicit_register_f2:108; RV64IF: # %bb.0:109; RV64IF-NEXT: fmv.s ft2, fa0110; RV64IF-NEXT: #APP111; RV64IF-NEXT: fcvt.w.s a0, ft2112; RV64IF-NEXT: #NO_APP113; RV64IF-NEXT: ret114 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f2}"(float %a)115 ret i32 %1116}117 118define i32 @explicit_register_ft2(float %a) nounwind {119; RV32IF-LABEL: explicit_register_ft2:120; RV32IF: # %bb.0:121; RV32IF-NEXT: fmv.s ft2, fa0122; RV32IF-NEXT: #APP123; RV32IF-NEXT: fcvt.w.s a0, ft2124; RV32IF-NEXT: #NO_APP125; RV32IF-NEXT: ret126;127; RV64IF-LABEL: explicit_register_ft2:128; RV64IF: # %bb.0:129; RV64IF-NEXT: fmv.s ft2, fa0130; RV64IF-NEXT: #APP131; RV64IF-NEXT: fcvt.w.s a0, ft2132; RV64IF-NEXT: #NO_APP133; RV64IF-NEXT: ret134 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft2}"(float %a)135 ret i32 %1136}137 138define i32 @explicit_register_f3(float %a) nounwind {139; RV32IF-LABEL: explicit_register_f3:140; RV32IF: # %bb.0:141; RV32IF-NEXT: fmv.s ft3, fa0142; RV32IF-NEXT: #APP143; RV32IF-NEXT: fcvt.w.s a0, ft3144; RV32IF-NEXT: #NO_APP145; RV32IF-NEXT: ret146;147; RV64IF-LABEL: explicit_register_f3:148; RV64IF: # %bb.0:149; RV64IF-NEXT: fmv.s ft3, fa0150; RV64IF-NEXT: #APP151; RV64IF-NEXT: fcvt.w.s a0, ft3152; RV64IF-NEXT: #NO_APP153; RV64IF-NEXT: ret154 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f3}"(float %a)155 ret i32 %1156}157 158define i32 @explicit_register_ft3(float %a) nounwind {159; RV32IF-LABEL: explicit_register_ft3:160; RV32IF: # %bb.0:161; RV32IF-NEXT: fmv.s ft3, fa0162; RV32IF-NEXT: #APP163; RV32IF-NEXT: fcvt.w.s a0, ft3164; RV32IF-NEXT: #NO_APP165; RV32IF-NEXT: ret166;167; RV64IF-LABEL: explicit_register_ft3:168; RV64IF: # %bb.0:169; RV64IF-NEXT: fmv.s ft3, fa0170; RV64IF-NEXT: #APP171; RV64IF-NEXT: fcvt.w.s a0, ft3172; RV64IF-NEXT: #NO_APP173; RV64IF-NEXT: ret174 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft3}"(float %a)175 ret i32 %1176}177 178define i32 @explicit_register_f4(float %a) nounwind {179; RV32IF-LABEL: explicit_register_f4:180; RV32IF: # %bb.0:181; RV32IF-NEXT: fmv.s ft4, fa0182; RV32IF-NEXT: #APP183; RV32IF-NEXT: fcvt.w.s a0, ft4184; RV32IF-NEXT: #NO_APP185; RV32IF-NEXT: ret186;187; RV64IF-LABEL: explicit_register_f4:188; RV64IF: # %bb.0:189; RV64IF-NEXT: fmv.s ft4, fa0190; RV64IF-NEXT: #APP191; RV64IF-NEXT: fcvt.w.s a0, ft4192; RV64IF-NEXT: #NO_APP193; RV64IF-NEXT: ret194 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f4}"(float %a)195 ret i32 %1196}197 198define i32 @explicit_register_ft4(float %a) nounwind {199; RV32IF-LABEL: explicit_register_ft4:200; RV32IF: # %bb.0:201; RV32IF-NEXT: fmv.s ft4, fa0202; RV32IF-NEXT: #APP203; RV32IF-NEXT: fcvt.w.s a0, ft4204; RV32IF-NEXT: #NO_APP205; RV32IF-NEXT: ret206;207; RV64IF-LABEL: explicit_register_ft4:208; RV64IF: # %bb.0:209; RV64IF-NEXT: fmv.s ft4, fa0210; RV64IF-NEXT: #APP211; RV64IF-NEXT: fcvt.w.s a0, ft4212; RV64IF-NEXT: #NO_APP213; RV64IF-NEXT: ret214 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft4}"(float %a)215 ret i32 %1216}217 218define i32 @explicit_register_f5(float %a) nounwind {219; RV32IF-LABEL: explicit_register_f5:220; RV32IF: # %bb.0:221; RV32IF-NEXT: fmv.s ft5, fa0222; RV32IF-NEXT: #APP223; RV32IF-NEXT: fcvt.w.s a0, ft5224; RV32IF-NEXT: #NO_APP225; RV32IF-NEXT: ret226;227; RV64IF-LABEL: explicit_register_f5:228; RV64IF: # %bb.0:229; RV64IF-NEXT: fmv.s ft5, fa0230; RV64IF-NEXT: #APP231; RV64IF-NEXT: fcvt.w.s a0, ft5232; RV64IF-NEXT: #NO_APP233; RV64IF-NEXT: ret234 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f5}"(float %a)235 ret i32 %1236}237 238define i32 @explicit_register_ft5(float %a) nounwind {239; RV32IF-LABEL: explicit_register_ft5:240; RV32IF: # %bb.0:241; RV32IF-NEXT: fmv.s ft5, fa0242; RV32IF-NEXT: #APP243; RV32IF-NEXT: fcvt.w.s a0, ft5244; RV32IF-NEXT: #NO_APP245; RV32IF-NEXT: ret246;247; RV64IF-LABEL: explicit_register_ft5:248; RV64IF: # %bb.0:249; RV64IF-NEXT: fmv.s ft5, fa0250; RV64IF-NEXT: #APP251; RV64IF-NEXT: fcvt.w.s a0, ft5252; RV64IF-NEXT: #NO_APP253; RV64IF-NEXT: ret254 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft5}"(float %a)255 ret i32 %1256}257 258define i32 @explicit_register_f6(float %a) nounwind {259; RV32IF-LABEL: explicit_register_f6:260; RV32IF: # %bb.0:261; RV32IF-NEXT: fmv.s ft6, fa0262; RV32IF-NEXT: #APP263; RV32IF-NEXT: fcvt.w.s a0, ft6264; RV32IF-NEXT: #NO_APP265; RV32IF-NEXT: ret266;267; RV64IF-LABEL: explicit_register_f6:268; RV64IF: # %bb.0:269; RV64IF-NEXT: fmv.s ft6, fa0270; RV64IF-NEXT: #APP271; RV64IF-NEXT: fcvt.w.s a0, ft6272; RV64IF-NEXT: #NO_APP273; RV64IF-NEXT: ret274 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f6}"(float %a)275 ret i32 %1276}277 278define i32 @explicit_register_ft6(float %a) nounwind {279; RV32IF-LABEL: explicit_register_ft6:280; RV32IF: # %bb.0:281; RV32IF-NEXT: fmv.s ft6, fa0282; RV32IF-NEXT: #APP283; RV32IF-NEXT: fcvt.w.s a0, ft6284; RV32IF-NEXT: #NO_APP285; RV32IF-NEXT: ret286;287; RV64IF-LABEL: explicit_register_ft6:288; RV64IF: # %bb.0:289; RV64IF-NEXT: fmv.s ft6, fa0290; RV64IF-NEXT: #APP291; RV64IF-NEXT: fcvt.w.s a0, ft6292; RV64IF-NEXT: #NO_APP293; RV64IF-NEXT: ret294 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft6}"(float %a)295 ret i32 %1296}297 298define i32 @explicit_register_f7(float %a) nounwind {299; RV32IF-LABEL: explicit_register_f7:300; RV32IF: # %bb.0:301; RV32IF-NEXT: fmv.s ft7, fa0302; RV32IF-NEXT: #APP303; RV32IF-NEXT: fcvt.w.s a0, ft7304; RV32IF-NEXT: #NO_APP305; RV32IF-NEXT: ret306;307; RV64IF-LABEL: explicit_register_f7:308; RV64IF: # %bb.0:309; RV64IF-NEXT: fmv.s ft7, fa0310; RV64IF-NEXT: #APP311; RV64IF-NEXT: fcvt.w.s a0, ft7312; RV64IF-NEXT: #NO_APP313; RV64IF-NEXT: ret314 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f7}"(float %a)315 ret i32 %1316}317 318define i32 @explicit_register_ft7(float %a) nounwind {319; RV32IF-LABEL: explicit_register_ft7:320; RV32IF: # %bb.0:321; RV32IF-NEXT: fmv.s ft7, fa0322; RV32IF-NEXT: #APP323; RV32IF-NEXT: fcvt.w.s a0, ft7324; RV32IF-NEXT: #NO_APP325; RV32IF-NEXT: ret326;327; RV64IF-LABEL: explicit_register_ft7:328; RV64IF: # %bb.0:329; RV64IF-NEXT: fmv.s ft7, fa0330; RV64IF-NEXT: #APP331; RV64IF-NEXT: fcvt.w.s a0, ft7332; RV64IF-NEXT: #NO_APP333; RV64IF-NEXT: ret334 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft7}"(float %a)335 ret i32 %1336}337 338 339; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved.340define i32 @explicit_register_f8(float %a) nounwind {341; RV32IF-LABEL: explicit_register_f8:342; RV32IF: # %bb.0:343; RV32IF-NEXT: addi sp, sp, -16344; RV32IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill345; RV32IF-NEXT: fmv.s fs0, fa0346; RV32IF-NEXT: #APP347; RV32IF-NEXT: fcvt.w.s a0, fs0348; RV32IF-NEXT: #NO_APP349; RV32IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload350; RV32IF-NEXT: addi sp, sp, 16351; RV32IF-NEXT: ret352;353; RV64IF-LABEL: explicit_register_f8:354; RV64IF: # %bb.0:355; RV64IF-NEXT: addi sp, sp, -16356; RV64IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill357; RV64IF-NEXT: fmv.s fs0, fa0358; RV64IF-NEXT: #APP359; RV64IF-NEXT: fcvt.w.s a0, fs0360; RV64IF-NEXT: #NO_APP361; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload362; RV64IF-NEXT: addi sp, sp, 16363; RV64IF-NEXT: ret364 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f8}"(float %a)365 ret i32 %1366}367 368; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved.369define i32 @explicit_register_fs0(float %a) nounwind {370; RV32IF-LABEL: explicit_register_fs0:371; RV32IF: # %bb.0:372; RV32IF-NEXT: addi sp, sp, -16373; RV32IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill374; RV32IF-NEXT: fmv.s fs0, fa0375; RV32IF-NEXT: #APP376; RV32IF-NEXT: fcvt.w.s a0, fs0377; RV32IF-NEXT: #NO_APP378; RV32IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload379; RV32IF-NEXT: addi sp, sp, 16380; RV32IF-NEXT: ret381;382; RV64IF-LABEL: explicit_register_fs0:383; RV64IF: # %bb.0:384; RV64IF-NEXT: addi sp, sp, -16385; RV64IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill386; RV64IF-NEXT: fmv.s fs0, fa0387; RV64IF-NEXT: #APP388; RV64IF-NEXT: fcvt.w.s a0, fs0389; RV64IF-NEXT: #NO_APP390; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload391; RV64IF-NEXT: addi sp, sp, 16392; RV64IF-NEXT: ret393 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs0}"(float %a)394 ret i32 %1395}396 397; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved.398define i32 @explicit_register_f9(float %a) nounwind {399; RV32IF-LABEL: explicit_register_f9:400; RV32IF: # %bb.0:401; RV32IF-NEXT: addi sp, sp, -16402; RV32IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill403; RV32IF-NEXT: fmv.s fs1, fa0404; RV32IF-NEXT: #APP405; RV32IF-NEXT: fcvt.w.s a0, fs1406; RV32IF-NEXT: #NO_APP407; RV32IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload408; RV32IF-NEXT: addi sp, sp, 16409; RV32IF-NEXT: ret410;411; RV64IF-LABEL: explicit_register_f9:412; RV64IF: # %bb.0:413; RV64IF-NEXT: addi sp, sp, -16414; RV64IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill415; RV64IF-NEXT: fmv.s fs1, fa0416; RV64IF-NEXT: #APP417; RV64IF-NEXT: fcvt.w.s a0, fs1418; RV64IF-NEXT: #NO_APP419; RV64IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload420; RV64IF-NEXT: addi sp, sp, 16421; RV64IF-NEXT: ret422 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f9}"(float %a)423 ret i32 %1424}425 426; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved.427define i32 @explicit_register_fs1(float %a) nounwind {428; RV32IF-LABEL: explicit_register_fs1:429; RV32IF: # %bb.0:430; RV32IF-NEXT: addi sp, sp, -16431; RV32IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill432; RV32IF-NEXT: fmv.s fs1, fa0433; RV32IF-NEXT: #APP434; RV32IF-NEXT: fcvt.w.s a0, fs1435; RV32IF-NEXT: #NO_APP436; RV32IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload437; RV32IF-NEXT: addi sp, sp, 16438; RV32IF-NEXT: ret439;440; RV64IF-LABEL: explicit_register_fs1:441; RV64IF: # %bb.0:442; RV64IF-NEXT: addi sp, sp, -16443; RV64IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill444; RV64IF-NEXT: fmv.s fs1, fa0445; RV64IF-NEXT: #APP446; RV64IF-NEXT: fcvt.w.s a0, fs1447; RV64IF-NEXT: #NO_APP448; RV64IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload449; RV64IF-NEXT: addi sp, sp, 16450; RV64IF-NEXT: ret451 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs1}"(float %a)452 ret i32 %1453}454 455define i32 @explicit_register_f10(float %a) nounwind {456; RV32IF-LABEL: explicit_register_f10:457; RV32IF: # %bb.0:458; RV32IF-NEXT: #APP459; RV32IF-NEXT: fcvt.w.s a0, fa0460; RV32IF-NEXT: #NO_APP461; RV32IF-NEXT: ret462;463; RV64IF-LABEL: explicit_register_f10:464; RV64IF: # %bb.0:465; RV64IF-NEXT: #APP466; RV64IF-NEXT: fcvt.w.s a0, fa0467; RV64IF-NEXT: #NO_APP468; RV64IF-NEXT: ret469 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f10}"(float %a)470 ret i32 %1471}472 473define i32 @explicit_register_fa0(float %a) nounwind {474; RV32IF-LABEL: explicit_register_fa0:475; RV32IF: # %bb.0:476; RV32IF-NEXT: #APP477; RV32IF-NEXT: fcvt.w.s a0, fa0478; RV32IF-NEXT: #NO_APP479; RV32IF-NEXT: ret480;481; RV64IF-LABEL: explicit_register_fa0:482; RV64IF: # %bb.0:483; RV64IF-NEXT: #APP484; RV64IF-NEXT: fcvt.w.s a0, fa0485; RV64IF-NEXT: #NO_APP486; RV64IF-NEXT: ret487 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa0}"(float %a)488 ret i32 %1489}490 491define i32 @explicit_register_f11(float %a) nounwind {492; RV32IF-LABEL: explicit_register_f11:493; RV32IF: # %bb.0:494; RV32IF-NEXT: fmv.s fa1, fa0495; RV32IF-NEXT: #APP496; RV32IF-NEXT: fcvt.w.s a0, fa1497; RV32IF-NEXT: #NO_APP498; RV32IF-NEXT: ret499;500; RV64IF-LABEL: explicit_register_f11:501; RV64IF: # %bb.0:502; RV64IF-NEXT: fmv.s fa1, fa0503; RV64IF-NEXT: #APP504; RV64IF-NEXT: fcvt.w.s a0, fa1505; RV64IF-NEXT: #NO_APP506; RV64IF-NEXT: ret507 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f11}"(float %a)508 ret i32 %1509}510 511define i32 @explicit_register_fa1(float %a) nounwind {512; RV32IF-LABEL: explicit_register_fa1:513; RV32IF: # %bb.0:514; RV32IF-NEXT: fmv.s fa1, fa0515; RV32IF-NEXT: #APP516; RV32IF-NEXT: fcvt.w.s a0, fa1517; RV32IF-NEXT: #NO_APP518; RV32IF-NEXT: ret519;520; RV64IF-LABEL: explicit_register_fa1:521; RV64IF: # %bb.0:522; RV64IF-NEXT: fmv.s fa1, fa0523; RV64IF-NEXT: #APP524; RV64IF-NEXT: fcvt.w.s a0, fa1525; RV64IF-NEXT: #NO_APP526; RV64IF-NEXT: ret527 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa1}"(float %a)528 ret i32 %1529}530 531define i32 @explicit_register_f12(float %a) nounwind {532; RV32IF-LABEL: explicit_register_f12:533; RV32IF: # %bb.0:534; RV32IF-NEXT: fmv.s fa2, fa0535; RV32IF-NEXT: #APP536; RV32IF-NEXT: fcvt.w.s a0, fa2537; RV32IF-NEXT: #NO_APP538; RV32IF-NEXT: ret539;540; RV64IF-LABEL: explicit_register_f12:541; RV64IF: # %bb.0:542; RV64IF-NEXT: fmv.s fa2, fa0543; RV64IF-NEXT: #APP544; RV64IF-NEXT: fcvt.w.s a0, fa2545; RV64IF-NEXT: #NO_APP546; RV64IF-NEXT: ret547 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f12}"(float %a)548 ret i32 %1549}550 551define i32 @explicit_register_fa2(float %a) nounwind {552; RV32IF-LABEL: explicit_register_fa2:553; RV32IF: # %bb.0:554; RV32IF-NEXT: fmv.s fa2, fa0555; RV32IF-NEXT: #APP556; RV32IF-NEXT: fcvt.w.s a0, fa2557; RV32IF-NEXT: #NO_APP558; RV32IF-NEXT: ret559;560; RV64IF-LABEL: explicit_register_fa2:561; RV64IF: # %bb.0:562; RV64IF-NEXT: fmv.s fa2, fa0563; RV64IF-NEXT: #APP564; RV64IF-NEXT: fcvt.w.s a0, fa2565; RV64IF-NEXT: #NO_APP566; RV64IF-NEXT: ret567 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa2}"(float %a)568 ret i32 %1569}570 571define i32 @explicit_register_f13(float %a) nounwind {572; RV32IF-LABEL: explicit_register_f13:573; RV32IF: # %bb.0:574; RV32IF-NEXT: fmv.s fa3, fa0575; RV32IF-NEXT: #APP576; RV32IF-NEXT: fcvt.w.s a0, fa3577; RV32IF-NEXT: #NO_APP578; RV32IF-NEXT: ret579;580; RV64IF-LABEL: explicit_register_f13:581; RV64IF: # %bb.0:582; RV64IF-NEXT: fmv.s fa3, fa0583; RV64IF-NEXT: #APP584; RV64IF-NEXT: fcvt.w.s a0, fa3585; RV64IF-NEXT: #NO_APP586; RV64IF-NEXT: ret587 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f13}"(float %a)588 ret i32 %1589}590 591define i32 @explicit_register_fa3(float %a) nounwind {592; RV32IF-LABEL: explicit_register_fa3:593; RV32IF: # %bb.0:594; RV32IF-NEXT: fmv.s fa3, fa0595; RV32IF-NEXT: #APP596; RV32IF-NEXT: fcvt.w.s a0, fa3597; RV32IF-NEXT: #NO_APP598; RV32IF-NEXT: ret599;600; RV64IF-LABEL: explicit_register_fa3:601; RV64IF: # %bb.0:602; RV64IF-NEXT: fmv.s fa3, fa0603; RV64IF-NEXT: #APP604; RV64IF-NEXT: fcvt.w.s a0, fa3605; RV64IF-NEXT: #NO_APP606; RV64IF-NEXT: ret607 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa3}"(float %a)608 ret i32 %1609}610 611define i32 @explicit_register_f14(float %a) nounwind {612; RV32IF-LABEL: explicit_register_f14:613; RV32IF: # %bb.0:614; RV32IF-NEXT: fmv.s fa4, fa0615; RV32IF-NEXT: #APP616; RV32IF-NEXT: fcvt.w.s a0, fa4617; RV32IF-NEXT: #NO_APP618; RV32IF-NEXT: ret619;620; RV64IF-LABEL: explicit_register_f14:621; RV64IF: # %bb.0:622; RV64IF-NEXT: fmv.s fa4, fa0623; RV64IF-NEXT: #APP624; RV64IF-NEXT: fcvt.w.s a0, fa4625; RV64IF-NEXT: #NO_APP626; RV64IF-NEXT: ret627 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f14}"(float %a)628 ret i32 %1629}630 631define i32 @explicit_register_fa4(float %a) nounwind {632; RV32IF-LABEL: explicit_register_fa4:633; RV32IF: # %bb.0:634; RV32IF-NEXT: fmv.s fa4, fa0635; RV32IF-NEXT: #APP636; RV32IF-NEXT: fcvt.w.s a0, fa4637; RV32IF-NEXT: #NO_APP638; RV32IF-NEXT: ret639;640; RV64IF-LABEL: explicit_register_fa4:641; RV64IF: # %bb.0:642; RV64IF-NEXT: fmv.s fa4, fa0643; RV64IF-NEXT: #APP644; RV64IF-NEXT: fcvt.w.s a0, fa4645; RV64IF-NEXT: #NO_APP646; RV64IF-NEXT: ret647 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa4}"(float %a)648 ret i32 %1649}650 651define i32 @explicit_register_f15(float %a) nounwind {652; RV32IF-LABEL: explicit_register_f15:653; RV32IF: # %bb.0:654; RV32IF-NEXT: fmv.s fa5, fa0655; RV32IF-NEXT: #APP656; RV32IF-NEXT: fcvt.w.s a0, fa5657; RV32IF-NEXT: #NO_APP658; RV32IF-NEXT: ret659;660; RV64IF-LABEL: explicit_register_f15:661; RV64IF: # %bb.0:662; RV64IF-NEXT: fmv.s fa5, fa0663; RV64IF-NEXT: #APP664; RV64IF-NEXT: fcvt.w.s a0, fa5665; RV64IF-NEXT: #NO_APP666; RV64IF-NEXT: ret667 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f15}"(float %a)668 ret i32 %1669}670 671define i32 @explicit_register_fa5(float %a) nounwind {672; RV32IF-LABEL: explicit_register_fa5:673; RV32IF: # %bb.0:674; RV32IF-NEXT: fmv.s fa5, fa0675; RV32IF-NEXT: #APP676; RV32IF-NEXT: fcvt.w.s a0, fa5677; RV32IF-NEXT: #NO_APP678; RV32IF-NEXT: ret679;680; RV64IF-LABEL: explicit_register_fa5:681; RV64IF: # %bb.0:682; RV64IF-NEXT: fmv.s fa5, fa0683; RV64IF-NEXT: #APP684; RV64IF-NEXT: fcvt.w.s a0, fa5685; RV64IF-NEXT: #NO_APP686; RV64IF-NEXT: ret687 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa5}"(float %a)688 ret i32 %1689}690 691define i32 @explicit_register_f16(float %a) nounwind {692; RV32IF-LABEL: explicit_register_f16:693; RV32IF: # %bb.0:694; RV32IF-NEXT: fmv.s fa6, fa0695; RV32IF-NEXT: #APP696; RV32IF-NEXT: fcvt.w.s a0, fa6697; RV32IF-NEXT: #NO_APP698; RV32IF-NEXT: ret699;700; RV64IF-LABEL: explicit_register_f16:701; RV64IF: # %bb.0:702; RV64IF-NEXT: fmv.s fa6, fa0703; RV64IF-NEXT: #APP704; RV64IF-NEXT: fcvt.w.s a0, fa6705; RV64IF-NEXT: #NO_APP706; RV64IF-NEXT: ret707 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f16}"(float %a)708 ret i32 %1709}710 711define i32 @explicit_register_fa6(float %a) nounwind {712; RV32IF-LABEL: explicit_register_fa6:713; RV32IF: # %bb.0:714; RV32IF-NEXT: fmv.s fa6, fa0715; RV32IF-NEXT: #APP716; RV32IF-NEXT: fcvt.w.s a0, fa6717; RV32IF-NEXT: #NO_APP718; RV32IF-NEXT: ret719;720; RV64IF-LABEL: explicit_register_fa6:721; RV64IF: # %bb.0:722; RV64IF-NEXT: fmv.s fa6, fa0723; RV64IF-NEXT: #APP724; RV64IF-NEXT: fcvt.w.s a0, fa6725; RV64IF-NEXT: #NO_APP726; RV64IF-NEXT: ret727 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa6}"(float %a)728 ret i32 %1729}730 731define i32 @explicit_register_f17(float %a) nounwind {732; RV32IF-LABEL: explicit_register_f17:733; RV32IF: # %bb.0:734; RV32IF-NEXT: fmv.s fa7, fa0735; RV32IF-NEXT: #APP736; RV32IF-NEXT: fcvt.w.s a0, fa7737; RV32IF-NEXT: #NO_APP738; RV32IF-NEXT: ret739;740; RV64IF-LABEL: explicit_register_f17:741; RV64IF: # %bb.0:742; RV64IF-NEXT: fmv.s fa7, fa0743; RV64IF-NEXT: #APP744; RV64IF-NEXT: fcvt.w.s a0, fa7745; RV64IF-NEXT: #NO_APP746; RV64IF-NEXT: ret747 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f17}"(float %a)748 ret i32 %1749}750 751define i32 @explicit_register_fa7(float %a) nounwind {752; RV32IF-LABEL: explicit_register_fa7:753; RV32IF: # %bb.0:754; RV32IF-NEXT: fmv.s fa7, fa0755; RV32IF-NEXT: #APP756; RV32IF-NEXT: fcvt.w.s a0, fa7757; RV32IF-NEXT: #NO_APP758; RV32IF-NEXT: ret759;760; RV64IF-LABEL: explicit_register_fa7:761; RV64IF: # %bb.0:762; RV64IF-NEXT: fmv.s fa7, fa0763; RV64IF-NEXT: #APP764; RV64IF-NEXT: fcvt.w.s a0, fa7765; RV64IF-NEXT: #NO_APP766; RV64IF-NEXT: ret767 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa7}"(float %a)768 ret i32 %1769}770 771; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved.772define i32 @explicit_register_f18(float %a) nounwind {773; RV32IF-LABEL: explicit_register_f18:774; RV32IF: # %bb.0:775; RV32IF-NEXT: addi sp, sp, -16776; RV32IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill777; RV32IF-NEXT: fmv.s fs2, fa0778; RV32IF-NEXT: #APP779; RV32IF-NEXT: fcvt.w.s a0, fs2780; RV32IF-NEXT: #NO_APP781; RV32IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload782; RV32IF-NEXT: addi sp, sp, 16783; RV32IF-NEXT: ret784;785; RV64IF-LABEL: explicit_register_f18:786; RV64IF: # %bb.0:787; RV64IF-NEXT: addi sp, sp, -16788; RV64IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill789; RV64IF-NEXT: fmv.s fs2, fa0790; RV64IF-NEXT: #APP791; RV64IF-NEXT: fcvt.w.s a0, fs2792; RV64IF-NEXT: #NO_APP793; RV64IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload794; RV64IF-NEXT: addi sp, sp, 16795; RV64IF-NEXT: ret796 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f18}"(float %a)797 ret i32 %1798}799 800; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved.801define i32 @explicit_register_fs2(float %a) nounwind {802; RV32IF-LABEL: explicit_register_fs2:803; RV32IF: # %bb.0:804; RV32IF-NEXT: addi sp, sp, -16805; RV32IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill806; RV32IF-NEXT: fmv.s fs2, fa0807; RV32IF-NEXT: #APP808; RV32IF-NEXT: fcvt.w.s a0, fs2809; RV32IF-NEXT: #NO_APP810; RV32IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload811; RV32IF-NEXT: addi sp, sp, 16812; RV32IF-NEXT: ret813;814; RV64IF-LABEL: explicit_register_fs2:815; RV64IF: # %bb.0:816; RV64IF-NEXT: addi sp, sp, -16817; RV64IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill818; RV64IF-NEXT: fmv.s fs2, fa0819; RV64IF-NEXT: #APP820; RV64IF-NEXT: fcvt.w.s a0, fs2821; RV64IF-NEXT: #NO_APP822; RV64IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload823; RV64IF-NEXT: addi sp, sp, 16824; RV64IF-NEXT: ret825 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs2}"(float %a)826 ret i32 %1827}828 829; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved.830define i32 @explicit_register_f19(float %a) nounwind {831; RV32IF-LABEL: explicit_register_f19:832; RV32IF: # %bb.0:833; RV32IF-NEXT: addi sp, sp, -16834; RV32IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill835; RV32IF-NEXT: fmv.s fs3, fa0836; RV32IF-NEXT: #APP837; RV32IF-NEXT: fcvt.w.s a0, fs3838; RV32IF-NEXT: #NO_APP839; RV32IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload840; RV32IF-NEXT: addi sp, sp, 16841; RV32IF-NEXT: ret842;843; RV64IF-LABEL: explicit_register_f19:844; RV64IF: # %bb.0:845; RV64IF-NEXT: addi sp, sp, -16846; RV64IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill847; RV64IF-NEXT: fmv.s fs3, fa0848; RV64IF-NEXT: #APP849; RV64IF-NEXT: fcvt.w.s a0, fs3850; RV64IF-NEXT: #NO_APP851; RV64IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload852; RV64IF-NEXT: addi sp, sp, 16853; RV64IF-NEXT: ret854 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f19}"(float %a)855 ret i32 %1856}857 858; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved.859define i32 @explicit_register_fs3(float %a) nounwind {860; RV32IF-LABEL: explicit_register_fs3:861; RV32IF: # %bb.0:862; RV32IF-NEXT: addi sp, sp, -16863; RV32IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill864; RV32IF-NEXT: fmv.s fs3, fa0865; RV32IF-NEXT: #APP866; RV32IF-NEXT: fcvt.w.s a0, fs3867; RV32IF-NEXT: #NO_APP868; RV32IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload869; RV32IF-NEXT: addi sp, sp, 16870; RV32IF-NEXT: ret871;872; RV64IF-LABEL: explicit_register_fs3:873; RV64IF: # %bb.0:874; RV64IF-NEXT: addi sp, sp, -16875; RV64IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill876; RV64IF-NEXT: fmv.s fs3, fa0877; RV64IF-NEXT: #APP878; RV64IF-NEXT: fcvt.w.s a0, fs3879; RV64IF-NEXT: #NO_APP880; RV64IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload881; RV64IF-NEXT: addi sp, sp, 16882; RV64IF-NEXT: ret883 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs3}"(float %a)884 ret i32 %1885}886 887; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved.888define i32 @explicit_register_f20(float %a) nounwind {889; RV32IF-LABEL: explicit_register_f20:890; RV32IF: # %bb.0:891; RV32IF-NEXT: addi sp, sp, -16892; RV32IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill893; RV32IF-NEXT: fmv.s fs4, fa0894; RV32IF-NEXT: #APP895; RV32IF-NEXT: fcvt.w.s a0, fs4896; RV32IF-NEXT: #NO_APP897; RV32IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload898; RV32IF-NEXT: addi sp, sp, 16899; RV32IF-NEXT: ret900;901; RV64IF-LABEL: explicit_register_f20:902; RV64IF: # %bb.0:903; RV64IF-NEXT: addi sp, sp, -16904; RV64IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill905; RV64IF-NEXT: fmv.s fs4, fa0906; RV64IF-NEXT: #APP907; RV64IF-NEXT: fcvt.w.s a0, fs4908; RV64IF-NEXT: #NO_APP909; RV64IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload910; RV64IF-NEXT: addi sp, sp, 16911; RV64IF-NEXT: ret912 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f20}"(float %a)913 ret i32 %1914}915 916; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved.917define i32 @explicit_register_fs4(float %a) nounwind {918; RV32IF-LABEL: explicit_register_fs4:919; RV32IF: # %bb.0:920; RV32IF-NEXT: addi sp, sp, -16921; RV32IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill922; RV32IF-NEXT: fmv.s fs4, fa0923; RV32IF-NEXT: #APP924; RV32IF-NEXT: fcvt.w.s a0, fs4925; RV32IF-NEXT: #NO_APP926; RV32IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload927; RV32IF-NEXT: addi sp, sp, 16928; RV32IF-NEXT: ret929;930; RV64IF-LABEL: explicit_register_fs4:931; RV64IF: # %bb.0:932; RV64IF-NEXT: addi sp, sp, -16933; RV64IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill934; RV64IF-NEXT: fmv.s fs4, fa0935; RV64IF-NEXT: #APP936; RV64IF-NEXT: fcvt.w.s a0, fs4937; RV64IF-NEXT: #NO_APP938; RV64IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload939; RV64IF-NEXT: addi sp, sp, 16940; RV64IF-NEXT: ret941 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs4}"(float %a)942 ret i32 %1943}944 945; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved.946define i32 @explicit_register_f21(float %a) nounwind {947; RV32IF-LABEL: explicit_register_f21:948; RV32IF: # %bb.0:949; RV32IF-NEXT: addi sp, sp, -16950; RV32IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill951; RV32IF-NEXT: fmv.s fs5, fa0952; RV32IF-NEXT: #APP953; RV32IF-NEXT: fcvt.w.s a0, fs5954; RV32IF-NEXT: #NO_APP955; RV32IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload956; RV32IF-NEXT: addi sp, sp, 16957; RV32IF-NEXT: ret958;959; RV64IF-LABEL: explicit_register_f21:960; RV64IF: # %bb.0:961; RV64IF-NEXT: addi sp, sp, -16962; RV64IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill963; RV64IF-NEXT: fmv.s fs5, fa0964; RV64IF-NEXT: #APP965; RV64IF-NEXT: fcvt.w.s a0, fs5966; RV64IF-NEXT: #NO_APP967; RV64IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload968; RV64IF-NEXT: addi sp, sp, 16969; RV64IF-NEXT: ret970 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f21}"(float %a)971 ret i32 %1972}973 974; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved.975define i32 @explicit_register_fs5(float %a) nounwind {976; RV32IF-LABEL: explicit_register_fs5:977; RV32IF: # %bb.0:978; RV32IF-NEXT: addi sp, sp, -16979; RV32IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill980; RV32IF-NEXT: fmv.s fs5, fa0981; RV32IF-NEXT: #APP982; RV32IF-NEXT: fcvt.w.s a0, fs5983; RV32IF-NEXT: #NO_APP984; RV32IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload985; RV32IF-NEXT: addi sp, sp, 16986; RV32IF-NEXT: ret987;988; RV64IF-LABEL: explicit_register_fs5:989; RV64IF: # %bb.0:990; RV64IF-NEXT: addi sp, sp, -16991; RV64IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill992; RV64IF-NEXT: fmv.s fs5, fa0993; RV64IF-NEXT: #APP994; RV64IF-NEXT: fcvt.w.s a0, fs5995; RV64IF-NEXT: #NO_APP996; RV64IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload997; RV64IF-NEXT: addi sp, sp, 16998; RV64IF-NEXT: ret999 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs5}"(float %a)1000 ret i32 %11001}1002 1003; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved.1004define i32 @explicit_register_f22(float %a) nounwind {1005; RV32IF-LABEL: explicit_register_f22:1006; RV32IF: # %bb.0:1007; RV32IF-NEXT: addi sp, sp, -161008; RV32IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill1009; RV32IF-NEXT: fmv.s fs6, fa01010; RV32IF-NEXT: #APP1011; RV32IF-NEXT: fcvt.w.s a0, fs61012; RV32IF-NEXT: #NO_APP1013; RV32IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload1014; RV32IF-NEXT: addi sp, sp, 161015; RV32IF-NEXT: ret1016;1017; RV64IF-LABEL: explicit_register_f22:1018; RV64IF: # %bb.0:1019; RV64IF-NEXT: addi sp, sp, -161020; RV64IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill1021; RV64IF-NEXT: fmv.s fs6, fa01022; RV64IF-NEXT: #APP1023; RV64IF-NEXT: fcvt.w.s a0, fs61024; RV64IF-NEXT: #NO_APP1025; RV64IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload1026; RV64IF-NEXT: addi sp, sp, 161027; RV64IF-NEXT: ret1028 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f22}"(float %a)1029 ret i32 %11030}1031 1032; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved.1033define i32 @explicit_register_fs6(float %a) nounwind {1034; RV32IF-LABEL: explicit_register_fs6:1035; RV32IF: # %bb.0:1036; RV32IF-NEXT: addi sp, sp, -161037; RV32IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill1038; RV32IF-NEXT: fmv.s fs6, fa01039; RV32IF-NEXT: #APP1040; RV32IF-NEXT: fcvt.w.s a0, fs61041; RV32IF-NEXT: #NO_APP1042; RV32IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload1043; RV32IF-NEXT: addi sp, sp, 161044; RV32IF-NEXT: ret1045;1046; RV64IF-LABEL: explicit_register_fs6:1047; RV64IF: # %bb.0:1048; RV64IF-NEXT: addi sp, sp, -161049; RV64IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill1050; RV64IF-NEXT: fmv.s fs6, fa01051; RV64IF-NEXT: #APP1052; RV64IF-NEXT: fcvt.w.s a0, fs61053; RV64IF-NEXT: #NO_APP1054; RV64IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload1055; RV64IF-NEXT: addi sp, sp, 161056; RV64IF-NEXT: ret1057 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs6}"(float %a)1058 ret i32 %11059}1060 1061; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved.1062define i32 @explicit_register_f23(float %a) nounwind {1063; RV32IF-LABEL: explicit_register_f23:1064; RV32IF: # %bb.0:1065; RV32IF-NEXT: addi sp, sp, -161066; RV32IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill1067; RV32IF-NEXT: fmv.s fs7, fa01068; RV32IF-NEXT: #APP1069; RV32IF-NEXT: fcvt.w.s a0, fs71070; RV32IF-NEXT: #NO_APP1071; RV32IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload1072; RV32IF-NEXT: addi sp, sp, 161073; RV32IF-NEXT: ret1074;1075; RV64IF-LABEL: explicit_register_f23:1076; RV64IF: # %bb.0:1077; RV64IF-NEXT: addi sp, sp, -161078; RV64IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill1079; RV64IF-NEXT: fmv.s fs7, fa01080; RV64IF-NEXT: #APP1081; RV64IF-NEXT: fcvt.w.s a0, fs71082; RV64IF-NEXT: #NO_APP1083; RV64IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload1084; RV64IF-NEXT: addi sp, sp, 161085; RV64IF-NEXT: ret1086 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f23}"(float %a)1087 ret i32 %11088}1089 1090; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved.1091define i32 @explicit_register_fs7(float %a) nounwind {1092; RV32IF-LABEL: explicit_register_fs7:1093; RV32IF: # %bb.0:1094; RV32IF-NEXT: addi sp, sp, -161095; RV32IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill1096; RV32IF-NEXT: fmv.s fs7, fa01097; RV32IF-NEXT: #APP1098; RV32IF-NEXT: fcvt.w.s a0, fs71099; RV32IF-NEXT: #NO_APP1100; RV32IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload1101; RV32IF-NEXT: addi sp, sp, 161102; RV32IF-NEXT: ret1103;1104; RV64IF-LABEL: explicit_register_fs7:1105; RV64IF: # %bb.0:1106; RV64IF-NEXT: addi sp, sp, -161107; RV64IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill1108; RV64IF-NEXT: fmv.s fs7, fa01109; RV64IF-NEXT: #APP1110; RV64IF-NEXT: fcvt.w.s a0, fs71111; RV64IF-NEXT: #NO_APP1112; RV64IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload1113; RV64IF-NEXT: addi sp, sp, 161114; RV64IF-NEXT: ret1115 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs7}"(float %a)1116 ret i32 %11117}1118 1119; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved.1120define i32 @explicit_register_f24(float %a) nounwind {1121; RV32IF-LABEL: explicit_register_f24:1122; RV32IF: # %bb.0:1123; RV32IF-NEXT: addi sp, sp, -161124; RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill1125; RV32IF-NEXT: fmv.s fs8, fa01126; RV32IF-NEXT: #APP1127; RV32IF-NEXT: fcvt.w.s a0, fs81128; RV32IF-NEXT: #NO_APP1129; RV32IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload1130; RV32IF-NEXT: addi sp, sp, 161131; RV32IF-NEXT: ret1132;1133; RV64IF-LABEL: explicit_register_f24:1134; RV64IF: # %bb.0:1135; RV64IF-NEXT: addi sp, sp, -161136; RV64IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill1137; RV64IF-NEXT: fmv.s fs8, fa01138; RV64IF-NEXT: #APP1139; RV64IF-NEXT: fcvt.w.s a0, fs81140; RV64IF-NEXT: #NO_APP1141; RV64IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload1142; RV64IF-NEXT: addi sp, sp, 161143; RV64IF-NEXT: ret1144 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f24}"(float %a)1145 ret i32 %11146}1147 1148; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved.1149define i32 @explicit_register_fs8(float %a) nounwind {1150; RV32IF-LABEL: explicit_register_fs8:1151; RV32IF: # %bb.0:1152; RV32IF-NEXT: addi sp, sp, -161153; RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill1154; RV32IF-NEXT: fmv.s fs8, fa01155; RV32IF-NEXT: #APP1156; RV32IF-NEXT: fcvt.w.s a0, fs81157; RV32IF-NEXT: #NO_APP1158; RV32IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload1159; RV32IF-NEXT: addi sp, sp, 161160; RV32IF-NEXT: ret1161;1162; RV64IF-LABEL: explicit_register_fs8:1163; RV64IF: # %bb.0:1164; RV64IF-NEXT: addi sp, sp, -161165; RV64IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill1166; RV64IF-NEXT: fmv.s fs8, fa01167; RV64IF-NEXT: #APP1168; RV64IF-NEXT: fcvt.w.s a0, fs81169; RV64IF-NEXT: #NO_APP1170; RV64IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload1171; RV64IF-NEXT: addi sp, sp, 161172; RV64IF-NEXT: ret1173 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs8}"(float %a)1174 ret i32 %11175}1176 1177; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved.1178define i32 @explicit_register_f25(float %a) nounwind {1179; RV32IF-LABEL: explicit_register_f25:1180; RV32IF: # %bb.0:1181; RV32IF-NEXT: addi sp, sp, -161182; RV32IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill1183; RV32IF-NEXT: fmv.s fs9, fa01184; RV32IF-NEXT: #APP1185; RV32IF-NEXT: fcvt.w.s a0, fs91186; RV32IF-NEXT: #NO_APP1187; RV32IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload1188; RV32IF-NEXT: addi sp, sp, 161189; RV32IF-NEXT: ret1190;1191; RV64IF-LABEL: explicit_register_f25:1192; RV64IF: # %bb.0:1193; RV64IF-NEXT: addi sp, sp, -161194; RV64IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill1195; RV64IF-NEXT: fmv.s fs9, fa01196; RV64IF-NEXT: #APP1197; RV64IF-NEXT: fcvt.w.s a0, fs91198; RV64IF-NEXT: #NO_APP1199; RV64IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload1200; RV64IF-NEXT: addi sp, sp, 161201; RV64IF-NEXT: ret1202 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f25}"(float %a)1203 ret i32 %11204}1205 1206; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved.1207define i32 @explicit_register_fs9(float %a) nounwind {1208; RV32IF-LABEL: explicit_register_fs9:1209; RV32IF: # %bb.0:1210; RV32IF-NEXT: addi sp, sp, -161211; RV32IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill1212; RV32IF-NEXT: fmv.s fs9, fa01213; RV32IF-NEXT: #APP1214; RV32IF-NEXT: fcvt.w.s a0, fs91215; RV32IF-NEXT: #NO_APP1216; RV32IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload1217; RV32IF-NEXT: addi sp, sp, 161218; RV32IF-NEXT: ret1219;1220; RV64IF-LABEL: explicit_register_fs9:1221; RV64IF: # %bb.0:1222; RV64IF-NEXT: addi sp, sp, -161223; RV64IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill1224; RV64IF-NEXT: fmv.s fs9, fa01225; RV64IF-NEXT: #APP1226; RV64IF-NEXT: fcvt.w.s a0, fs91227; RV64IF-NEXT: #NO_APP1228; RV64IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload1229; RV64IF-NEXT: addi sp, sp, 161230; RV64IF-NEXT: ret1231 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs9}"(float %a)1232 ret i32 %11233}1234 1235; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved.1236define i32 @explicit_register_f26(float %a) nounwind {1237; RV32IF-LABEL: explicit_register_f26:1238; RV32IF: # %bb.0:1239; RV32IF-NEXT: addi sp, sp, -161240; RV32IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill1241; RV32IF-NEXT: fmv.s fs10, fa01242; RV32IF-NEXT: #APP1243; RV32IF-NEXT: fcvt.w.s a0, fs101244; RV32IF-NEXT: #NO_APP1245; RV32IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload1246; RV32IF-NEXT: addi sp, sp, 161247; RV32IF-NEXT: ret1248;1249; RV64IF-LABEL: explicit_register_f26:1250; RV64IF: # %bb.0:1251; RV64IF-NEXT: addi sp, sp, -161252; RV64IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill1253; RV64IF-NEXT: fmv.s fs10, fa01254; RV64IF-NEXT: #APP1255; RV64IF-NEXT: fcvt.w.s a0, fs101256; RV64IF-NEXT: #NO_APP1257; RV64IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload1258; RV64IF-NEXT: addi sp, sp, 161259; RV64IF-NEXT: ret1260 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f26}"(float %a)1261 ret i32 %11262}1263 1264; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved.1265define i32 @explicit_register_fs10(float %a) nounwind {1266; RV32IF-LABEL: explicit_register_fs10:1267; RV32IF: # %bb.0:1268; RV32IF-NEXT: addi sp, sp, -161269; RV32IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill1270; RV32IF-NEXT: fmv.s fs10, fa01271; RV32IF-NEXT: #APP1272; RV32IF-NEXT: fcvt.w.s a0, fs101273; RV32IF-NEXT: #NO_APP1274; RV32IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload1275; RV32IF-NEXT: addi sp, sp, 161276; RV32IF-NEXT: ret1277;1278; RV64IF-LABEL: explicit_register_fs10:1279; RV64IF: # %bb.0:1280; RV64IF-NEXT: addi sp, sp, -161281; RV64IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill1282; RV64IF-NEXT: fmv.s fs10, fa01283; RV64IF-NEXT: #APP1284; RV64IF-NEXT: fcvt.w.s a0, fs101285; RV64IF-NEXT: #NO_APP1286; RV64IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload1287; RV64IF-NEXT: addi sp, sp, 161288; RV64IF-NEXT: ret1289 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs10}"(float %a)1290 ret i32 %11291}1292 1293; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved.1294define i32 @explicit_register_f27(float %a) nounwind {1295; RV32IF-LABEL: explicit_register_f27:1296; RV32IF: # %bb.0:1297; RV32IF-NEXT: addi sp, sp, -161298; RV32IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill1299; RV32IF-NEXT: fmv.s fs11, fa01300; RV32IF-NEXT: #APP1301; RV32IF-NEXT: fcvt.w.s a0, fs111302; RV32IF-NEXT: #NO_APP1303; RV32IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload1304; RV32IF-NEXT: addi sp, sp, 161305; RV32IF-NEXT: ret1306;1307; RV64IF-LABEL: explicit_register_f27:1308; RV64IF: # %bb.0:1309; RV64IF-NEXT: addi sp, sp, -161310; RV64IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill1311; RV64IF-NEXT: fmv.s fs11, fa01312; RV64IF-NEXT: #APP1313; RV64IF-NEXT: fcvt.w.s a0, fs111314; RV64IF-NEXT: #NO_APP1315; RV64IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload1316; RV64IF-NEXT: addi sp, sp, 161317; RV64IF-NEXT: ret1318 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f27}"(float %a)1319 ret i32 %11320}1321 1322; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved.1323define i32 @explicit_register_fs11(float %a) nounwind {1324; RV32IF-LABEL: explicit_register_fs11:1325; RV32IF: # %bb.0:1326; RV32IF-NEXT: addi sp, sp, -161327; RV32IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill1328; RV32IF-NEXT: fmv.s fs11, fa01329; RV32IF-NEXT: #APP1330; RV32IF-NEXT: fcvt.w.s a0, fs111331; RV32IF-NEXT: #NO_APP1332; RV32IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload1333; RV32IF-NEXT: addi sp, sp, 161334; RV32IF-NEXT: ret1335;1336; RV64IF-LABEL: explicit_register_fs11:1337; RV64IF: # %bb.0:1338; RV64IF-NEXT: addi sp, sp, -161339; RV64IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill1340; RV64IF-NEXT: fmv.s fs11, fa01341; RV64IF-NEXT: #APP1342; RV64IF-NEXT: fcvt.w.s a0, fs111343; RV64IF-NEXT: #NO_APP1344; RV64IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload1345; RV64IF-NEXT: addi sp, sp, 161346; RV64IF-NEXT: ret1347 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs11}"(float %a)1348 ret i32 %11349}1350 1351define i32 @explicit_register_f28(float %a) nounwind {1352; RV32IF-LABEL: explicit_register_f28:1353; RV32IF: # %bb.0:1354; RV32IF-NEXT: fmv.s ft8, fa01355; RV32IF-NEXT: #APP1356; RV32IF-NEXT: fcvt.w.s a0, ft81357; RV32IF-NEXT: #NO_APP1358; RV32IF-NEXT: ret1359;1360; RV64IF-LABEL: explicit_register_f28:1361; RV64IF: # %bb.0:1362; RV64IF-NEXT: fmv.s ft8, fa01363; RV64IF-NEXT: #APP1364; RV64IF-NEXT: fcvt.w.s a0, ft81365; RV64IF-NEXT: #NO_APP1366; RV64IF-NEXT: ret1367 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f28}"(float %a)1368 ret i32 %11369}1370 1371define i32 @explicit_register_ft8(float %a) nounwind {1372; RV32IF-LABEL: explicit_register_ft8:1373; RV32IF: # %bb.0:1374; RV32IF-NEXT: fmv.s ft8, fa01375; RV32IF-NEXT: #APP1376; RV32IF-NEXT: fcvt.w.s a0, ft81377; RV32IF-NEXT: #NO_APP1378; RV32IF-NEXT: ret1379;1380; RV64IF-LABEL: explicit_register_ft8:1381; RV64IF: # %bb.0:1382; RV64IF-NEXT: fmv.s ft8, fa01383; RV64IF-NEXT: #APP1384; RV64IF-NEXT: fcvt.w.s a0, ft81385; RV64IF-NEXT: #NO_APP1386; RV64IF-NEXT: ret1387 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft8}"(float %a)1388 ret i32 %11389}1390 1391define i32 @explicit_register_f29(float %a) nounwind {1392; RV32IF-LABEL: explicit_register_f29:1393; RV32IF: # %bb.0:1394; RV32IF-NEXT: fmv.s ft9, fa01395; RV32IF-NEXT: #APP1396; RV32IF-NEXT: fcvt.w.s a0, ft91397; RV32IF-NEXT: #NO_APP1398; RV32IF-NEXT: ret1399;1400; RV64IF-LABEL: explicit_register_f29:1401; RV64IF: # %bb.0:1402; RV64IF-NEXT: fmv.s ft9, fa01403; RV64IF-NEXT: #APP1404; RV64IF-NEXT: fcvt.w.s a0, ft91405; RV64IF-NEXT: #NO_APP1406; RV64IF-NEXT: ret1407 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f29}"(float %a)1408 ret i32 %11409}1410 1411define i32 @explicit_register_ft9(float %a) nounwind {1412; RV32IF-LABEL: explicit_register_ft9:1413; RV32IF: # %bb.0:1414; RV32IF-NEXT: fmv.s ft9, fa01415; RV32IF-NEXT: #APP1416; RV32IF-NEXT: fcvt.w.s a0, ft91417; RV32IF-NEXT: #NO_APP1418; RV32IF-NEXT: ret1419;1420; RV64IF-LABEL: explicit_register_ft9:1421; RV64IF: # %bb.0:1422; RV64IF-NEXT: fmv.s ft9, fa01423; RV64IF-NEXT: #APP1424; RV64IF-NEXT: fcvt.w.s a0, ft91425; RV64IF-NEXT: #NO_APP1426; RV64IF-NEXT: ret1427 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft9}"(float %a)1428 ret i32 %11429}1430 1431define i32 @explicit_register_f30(float %a) nounwind {1432; RV32IF-LABEL: explicit_register_f30:1433; RV32IF: # %bb.0:1434; RV32IF-NEXT: fmv.s ft10, fa01435; RV32IF-NEXT: #APP1436; RV32IF-NEXT: fcvt.w.s a0, ft101437; RV32IF-NEXT: #NO_APP1438; RV32IF-NEXT: ret1439;1440; RV64IF-LABEL: explicit_register_f30:1441; RV64IF: # %bb.0:1442; RV64IF-NEXT: fmv.s ft10, fa01443; RV64IF-NEXT: #APP1444; RV64IF-NEXT: fcvt.w.s a0, ft101445; RV64IF-NEXT: #NO_APP1446; RV64IF-NEXT: ret1447 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f30}"(float %a)1448 ret i32 %11449}1450 1451define i32 @explicit_register_ft10(float %a) nounwind {1452; RV32IF-LABEL: explicit_register_ft10:1453; RV32IF: # %bb.0:1454; RV32IF-NEXT: fmv.s ft10, fa01455; RV32IF-NEXT: #APP1456; RV32IF-NEXT: fcvt.w.s a0, ft101457; RV32IF-NEXT: #NO_APP1458; RV32IF-NEXT: ret1459;1460; RV64IF-LABEL: explicit_register_ft10:1461; RV64IF: # %bb.0:1462; RV64IF-NEXT: fmv.s ft10, fa01463; RV64IF-NEXT: #APP1464; RV64IF-NEXT: fcvt.w.s a0, ft101465; RV64IF-NEXT: #NO_APP1466; RV64IF-NEXT: ret1467 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft10}"(float %a)1468 ret i32 %11469}1470 1471define i32 @explicit_register_f31(float %a) nounwind {1472; RV32IF-LABEL: explicit_register_f31:1473; RV32IF: # %bb.0:1474; RV32IF-NEXT: fmv.s ft11, fa01475; RV32IF-NEXT: #APP1476; RV32IF-NEXT: fcvt.w.s a0, ft111477; RV32IF-NEXT: #NO_APP1478; RV32IF-NEXT: ret1479;1480; RV64IF-LABEL: explicit_register_f31:1481; RV64IF: # %bb.0:1482; RV64IF-NEXT: fmv.s ft11, fa01483; RV64IF-NEXT: #APP1484; RV64IF-NEXT: fcvt.w.s a0, ft111485; RV64IF-NEXT: #NO_APP1486; RV64IF-NEXT: ret1487 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f31}"(float %a)1488 ret i32 %11489}1490 1491define i32 @explicit_register_ft11(float %a) nounwind {1492; RV32IF-LABEL: explicit_register_ft11:1493; RV32IF: # %bb.0:1494; RV32IF-NEXT: fmv.s ft11, fa01495; RV32IF-NEXT: #APP1496; RV32IF-NEXT: fcvt.w.s a0, ft111497; RV32IF-NEXT: #NO_APP1498; RV32IF-NEXT: ret1499;1500; RV64IF-LABEL: explicit_register_ft11:1501; RV64IF: # %bb.0:1502; RV64IF-NEXT: fmv.s ft11, fa01503; RV64IF-NEXT: #APP1504; RV64IF-NEXT: fcvt.w.s a0, ft111505; RV64IF-NEXT: #NO_APP1506; RV64IF-NEXT: ret1507 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft11}"(float %a)1508 ret i32 %11509}1510