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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32F %s4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64F %s6; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \7; RUN: | FileCheck -check-prefix=RV32F %s8; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \9; RUN: | FileCheck -check-prefix=RV64F %s10 11@gf = external global float12 13define float @constraint_f_float(float %a) nounwind {14; RV32F-LABEL: constraint_f_float:15; RV32F: # %bb.0:16; RV32F-NEXT: lui a1, %hi(gf)17; RV32F-NEXT: flw fa5, %lo(gf)(a1)18; RV32F-NEXT: fmv.w.x fa4, a019; RV32F-NEXT: #APP20; RV32F-NEXT: fadd.s fa5, fa4, fa521; RV32F-NEXT: #NO_APP22; RV32F-NEXT: fmv.x.w a0, fa523; RV32F-NEXT: ret24;25; RV64F-LABEL: constraint_f_float:26; RV64F: # %bb.0:27; RV64F-NEXT: lui a1, %hi(gf)28; RV64F-NEXT: flw fa5, %lo(gf)(a1)29; RV64F-NEXT: fmv.w.x fa4, a030; RV64F-NEXT: #APP31; RV64F-NEXT: fadd.s fa5, fa4, fa532; RV64F-NEXT: #NO_APP33; RV64F-NEXT: fmv.x.w a0, fa534; RV64F-NEXT: ret35 %1 = load float, ptr @gf36 %2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1)37 ret float %238}39 40define float @constraint_cf_float(float %a) nounwind {41; RV32F-LABEL: constraint_cf_float:42; RV32F: # %bb.0:43; RV32F-NEXT: lui a1, %hi(gf)44; RV32F-NEXT: flw fa5, %lo(gf)(a1)45; RV32F-NEXT: fmv.w.x fa4, a046; RV32F-NEXT: #APP47; RV32F-NEXT: fadd.s fa5, fa4, fa548; RV32F-NEXT: #NO_APP49; RV32F-NEXT: fmv.x.w a0, fa550; RV32F-NEXT: ret51;52; RV64F-LABEL: constraint_cf_float:53; RV64F: # %bb.0:54; RV64F-NEXT: lui a1, %hi(gf)55; RV64F-NEXT: flw fa5, %lo(gf)(a1)56; RV64F-NEXT: fmv.w.x fa4, a057; RV64F-NEXT: #APP58; RV64F-NEXT: fadd.s fa5, fa4, fa559; RV64F-NEXT: #NO_APP60; RV64F-NEXT: fmv.x.w a0, fa561; RV64F-NEXT: ret62 %1 = load float, ptr @gf63 %2 = tail call float asm "fadd.s $0, $1, $2", "=^cf,cf,cf"(float %a, float %1)64 ret float %265}66 67define float @constraint_f_float_abi_name(float %a) nounwind {68; RV32F-LABEL: constraint_f_float_abi_name:69; RV32F: # %bb.0:70; RV32F-NEXT: lui a1, %hi(gf)71; RV32F-NEXT: flw fs0, %lo(gf)(a1)72; RV32F-NEXT: fmv.w.x fa0, a073; RV32F-NEXT: #APP74; RV32F-NEXT: fadd.s ft0, fa0, fs075; RV32F-NEXT: #NO_APP76; RV32F-NEXT: fmv.x.w a0, ft077; RV32F-NEXT: ret78;79; RV64F-LABEL: constraint_f_float_abi_name:80; RV64F: # %bb.0:81; RV64F-NEXT: lui a1, %hi(gf)82; RV64F-NEXT: flw fs0, %lo(gf)(a1)83; RV64F-NEXT: fmv.w.x fa0, a084; RV64F-NEXT: #APP85; RV64F-NEXT: fadd.s ft0, fa0, fs086; RV64F-NEXT: #NO_APP87; RV64F-NEXT: fmv.x.w a0, ft088; RV64F-NEXT: ret89 %1 = load float, ptr @gf90 %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1)91 ret float %292}93 94define float @constraint_gpr(float %x) {95; RV32F-LABEL: constraint_gpr:96; RV32F: # %bb.0:97; RV32F-NEXT: #APP98; RV32F-NEXT: mv a0, a099; RV32F-NEXT: #NO_APP100; RV32F-NEXT: ret101;102; RV64F-LABEL: constraint_gpr:103; RV64F: # %bb.0:104; RV64F-NEXT: #APP105; RV64F-NEXT: mv a0, a0106; RV64F-NEXT: #NO_APP107; RV64F-NEXT: ret108 %1 = tail call float asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(float %x)109 ret float %1110}111