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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32I %s4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64I %s6 7define <1 x i8> @constraint_vr_fixed(<1 x i8> %0, <1 x i8> %1) nounwind {8; RV32I-LABEL: constraint_vr_fixed:9; RV32I: # %bb.0:10; RV32I-NEXT: #APP11; RV32I-NEXT: vadd.vv v8, v8, v912; RV32I-NEXT: #NO_APP13; RV32I-NEXT: ret14;15; RV64I-LABEL: constraint_vr_fixed:16; RV64I: # %bb.0:17; RV64I-NEXT: #APP18; RV64I-NEXT: vadd.vv v8, v8, v919; RV64I-NEXT: #NO_APP20; RV64I-NEXT: ret21 %a = tail call <1 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(22 <1 x i8> %0, <1 x i8> %1)23 ret <1 x i8> %a24}25 26define <4 x i32> @constraint_vd_fixed(<4 x i32> %0, <4 x i32> %1) nounwind {27; RV32I-LABEL: constraint_vd_fixed:28; RV32I: # %bb.0:29; RV32I-NEXT: #APP30; RV32I-NEXT: vadd.vv v8, v8, v931; RV32I-NEXT: #NO_APP32; RV32I-NEXT: ret33;34; RV64I-LABEL: constraint_vd_fixed:35; RV64I: # %bb.0:36; RV64I-NEXT: #APP37; RV64I-NEXT: vadd.vv v8, v8, v938; RV64I-NEXT: #NO_APP39; RV64I-NEXT: ret40 %a = tail call <4 x i32> asm "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"(41 <4 x i32> %0, <4 x i32> %1)42 ret <4 x i32> %a43}44 45define <16 x i1> @constraint_vm_fixed(<16 x i1> %0, <16 x i1> %1) nounwind {46; RV32I-LABEL: constraint_vm_fixed:47; RV32I: # %bb.0:48; RV32I-NEXT: vsetivli zero, 1, e8, m1, ta, ma49; RV32I-NEXT: vmv1r.v v9, v050; RV32I-NEXT: vmv1r.v v0, v851; RV32I-NEXT: #APP52; RV32I-NEXT: vadd.vv v0, v9, v053; RV32I-NEXT: #NO_APP54; RV32I-NEXT: ret55;56; RV64I-LABEL: constraint_vm_fixed:57; RV64I: # %bb.0:58; RV64I-NEXT: vsetivli zero, 1, e8, m1, ta, ma59; RV64I-NEXT: vmv1r.v v9, v060; RV64I-NEXT: vmv1r.v v0, v861; RV64I-NEXT: #APP62; RV64I-NEXT: vadd.vv v0, v9, v063; RV64I-NEXT: #NO_APP64; RV64I-NEXT: ret65 %a = tail call <16 x i1> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vm"(66 <16 x i1> %0, <16 x i1> %1)67 ret <16 x i1> %a68}69