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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7; VCIX instructions can not reorder between each other.8define void @test_reorder(<vscale x 1 x i64> %vreg) {9; CHECK-LABEL: test_reorder:10; CHECK: # %bb.0: # %entry11; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma12; CHECK-NEXT: sf.vc.iv 0, 0, v8, 013; CHECK-NEXT: #APP14; CHECK-NEXT: sf.vc.vv 3, 0, v8, v815; CHECK-EMPTY:16; CHECK-NEXT: #NO_APP17; CHECK-NEXT: ret18entry:19 call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen 0, <vscale x 1 x i64> %vreg, iXLen 0, iXLen 0)20 call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;", "=r,^vr,~{memory},~{vl},~{sf.vcix_state}"(<vscale x 1 x i64> %vreg)21 ret void22}23