195 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=zfh -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32ZFH %s4; RUN: llc -mtriple=riscv64 -mattr=zfh -verify-machineinstrs < %s \5; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64ZFH %s6; RUN: llc -mtriple=riscv32 -mattr=zfh,+d -verify-machineinstrs < %s \7; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32DZFH %s8; RUN: llc -mtriple=riscv64 -mattr=zfh,+d -verify-machineinstrs < %s \9; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64DZFH %s10 11@gh = external global half12 13define half @constraint_f_half(half %a) nounwind {14; RV32ZFH-LABEL: constraint_f_half:15; RV32ZFH: # %bb.0:16; RV32ZFH-NEXT: lui a0, %hi(gh)17; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0)18; RV32ZFH-NEXT: #APP19; RV32ZFH-NEXT: fadd.h fa0, fa0, fa520; RV32ZFH-NEXT: #NO_APP21; RV32ZFH-NEXT: ret22;23; RV64ZFH-LABEL: constraint_f_half:24; RV64ZFH: # %bb.0:25; RV64ZFH-NEXT: lui a0, %hi(gh)26; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0)27; RV64ZFH-NEXT: #APP28; RV64ZFH-NEXT: fadd.h fa0, fa0, fa529; RV64ZFH-NEXT: #NO_APP30; RV64ZFH-NEXT: ret31;32; RV32DZFH-LABEL: constraint_f_half:33; RV32DZFH: # %bb.0:34; RV32DZFH-NEXT: lui a0, %hi(gh)35; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0)36; RV32DZFH-NEXT: #APP37; RV32DZFH-NEXT: fadd.h fa0, fa0, fa538; RV32DZFH-NEXT: #NO_APP39; RV32DZFH-NEXT: ret40;41; RV64DZFH-LABEL: constraint_f_half:42; RV64DZFH: # %bb.0:43; RV64DZFH-NEXT: lui a0, %hi(gh)44; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0)45; RV64DZFH-NEXT: #APP46; RV64DZFH-NEXT: fadd.h fa0, fa0, fa547; RV64DZFH-NEXT: #NO_APP48; RV64DZFH-NEXT: ret49 %1 = load half, ptr @gh50 %2 = tail call half asm "fadd.h $0, $1, $2", "=f,f,f"(half %a, half %1)51 ret half %252}53 54define half @constraint_cf_half(half %a) nounwind {55; RV32ZFH-LABEL: constraint_cf_half:56; RV32ZFH: # %bb.0:57; RV32ZFH-NEXT: lui a0, %hi(gh)58; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0)59; RV32ZFH-NEXT: #APP60; RV32ZFH-NEXT: fadd.h fa0, fa0, fa561; RV32ZFH-NEXT: #NO_APP62; RV32ZFH-NEXT: ret63;64; RV64ZFH-LABEL: constraint_cf_half:65; RV64ZFH: # %bb.0:66; RV64ZFH-NEXT: lui a0, %hi(gh)67; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0)68; RV64ZFH-NEXT: #APP69; RV64ZFH-NEXT: fadd.h fa0, fa0, fa570; RV64ZFH-NEXT: #NO_APP71; RV64ZFH-NEXT: ret72;73; RV32DZFH-LABEL: constraint_cf_half:74; RV32DZFH: # %bb.0:75; RV32DZFH-NEXT: lui a0, %hi(gh)76; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0)77; RV32DZFH-NEXT: #APP78; RV32DZFH-NEXT: fadd.h fa0, fa0, fa579; RV32DZFH-NEXT: #NO_APP80; RV32DZFH-NEXT: ret81;82; RV64DZFH-LABEL: constraint_cf_half:83; RV64DZFH: # %bb.0:84; RV64DZFH-NEXT: lui a0, %hi(gh)85; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0)86; RV64DZFH-NEXT: #APP87; RV64DZFH-NEXT: fadd.h fa0, fa0, fa588; RV64DZFH-NEXT: #NO_APP89; RV64DZFH-NEXT: ret90 %1 = load half, ptr @gh91 %2 = tail call half asm "fadd.h $0, $1, $2", "=^cf,^cf,^cf"(half %a, half %1)92 ret half %293}94 95define half @constraint_f_half_abi_name(half %a) nounwind {96; RV32ZFH-LABEL: constraint_f_half_abi_name:97; RV32ZFH: # %bb.0:98; RV32ZFH-NEXT: addi sp, sp, -1699; RV32ZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill100; RV32ZFH-NEXT: lui a0, %hi(gh)101; RV32ZFH-NEXT: flh fs0, %lo(gh)(a0)102; RV32ZFH-NEXT: #APP103; RV32ZFH-NEXT: fadd.s ft0, fa0, fs0104; RV32ZFH-NEXT: #NO_APP105; RV32ZFH-NEXT: fmv.h fa0, ft0106; RV32ZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload107; RV32ZFH-NEXT: addi sp, sp, 16108; RV32ZFH-NEXT: ret109;110; RV64ZFH-LABEL: constraint_f_half_abi_name:111; RV64ZFH: # %bb.0:112; RV64ZFH-NEXT: addi sp, sp, -16113; RV64ZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill114; RV64ZFH-NEXT: lui a0, %hi(gh)115; RV64ZFH-NEXT: flh fs0, %lo(gh)(a0)116; RV64ZFH-NEXT: #APP117; RV64ZFH-NEXT: fadd.s ft0, fa0, fs0118; RV64ZFH-NEXT: #NO_APP119; RV64ZFH-NEXT: fmv.h fa0, ft0120; RV64ZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload121; RV64ZFH-NEXT: addi sp, sp, 16122; RV64ZFH-NEXT: ret123;124; RV32DZFH-LABEL: constraint_f_half_abi_name:125; RV32DZFH: # %bb.0:126; RV32DZFH-NEXT: addi sp, sp, -16127; RV32DZFH-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill128; RV32DZFH-NEXT: lui a0, %hi(gh)129; RV32DZFH-NEXT: flh fs0, %lo(gh)(a0)130; RV32DZFH-NEXT: #APP131; RV32DZFH-NEXT: fadd.s ft0, fa0, fs0132; RV32DZFH-NEXT: #NO_APP133; RV32DZFH-NEXT: fmv.h fa0, ft0134; RV32DZFH-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload135; RV32DZFH-NEXT: addi sp, sp, 16136; RV32DZFH-NEXT: ret137;138; RV64DZFH-LABEL: constraint_f_half_abi_name:139; RV64DZFH: # %bb.0:140; RV64DZFH-NEXT: addi sp, sp, -16141; RV64DZFH-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill142; RV64DZFH-NEXT: lui a0, %hi(gh)143; RV64DZFH-NEXT: flh fs0, %lo(gh)(a0)144; RV64DZFH-NEXT: #APP145; RV64DZFH-NEXT: fadd.s ft0, fa0, fs0146; RV64DZFH-NEXT: #NO_APP147; RV64DZFH-NEXT: fmv.h fa0, ft0148; RV64DZFH-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload149; RV64DZFH-NEXT: addi sp, sp, 16150; RV64DZFH-NEXT: ret151 %1 = load half, ptr @gh152 %2 = tail call half asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(half %a, half %1)153 ret half %2154}155 156define half @constraint_gpr(half %x) {157; RV32ZFH-LABEL: constraint_gpr:158; RV32ZFH: # %bb.0:159; RV32ZFH-NEXT: fmv.x.h a0, fa0160; RV32ZFH-NEXT: #APP161; RV32ZFH-NEXT: mv a0, a0162; RV32ZFH-NEXT: #NO_APP163; RV32ZFH-NEXT: fmv.h.x fa0, a0164; RV32ZFH-NEXT: ret165;166; RV64ZFH-LABEL: constraint_gpr:167; RV64ZFH: # %bb.0:168; RV64ZFH-NEXT: fmv.x.h a0, fa0169; RV64ZFH-NEXT: #APP170; RV64ZFH-NEXT: mv a0, a0171; RV64ZFH-NEXT: #NO_APP172; RV64ZFH-NEXT: fmv.h.x fa0, a0173; RV64ZFH-NEXT: ret174;175; RV32DZFH-LABEL: constraint_gpr:176; RV32DZFH: # %bb.0:177; RV32DZFH-NEXT: fmv.x.h a0, fa0178; RV32DZFH-NEXT: #APP179; RV32DZFH-NEXT: mv a0, a0180; RV32DZFH-NEXT: #NO_APP181; RV32DZFH-NEXT: fmv.h.x fa0, a0182; RV32DZFH-NEXT: ret183;184; RV64DZFH-LABEL: constraint_gpr:185; RV64DZFH: # %bb.0:186; RV64DZFH-NEXT: fmv.x.h a0, fa0187; RV64DZFH-NEXT: #APP188; RV64DZFH-NEXT: mv a0, a0189; RV64DZFH-NEXT: #NO_APP190; RV64DZFH-NEXT: fmv.h.x fa0, a0191; RV64DZFH-NEXT: ret192 %1 = tail call half asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(half %x)193 ret half %1194}195