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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=zfh -verify-machineinstrs -no-integrated-as < %s \3; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32ZFH %s4; RUN: llc -mtriple=riscv64 -mattr=zfh -verify-machineinstrs -no-integrated-as < %s \5; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64ZFH %s6; RUN: llc -mtriple=riscv32 -mattr=zfh,+d -verify-machineinstrs -no-integrated-as < %s \7; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32DZFH %s8; RUN: llc -mtriple=riscv64 -mattr=zfh,+d -verify-machineinstrs -no-integrated-as < %s \9; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64DZFH %s10 11;; `.insn 0x4, 0x04000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is12;; the raw encoding for `fadd.h`13 14@gh = external global half15 16define half @constraint_f_half(half %a) nounwind {17; RV32ZFH-LABEL: constraint_f_half:18; RV32ZFH: # %bb.0:19; RV32ZFH-NEXT: lui a0, %hi(gh)20; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0)21; RV32ZFH-NEXT: #APP22; RV32ZFH-NEXT: .insn 0x4, 0x04000053 | (10 << 7) | (10 << 15) | (15 << 20)23; RV32ZFH-NEXT: #NO_APP24; RV32ZFH-NEXT: ret25;26; RV64ZFH-LABEL: constraint_f_half:27; RV64ZFH: # %bb.0:28; RV64ZFH-NEXT: lui a0, %hi(gh)29; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0)30; RV64ZFH-NEXT: #APP31; RV64ZFH-NEXT: .insn 0x4, 0x04000053 | (10 << 7) | (10 << 15) | (15 << 20)32; RV64ZFH-NEXT: #NO_APP33; RV64ZFH-NEXT: ret34;35; RV32DZFH-LABEL: constraint_f_half:36; RV32DZFH: # %bb.0:37; RV32DZFH-NEXT: lui a0, %hi(gh)38; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0)39; RV32DZFH-NEXT: #APP40; RV32DZFH-NEXT: .insn 0x4, 0x04000053 | (10 << 7) | (10 << 15) | (15 << 20)41; RV32DZFH-NEXT: #NO_APP42; RV32DZFH-NEXT: ret43;44; RV64DZFH-LABEL: constraint_f_half:45; RV64DZFH: # %bb.0:46; RV64DZFH-NEXT: lui a0, %hi(gh)47; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0)48; RV64DZFH-NEXT: #APP49; RV64DZFH-NEXT: .insn 0x4, 0x04000053 | (10 << 7) | (10 << 15) | (15 << 20)50; RV64DZFH-NEXT: #NO_APP51; RV64DZFH-NEXT: ret52 %1 = load half, ptr @gh53 %2 = tail call half asm ".insn 0x4, 0x04000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=f,f,f"(half %a, half %1)54 ret half %255}56 57define half @constraint_cf_half(half %a) nounwind {58; RV32ZFH-LABEL: constraint_cf_half:59; RV32ZFH: # %bb.0:60; RV32ZFH-NEXT: lui a0, %hi(gh)61; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0)62; RV32ZFH-NEXT: #APP63; RV32ZFH-NEXT: .insn 0x4, 0x04000053 | (10 << 7) | (10 << 15) | (15 << 20)64; RV32ZFH-NEXT: #NO_APP65; RV32ZFH-NEXT: ret66;67; RV64ZFH-LABEL: constraint_cf_half:68; RV64ZFH: # %bb.0:69; RV64ZFH-NEXT: lui a0, %hi(gh)70; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0)71; RV64ZFH-NEXT: #APP72; RV64ZFH-NEXT: .insn 0x4, 0x04000053 | (10 << 7) | (10 << 15) | (15 << 20)73; RV64ZFH-NEXT: #NO_APP74; RV64ZFH-NEXT: ret75;76; RV32DZFH-LABEL: constraint_cf_half:77; RV32DZFH: # %bb.0:78; RV32DZFH-NEXT: lui a0, %hi(gh)79; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0)80; RV32DZFH-NEXT: #APP81; RV32DZFH-NEXT: .insn 0x4, 0x04000053 | (10 << 7) | (10 << 15) | (15 << 20)82; RV32DZFH-NEXT: #NO_APP83; RV32DZFH-NEXT: ret84;85; RV64DZFH-LABEL: constraint_cf_half:86; RV64DZFH: # %bb.0:87; RV64DZFH-NEXT: lui a0, %hi(gh)88; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0)89; RV64DZFH-NEXT: #APP90; RV64DZFH-NEXT: .insn 0x4, 0x04000053 | (10 << 7) | (10 << 15) | (15 << 20)91; RV64DZFH-NEXT: #NO_APP92; RV64DZFH-NEXT: ret93 %1 = load half, ptr @gh94 %2 = tail call half asm ".insn 0x4, 0x04000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=^cf,^cf,^cf"(half %a, half %1)95 ret half %296}97 98define half @constraint_f_half_abi_name(half %a) nounwind {99; RV32ZFH-LABEL: constraint_f_half_abi_name:100; RV32ZFH: # %bb.0:101; RV32ZFH-NEXT: addi sp, sp, -16102; RV32ZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill103; RV32ZFH-NEXT: lui a0, %hi(gh)104; RV32ZFH-NEXT: flh fs0, %lo(gh)(a0)105; RV32ZFH-NEXT: #APP106; RV32ZFH-NEXT: .insn 0x4, 0x04000053 | (0 << 7) | (10 << 15) | (8 << 20)107; RV32ZFH-NEXT: #NO_APP108; RV32ZFH-NEXT: fmv.h fa0, ft0109; RV32ZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload110; RV32ZFH-NEXT: addi sp, sp, 16111; RV32ZFH-NEXT: ret112;113; RV64ZFH-LABEL: constraint_f_half_abi_name:114; RV64ZFH: # %bb.0:115; RV64ZFH-NEXT: addi sp, sp, -16116; RV64ZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill117; RV64ZFH-NEXT: lui a0, %hi(gh)118; RV64ZFH-NEXT: flh fs0, %lo(gh)(a0)119; RV64ZFH-NEXT: #APP120; RV64ZFH-NEXT: .insn 0x4, 0x04000053 | (0 << 7) | (10 << 15) | (8 << 20)121; RV64ZFH-NEXT: #NO_APP122; RV64ZFH-NEXT: fmv.h fa0, ft0123; RV64ZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload124; RV64ZFH-NEXT: addi sp, sp, 16125; RV64ZFH-NEXT: ret126;127; RV32DZFH-LABEL: constraint_f_half_abi_name:128; RV32DZFH: # %bb.0:129; RV32DZFH-NEXT: addi sp, sp, -16130; RV32DZFH-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill131; RV32DZFH-NEXT: lui a0, %hi(gh)132; RV32DZFH-NEXT: flh fs0, %lo(gh)(a0)133; RV32DZFH-NEXT: #APP134; RV32DZFH-NEXT: .insn 0x4, 0x04000053 | (0 << 7) | (10 << 15) | (8 << 20)135; RV32DZFH-NEXT: #NO_APP136; RV32DZFH-NEXT: fmv.h fa0, ft0137; RV32DZFH-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload138; RV32DZFH-NEXT: addi sp, sp, 16139; RV32DZFH-NEXT: ret140;141; RV64DZFH-LABEL: constraint_f_half_abi_name:142; RV64DZFH: # %bb.0:143; RV64DZFH-NEXT: addi sp, sp, -16144; RV64DZFH-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill145; RV64DZFH-NEXT: lui a0, %hi(gh)146; RV64DZFH-NEXT: flh fs0, %lo(gh)(a0)147; RV64DZFH-NEXT: #APP148; RV64DZFH-NEXT: .insn 0x4, 0x04000053 | (0 << 7) | (10 << 15) | (8 << 20)149; RV64DZFH-NEXT: #NO_APP150; RV64DZFH-NEXT: fmv.h fa0, ft0151; RV64DZFH-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload152; RV64DZFH-NEXT: addi sp, sp, 16153; RV64DZFH-NEXT: ret154 %1 = load half, ptr @gh155 %2 = tail call half asm ".insn 0x4, 0x04000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "={ft0},{fa0},{fs0}"(half %a, half %1)156 ret half %2157}158