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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+zfinx -target-abi=ilp32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32FINX %s4; RUN: llc -mtriple=riscv64 -mattr=+zfinx -target-abi=lp64 -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64FINX %s6 7@gf = external global float8 9define float @constraint_r_float(float %a) nounwind {10; RV32FINX-LABEL: constraint_r_float:11; RV32FINX: # %bb.0:12; RV32FINX-NEXT: lui a1, %hi(gf)13; RV32FINX-NEXT: lw a1, %lo(gf)(a1)14; RV32FINX-NEXT: #APP15; RV32FINX-NEXT: fadd.s a0, a0, a116; RV32FINX-NEXT: #NO_APP17; RV32FINX-NEXT: ret18;19; RV64FINX-LABEL: constraint_r_float:20; RV64FINX: # %bb.0:21; RV64FINX-NEXT: lui a1, %hi(gf)22; RV64FINX-NEXT: lw a1, %lo(gf)(a1)23; RV64FINX-NEXT: #APP24; RV64FINX-NEXT: fadd.s a0, a0, a125; RV64FINX-NEXT: #NO_APP26; RV64FINX-NEXT: ret27 %1 = load float, ptr @gf28 %2 = tail call float asm "fadd.s $0, $1, $2", "=r,r,r"(float %a, float %1)29 ret float %230}31 32define float @constraint_cr_float(float %a) nounwind {33; RV32FINX-LABEL: constraint_cr_float:34; RV32FINX: # %bb.0:35; RV32FINX-NEXT: lui a1, %hi(gf)36; RV32FINX-NEXT: lw a1, %lo(gf)(a1)37; RV32FINX-NEXT: #APP38; RV32FINX-NEXT: fadd.s a0, a0, a139; RV32FINX-NEXT: #NO_APP40; RV32FINX-NEXT: ret41;42; RV64FINX-LABEL: constraint_cr_float:43; RV64FINX: # %bb.0:44; RV64FINX-NEXT: lui a1, %hi(gf)45; RV64FINX-NEXT: lw a1, %lo(gf)(a1)46; RV64FINX-NEXT: #APP47; RV64FINX-NEXT: fadd.s a0, a0, a148; RV64FINX-NEXT: #NO_APP49; RV64FINX-NEXT: ret50 %1 = load float, ptr @gf51 %2 = tail call float asm "fadd.s $0, $1, $2", "=^cr,cr,cr"(float %a, float %1)52 ret float %253}54 55define float @constraint_float_abi_name(float %a) nounwind {56; RV32FINX-LABEL: constraint_float_abi_name:57; RV32FINX: # %bb.0:58; RV32FINX-NEXT: addi sp, sp, -1659; RV32FINX-NEXT: sw s0, 12(sp) # 4-byte Folded Spill60; RV32FINX-NEXT: lui a1, %hi(gf)61; RV32FINX-NEXT: lw s0, %lo(gf)(a1)62; RV32FINX-NEXT: # kill: def $x10_w killed $x10_w def $x1063; RV32FINX-NEXT: #APP64; RV32FINX-NEXT: fadd.s t0, a0, s065; RV32FINX-NEXT: #NO_APP66; RV32FINX-NEXT: mv a0, t067; RV32FINX-NEXT: lw s0, 12(sp) # 4-byte Folded Reload68; RV32FINX-NEXT: addi sp, sp, 1669; RV32FINX-NEXT: ret70;71; RV64FINX-LABEL: constraint_float_abi_name:72; RV64FINX: # %bb.0:73; RV64FINX-NEXT: addi sp, sp, -1674; RV64FINX-NEXT: sd s0, 8(sp) # 8-byte Folded Spill75; RV64FINX-NEXT: lui a1, %hi(gf)76; RV64FINX-NEXT: lw s0, %lo(gf)(a1)77; RV64FINX-NEXT: # kill: def $x10_w killed $x10_w def $x1078; RV64FINX-NEXT: #APP79; RV64FINX-NEXT: fadd.s t0, a0, s080; RV64FINX-NEXT: #NO_APP81; RV64FINX-NEXT: mv a0, t082; RV64FINX-NEXT: ld s0, 8(sp) # 8-byte Folded Reload83; RV64FINX-NEXT: addi sp, sp, 1684; RV64FINX-NEXT: ret85 %1 = load float, ptr @gf86 %2 = tail call float asm "fadd.s $0, $1, $2", "={t0},{a0},{s0}"(float %a, float %1)87 ret float %288}89 90define float @constraint_f_float(float %a) nounwind {91; RV32FINX-LABEL: constraint_f_float:92; RV32FINX: # %bb.0:93; RV32FINX-NEXT: lui a1, %hi(gf)94; RV32FINX-NEXT: lw a1, %lo(gf)(a1)95; RV32FINX-NEXT: #APP96; RV32FINX-NEXT: fadd.s a0, a0, a197; RV32FINX-NEXT: #NO_APP98; RV32FINX-NEXT: ret99;100; RV64FINX-LABEL: constraint_f_float:101; RV64FINX: # %bb.0:102; RV64FINX-NEXT: lui a1, %hi(gf)103; RV64FINX-NEXT: lw a1, %lo(gf)(a1)104; RV64FINX-NEXT: #APP105; RV64FINX-NEXT: fadd.s a0, a0, a1106; RV64FINX-NEXT: #NO_APP107; RV64FINX-NEXT: ret108 %1 = load float, ptr @gf109 %2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1)110 ret float %2111}112 113define float @constraint_cf_float(float %a) nounwind {114; RV32FINX-LABEL: constraint_cf_float:115; RV32FINX: # %bb.0:116; RV32FINX-NEXT: lui a1, %hi(gf)117; RV32FINX-NEXT: lw a1, %lo(gf)(a1)118; RV32FINX-NEXT: #APP119; RV32FINX-NEXT: fadd.s a0, a0, a1120; RV32FINX-NEXT: #NO_APP121; RV32FINX-NEXT: ret122;123; RV64FINX-LABEL: constraint_cf_float:124; RV64FINX: # %bb.0:125; RV64FINX-NEXT: lui a1, %hi(gf)126; RV64FINX-NEXT: lw a1, %lo(gf)(a1)127; RV64FINX-NEXT: #APP128; RV64FINX-NEXT: fadd.s a0, a0, a1129; RV64FINX-NEXT: #NO_APP130; RV64FINX-NEXT: ret131 %1 = load float, ptr @gf132 %2 = tail call float asm "fadd.s $0, $1, $2", "=^cf,cf,cf"(float %a, float %1)133 ret float %2134}135