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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32 | FileCheck -check-prefix=RV32ZHINX %s4; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \5; RUN: -target-abi=lp64 | FileCheck -check-prefix=RV64ZHINX %s6; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinx -verify-machineinstrs < %s \7; RUN: -target-abi=ilp32 | FileCheck -check-prefix=RV32DINXZHINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinx -verify-machineinstrs < %s \9; RUN: -target-abi=lp64 | FileCheck -check-prefix=RV64DINXZHINX %s10 11@gh = external global half12 13define half @constraint_r_half(half %a) nounwind {14; RV32ZHINX-LABEL: constraint_r_half:15; RV32ZHINX: # %bb.0:16; RV32ZHINX-NEXT: lui a1, %hi(gh)17; RV32ZHINX-NEXT: lh a1, %lo(gh)(a1)18; RV32ZHINX-NEXT: #APP19; RV32ZHINX-NEXT: fadd.h a0, a0, a120; RV32ZHINX-NEXT: #NO_APP21; RV32ZHINX-NEXT: ret22;23; RV64ZHINX-LABEL: constraint_r_half:24; RV64ZHINX: # %bb.0:25; RV64ZHINX-NEXT: lui a1, %hi(gh)26; RV64ZHINX-NEXT: lh a1, %lo(gh)(a1)27; RV64ZHINX-NEXT: #APP28; RV64ZHINX-NEXT: fadd.h a0, a0, a129; RV64ZHINX-NEXT: #NO_APP30; RV64ZHINX-NEXT: ret31;32; RV32DINXZHINX-LABEL: constraint_r_half:33; RV32DINXZHINX: # %bb.0:34; RV32DINXZHINX-NEXT: lui a1, %hi(gh)35; RV32DINXZHINX-NEXT: lh a1, %lo(gh)(a1)36; RV32DINXZHINX-NEXT: #APP37; RV32DINXZHINX-NEXT: fadd.h a0, a0, a138; RV32DINXZHINX-NEXT: #NO_APP39; RV32DINXZHINX-NEXT: ret40;41; RV64DINXZHINX-LABEL: constraint_r_half:42; RV64DINXZHINX: # %bb.0:43; RV64DINXZHINX-NEXT: lui a1, %hi(gh)44; RV64DINXZHINX-NEXT: lh a1, %lo(gh)(a1)45; RV64DINXZHINX-NEXT: #APP46; RV64DINXZHINX-NEXT: fadd.h a0, a0, a147; RV64DINXZHINX-NEXT: #NO_APP48; RV64DINXZHINX-NEXT: ret49 %1 = load half, ptr @gh50 %2 = tail call half asm "fadd.h $0, $1, $2", "=r,r,r"(half %a, half %1)51 ret half %252}53 54define half @constraint_cr_half(half %a) nounwind {55; RV32ZHINX-LABEL: constraint_cr_half:56; RV32ZHINX: # %bb.0:57; RV32ZHINX-NEXT: lui a1, %hi(gh)58; RV32ZHINX-NEXT: lh a1, %lo(gh)(a1)59; RV32ZHINX-NEXT: #APP60; RV32ZHINX-NEXT: fadd.h a0, a0, a161; RV32ZHINX-NEXT: #NO_APP62; RV32ZHINX-NEXT: ret63;64; RV64ZHINX-LABEL: constraint_cr_half:65; RV64ZHINX: # %bb.0:66; RV64ZHINX-NEXT: lui a1, %hi(gh)67; RV64ZHINX-NEXT: lh a1, %lo(gh)(a1)68; RV64ZHINX-NEXT: #APP69; RV64ZHINX-NEXT: fadd.h a0, a0, a170; RV64ZHINX-NEXT: #NO_APP71; RV64ZHINX-NEXT: ret72;73; RV32DINXZHINX-LABEL: constraint_cr_half:74; RV32DINXZHINX: # %bb.0:75; RV32DINXZHINX-NEXT: lui a1, %hi(gh)76; RV32DINXZHINX-NEXT: lh a1, %lo(gh)(a1)77; RV32DINXZHINX-NEXT: #APP78; RV32DINXZHINX-NEXT: fadd.h a0, a0, a179; RV32DINXZHINX-NEXT: #NO_APP80; RV32DINXZHINX-NEXT: ret81;82; RV64DINXZHINX-LABEL: constraint_cr_half:83; RV64DINXZHINX: # %bb.0:84; RV64DINXZHINX-NEXT: lui a1, %hi(gh)85; RV64DINXZHINX-NEXT: lh a1, %lo(gh)(a1)86; RV64DINXZHINX-NEXT: #APP87; RV64DINXZHINX-NEXT: fadd.h a0, a0, a188; RV64DINXZHINX-NEXT: #NO_APP89; RV64DINXZHINX-NEXT: ret90 %1 = load half, ptr @gh91 %2 = tail call half asm "fadd.h $0, $1, $2", "=^cr,^cr,^cr"(half %a, half %1)92 ret half %293}94 95define half @constraint_half_abi_name(half %a) nounwind {96; RV32ZHINX-LABEL: constraint_half_abi_name:97; RV32ZHINX: # %bb.0:98; RV32ZHINX-NEXT: addi sp, sp, -1699; RV32ZHINX-NEXT: sw s0, 12(sp) # 4-byte Folded Spill100; RV32ZHINX-NEXT: lui a1, %hi(gh)101; RV32ZHINX-NEXT: lh s0, %lo(gh)(a1)102; RV32ZHINX-NEXT: # kill: def $x10_h killed $x10_h def $x10103; RV32ZHINX-NEXT: #APP104; RV32ZHINX-NEXT: fadd.s t0, a0, s0105; RV32ZHINX-NEXT: #NO_APP106; RV32ZHINX-NEXT: mv a0, t0107; RV32ZHINX-NEXT: lw s0, 12(sp) # 4-byte Folded Reload108; RV32ZHINX-NEXT: addi sp, sp, 16109; RV32ZHINX-NEXT: ret110;111; RV64ZHINX-LABEL: constraint_half_abi_name:112; RV64ZHINX: # %bb.0:113; RV64ZHINX-NEXT: addi sp, sp, -16114; RV64ZHINX-NEXT: sd s0, 8(sp) # 8-byte Folded Spill115; RV64ZHINX-NEXT: lui a1, %hi(gh)116; RV64ZHINX-NEXT: lh s0, %lo(gh)(a1)117; RV64ZHINX-NEXT: # kill: def $x10_h killed $x10_h def $x10118; RV64ZHINX-NEXT: #APP119; RV64ZHINX-NEXT: fadd.s t0, a0, s0120; RV64ZHINX-NEXT: #NO_APP121; RV64ZHINX-NEXT: mv a0, t0122; RV64ZHINX-NEXT: ld s0, 8(sp) # 8-byte Folded Reload123; RV64ZHINX-NEXT: addi sp, sp, 16124; RV64ZHINX-NEXT: ret125;126; RV32DINXZHINX-LABEL: constraint_half_abi_name:127; RV32DINXZHINX: # %bb.0:128; RV32DINXZHINX-NEXT: addi sp, sp, -16129; RV32DINXZHINX-NEXT: sw s0, 12(sp) # 4-byte Folded Spill130; RV32DINXZHINX-NEXT: lui a1, %hi(gh)131; RV32DINXZHINX-NEXT: lh s0, %lo(gh)(a1)132; RV32DINXZHINX-NEXT: # kill: def $x10_h killed $x10_h def $x10133; RV32DINXZHINX-NEXT: #APP134; RV32DINXZHINX-NEXT: fadd.s t0, a0, s0135; RV32DINXZHINX-NEXT: #NO_APP136; RV32DINXZHINX-NEXT: mv a0, t0137; RV32DINXZHINX-NEXT: lw s0, 12(sp) # 4-byte Folded Reload138; RV32DINXZHINX-NEXT: addi sp, sp, 16139; RV32DINXZHINX-NEXT: ret140;141; RV64DINXZHINX-LABEL: constraint_half_abi_name:142; RV64DINXZHINX: # %bb.0:143; RV64DINXZHINX-NEXT: addi sp, sp, -16144; RV64DINXZHINX-NEXT: sd s0, 8(sp) # 8-byte Folded Spill145; RV64DINXZHINX-NEXT: lui a1, %hi(gh)146; RV64DINXZHINX-NEXT: lh s0, %lo(gh)(a1)147; RV64DINXZHINX-NEXT: # kill: def $x10_h killed $x10_h def $x10148; RV64DINXZHINX-NEXT: #APP149; RV64DINXZHINX-NEXT: fadd.s t0, a0, s0150; RV64DINXZHINX-NEXT: #NO_APP151; RV64DINXZHINX-NEXT: mv a0, t0152; RV64DINXZHINX-NEXT: ld s0, 8(sp) # 8-byte Folded Reload153; RV64DINXZHINX-NEXT: addi sp, sp, 16154; RV64DINXZHINX-NEXT: ret155 %1 = load half, ptr @gh156 %2 = tail call half asm "fadd.s $0, $1, $2", "={t0},{a0},{s0}"(half %a, half %1)157 ret half %2158}159 160define half @constraint_f_half(half %a) nounwind {161; RV32ZHINX-LABEL: constraint_f_half:162; RV32ZHINX: # %bb.0:163; RV32ZHINX-NEXT: lui a1, %hi(gh)164; RV32ZHINX-NEXT: lh a1, %lo(gh)(a1)165; RV32ZHINX-NEXT: #APP166; RV32ZHINX-NEXT: fadd.h a0, a0, a1167; RV32ZHINX-NEXT: #NO_APP168; RV32ZHINX-NEXT: ret169;170; RV64ZHINX-LABEL: constraint_f_half:171; RV64ZHINX: # %bb.0:172; RV64ZHINX-NEXT: lui a1, %hi(gh)173; RV64ZHINX-NEXT: lh a1, %lo(gh)(a1)174; RV64ZHINX-NEXT: #APP175; RV64ZHINX-NEXT: fadd.h a0, a0, a1176; RV64ZHINX-NEXT: #NO_APP177; RV64ZHINX-NEXT: ret178;179; RV32DINXZHINX-LABEL: constraint_f_half:180; RV32DINXZHINX: # %bb.0:181; RV32DINXZHINX-NEXT: lui a1, %hi(gh)182; RV32DINXZHINX-NEXT: lh a1, %lo(gh)(a1)183; RV32DINXZHINX-NEXT: #APP184; RV32DINXZHINX-NEXT: fadd.h a0, a0, a1185; RV32DINXZHINX-NEXT: #NO_APP186; RV32DINXZHINX-NEXT: ret187;188; RV64DINXZHINX-LABEL: constraint_f_half:189; RV64DINXZHINX: # %bb.0:190; RV64DINXZHINX-NEXT: lui a1, %hi(gh)191; RV64DINXZHINX-NEXT: lh a1, %lo(gh)(a1)192; RV64DINXZHINX-NEXT: #APP193; RV64DINXZHINX-NEXT: fadd.h a0, a0, a1194; RV64DINXZHINX-NEXT: #NO_APP195; RV64DINXZHINX-NEXT: ret196 %1 = load half, ptr @gh197 %2 = tail call half asm "fadd.h $0, $1, $2", "=f,f,f"(half %a, half %1)198 ret half %2199}200 201define half @constraint_cf_half(half %a) nounwind {202; RV32ZHINX-LABEL: constraint_cf_half:203; RV32ZHINX: # %bb.0:204; RV32ZHINX-NEXT: lui a1, %hi(gh)205; RV32ZHINX-NEXT: lh a1, %lo(gh)(a1)206; RV32ZHINX-NEXT: #APP207; RV32ZHINX-NEXT: fadd.h a0, a0, a1208; RV32ZHINX-NEXT: #NO_APP209; RV32ZHINX-NEXT: ret210;211; RV64ZHINX-LABEL: constraint_cf_half:212; RV64ZHINX: # %bb.0:213; RV64ZHINX-NEXT: lui a1, %hi(gh)214; RV64ZHINX-NEXT: lh a1, %lo(gh)(a1)215; RV64ZHINX-NEXT: #APP216; RV64ZHINX-NEXT: fadd.h a0, a0, a1217; RV64ZHINX-NEXT: #NO_APP218; RV64ZHINX-NEXT: ret219;220; RV32DINXZHINX-LABEL: constraint_cf_half:221; RV32DINXZHINX: # %bb.0:222; RV32DINXZHINX-NEXT: lui a1, %hi(gh)223; RV32DINXZHINX-NEXT: lh a1, %lo(gh)(a1)224; RV32DINXZHINX-NEXT: #APP225; RV32DINXZHINX-NEXT: fadd.h a0, a0, a1226; RV32DINXZHINX-NEXT: #NO_APP227; RV32DINXZHINX-NEXT: ret228;229; RV64DINXZHINX-LABEL: constraint_cf_half:230; RV64DINXZHINX: # %bb.0:231; RV64DINXZHINX-NEXT: lui a1, %hi(gh)232; RV64DINXZHINX-NEXT: lh a1, %lo(gh)(a1)233; RV64DINXZHINX-NEXT: #APP234; RV64DINXZHINX-NEXT: fadd.h a0, a0, a1235; RV64DINXZHINX-NEXT: #NO_APP236; RV64DINXZHINX-NEXT: ret237 %1 = load half, ptr @gh238 %2 = tail call half asm "fadd.h $0, $1, $2", "=^cf,^cf,^cf"(half %a, half %1)239 ret half %2240}241