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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s -check-prefix=RV323; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s -check-prefix=RV644 5; WITH VSCALE RANGE6 7define i32 @ctz_nxv4i32(<vscale x 4 x i32> %a) #0 {8; RV32-LABEL: ctz_nxv4i32:9; RV32: # %bb.0:10; RV32-NEXT: csrr a0, vlenb11; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma12; RV32-NEXT: vid.v v1013; RV32-NEXT: li a1, -114; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma15; RV32-NEXT: vmsne.vi v0, v8, 016; RV32-NEXT: srli a0, a0, 117; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma18; RV32-NEXT: vmv.v.x v8, a019; RV32-NEXT: vmadd.vx v10, a1, v820; RV32-NEXT: vmv.v.i v8, 021; RV32-NEXT: vmerge.vvm v8, v8, v10, v022; RV32-NEXT: vredmaxu.vs v8, v8, v823; RV32-NEXT: vmv.x.s a1, v824; RV32-NEXT: sub a0, a0, a125; RV32-NEXT: slli a0, a0, 1626; RV32-NEXT: srli a0, a0, 1627; RV32-NEXT: ret28;29; RV64-LABEL: ctz_nxv4i32:30; RV64: # %bb.0:31; RV64-NEXT: csrr a0, vlenb32; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma33; RV64-NEXT: vid.v v1034; RV64-NEXT: li a1, -135; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma36; RV64-NEXT: vmsne.vi v0, v8, 037; RV64-NEXT: srli a0, a0, 138; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma39; RV64-NEXT: vmv.v.x v8, a040; RV64-NEXT: vmadd.vx v10, a1, v841; RV64-NEXT: vmv.v.i v8, 042; RV64-NEXT: vmerge.vvm v8, v8, v10, v043; RV64-NEXT: vredmaxu.vs v8, v8, v844; RV64-NEXT: vmv.x.s a1, v845; RV64-NEXT: sub a0, a0, a146; RV64-NEXT: slli a0, a0, 4847; RV64-NEXT: srli a0, a0, 4848; RV64-NEXT: ret49 %res = call i32 @llvm.experimental.cttz.elts.i32.nxv4i32(<vscale x 4 x i32> %a, i1 0)50 ret i32 %res51}52 53; NO VSCALE RANGE54 55define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {56; RV32-LABEL: ctz_nxv8i1_no_range:57; RV32: # %bb.0:58; RV32-NEXT: addi sp, sp, -4859; RV32-NEXT: .cfi_def_cfa_offset 4860; RV32-NEXT: sw ra, 44(sp) # 4-byte Folded Spill61; RV32-NEXT: .cfi_offset ra, -462; RV32-NEXT: csrr a0, vlenb63; RV32-NEXT: slli a0, a0, 164; RV32-NEXT: sub sp, sp, a065; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb66; RV32-NEXT: addi a0, sp, 3267; RV32-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill68; RV32-NEXT: csrr a0, vlenb69; RV32-NEXT: srli a0, a0, 370; RV32-NEXT: li a2, 871; RV32-NEXT: li a1, 072; RV32-NEXT: li a3, 073; RV32-NEXT: call __muldi374; RV32-NEXT: sw a0, 16(sp)75; RV32-NEXT: sw a1, 20(sp)76; RV32-NEXT: addi a2, sp, 1677; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma78; RV32-NEXT: vlse64.v v16, (a2), zero79; RV32-NEXT: vid.v v880; RV32-NEXT: li a2, -181; RV32-NEXT: addi a3, sp, 3282; RV32-NEXT: vl2r.v v24, (a3) # vscale x 16-byte Folded Reload83; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma84; RV32-NEXT: vmsne.vi v0, v24, 085; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma86; RV32-NEXT: vmadd.vx v8, a2, v1687; RV32-NEXT: vmv.v.i v16, 088; RV32-NEXT: li a2, 3289; RV32-NEXT: vmerge.vim v16, v16, -1, v090; RV32-NEXT: vand.vv v8, v8, v1691; RV32-NEXT: vredmaxu.vs v8, v8, v892; RV32-NEXT: vmv.x.s a3, v893; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma94; RV32-NEXT: vsrl.vx v8, v8, a295; RV32-NEXT: sltu a2, a0, a396; RV32-NEXT: vmv.x.s a4, v897; RV32-NEXT: sub a1, a1, a498; RV32-NEXT: sub a1, a1, a299; RV32-NEXT: sub a0, a0, a3100; RV32-NEXT: csrr a2, vlenb101; RV32-NEXT: slli a2, a2, 1102; RV32-NEXT: add sp, sp, a2103; RV32-NEXT: .cfi_def_cfa sp, 48104; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload105; RV32-NEXT: .cfi_restore ra106; RV32-NEXT: addi sp, sp, 48107; RV32-NEXT: .cfi_def_cfa_offset 0108; RV32-NEXT: ret109;110; RV64-LABEL: ctz_nxv8i1_no_range:111; RV64: # %bb.0:112; RV64-NEXT: csrr a0, vlenb113; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma114; RV64-NEXT: vid.v v16115; RV64-NEXT: li a1, -1116; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma117; RV64-NEXT: vmsne.vi v0, v8, 0118; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma119; RV64-NEXT: vmv.v.x v8, a0120; RV64-NEXT: vmadd.vx v16, a1, v8121; RV64-NEXT: vmv.v.i v8, 0122; RV64-NEXT: vmerge.vvm v8, v8, v16, v0123; RV64-NEXT: vredmaxu.vs v8, v8, v8124; RV64-NEXT: vmv.x.s a1, v8125; RV64-NEXT: sub a0, a0, a1126; RV64-NEXT: ret127 %res = call i64 @llvm.experimental.cttz.elts.i64.nxv8i16(<vscale x 8 x i16> %a, i1 0)128 ret i64 %res129}130 131define i32 @ctz_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {132; RV32-LABEL: ctz_nxv16i1:133; RV32: # %bb.0:134; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma135; RV32-NEXT: vfirst.m a0, v8136; RV32-NEXT: bgez a0, .LBB2_2137; RV32-NEXT: # %bb.1:138; RV32-NEXT: csrr a0, vlenb139; RV32-NEXT: slli a0, a0, 1140; RV32-NEXT: .LBB2_2:141; RV32-NEXT: ret142;143; RV64-LABEL: ctz_nxv16i1:144; RV64: # %bb.0:145; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma146; RV64-NEXT: vfirst.m a0, v8147; RV64-NEXT: bgez a0, .LBB2_2148; RV64-NEXT: # %bb.1:149; RV64-NEXT: csrr a0, vlenb150; RV64-NEXT: slli a0, a0, 1151; RV64-NEXT: .LBB2_2:152; RV64-NEXT: ret153 %res = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1(<vscale x 16 x i1> %a, i1 0)154 ret i32 %res155}156 157define i32 @ctz_nxv16i1_poison(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {158; RV32-LABEL: ctz_nxv16i1_poison:159; RV32: # %bb.0:160; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma161; RV32-NEXT: vfirst.m a0, v8162; RV32-NEXT: ret163;164; RV64-LABEL: ctz_nxv16i1_poison:165; RV64: # %bb.0:166; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma167; RV64-NEXT: vfirst.m a0, v8168; RV64-NEXT: ret169 %res = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1(<vscale x 16 x i1> %a, i1 1)170 ret i32 %res171}172 173define i32 @ctz_v16i1(<16 x i1> %pg, <16 x i1> %a) {174; RV32-LABEL: ctz_v16i1:175; RV32: # %bb.0:176; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma177; RV32-NEXT: vfirst.m a0, v8178; RV32-NEXT: bgez a0, .LBB4_2179; RV32-NEXT: # %bb.1:180; RV32-NEXT: li a0, 16181; RV32-NEXT: .LBB4_2:182; RV32-NEXT: ret183;184; RV64-LABEL: ctz_v16i1:185; RV64: # %bb.0:186; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma187; RV64-NEXT: vfirst.m a0, v8188; RV64-NEXT: bgez a0, .LBB4_2189; RV64-NEXT: # %bb.1:190; RV64-NEXT: li a0, 16191; RV64-NEXT: .LBB4_2:192; RV64-NEXT: ret193 %res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 0)194 ret i32 %res195}196 197define i32 @ctz_v16i1_poison(<16 x i1> %pg, <16 x i1> %a) {198; RV32-LABEL: ctz_v16i1_poison:199; RV32: # %bb.0:200; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma201; RV32-NEXT: vfirst.m a0, v8202; RV32-NEXT: ret203;204; RV64-LABEL: ctz_v16i1_poison:205; RV64: # %bb.0:206; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma207; RV64-NEXT: vfirst.m a0, v8208; RV64-NEXT: ret209 %res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 1)210 ret i32 %res211}212 213define i16 @ctz_v8i1_i16_ret(<8 x i1> %a) {214; RV32-LABEL: ctz_v8i1_i16_ret:215; RV32: # %bb.0:216; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma217; RV32-NEXT: vfirst.m a0, v0218; RV32-NEXT: bgez a0, .LBB6_2219; RV32-NEXT: # %bb.1:220; RV32-NEXT: li a0, 8221; RV32-NEXT: .LBB6_2:222; RV32-NEXT: ret223;224; RV64-LABEL: ctz_v8i1_i16_ret:225; RV64: # %bb.0:226; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma227; RV64-NEXT: vfirst.m a0, v0228; RV64-NEXT: bgez a0, .LBB6_2229; RV64-NEXT: # %bb.1:230; RV64-NEXT: li a0, 8231; RV64-NEXT: .LBB6_2:232; RV64-NEXT: ret233 %res = call i16 @llvm.experimental.cttz.elts.i16.v8i1(<8 x i1> %a, i1 0)234 ret i16 %res235}236 237attributes #0 = { vscale_range(2,1024) }238