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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s -check-prefix=RV323; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s -check-prefix=RV644 5; FIXED WIDTH6 7define i16 @ctz_v4i32(<4 x i32> %a) {8; RV32-LABEL: ctz_v4i32:9; RV32: # %bb.0:10; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma11; RV32-NEXT: vmsne.vi v0, v8, 012; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma13; RV32-NEXT: vmv.v.i v8, 014; RV32-NEXT: vmerge.vim v8, v8, -1, v015; RV32-NEXT: vid.v v916; RV32-NEXT: vrsub.vi v9, v9, 417; RV32-NEXT: vand.vv v8, v8, v918; RV32-NEXT: vredmaxu.vs v8, v8, v819; RV32-NEXT: vmv.x.s a0, v820; RV32-NEXT: li a1, 421; RV32-NEXT: sub a1, a1, a022; RV32-NEXT: zext.b a0, a123; RV32-NEXT: ret24;25; RV64-LABEL: ctz_v4i32:26; RV64: # %bb.0:27; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma28; RV64-NEXT: vmsne.vi v0, v8, 029; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma30; RV64-NEXT: vmv.v.i v8, 031; RV64-NEXT: vmerge.vim v8, v8, -1, v032; RV64-NEXT: vid.v v933; RV64-NEXT: vrsub.vi v9, v9, 434; RV64-NEXT: vand.vv v8, v8, v935; RV64-NEXT: vredmaxu.vs v8, v8, v836; RV64-NEXT: vmv.x.s a0, v837; RV64-NEXT: li a1, 438; RV64-NEXT: sub a1, a1, a039; RV64-NEXT: zext.b a0, a140; RV64-NEXT: ret41 %res = call i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32> %a, i1 0)42 ret i16 %res43}44 45; ZERO IS POISON46 47define i32 @ctz_v2i1_poison(<2 x i1> %a) {48; RV32-LABEL: ctz_v2i1_poison:49; RV32: # %bb.0:50; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma51; RV32-NEXT: vfirst.m a0, v052; RV32-NEXT: ret53;54; RV64-LABEL: ctz_v2i1_poison:55; RV64: # %bb.0:56; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma57; RV64-NEXT: vfirst.m a0, v058; RV64-NEXT: ret59 %res = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> %a, i1 1)60 ret i32 %res61}62 63