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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -verify-machineinstrs | FileCheck %s -check-prefixes=RV323; RUN: llc < %s -mtriple=riscv64 -verify-machineinstrs | FileCheck %s -check-prefixes=RV644 5; Test case:6; - `A[row]` is loop invariant and should be hoisted up to preheader7; FIXME: RV32 is working as expected, but RV64 doesn't8 9; The following LLVM IR simulates:10; int A[16][16];11; void test(int row, int N) {12; for (int i=0; i<N; ++I) {13; A[row][i+1] = 4;14; A[row][i+2] = 5;15; }16; }17 18; After LSR:19; int A[16][16];20; void test(int row, int N) {21; for (int *ptr = A[row][2]; N>0; N--) {22; *(ptr-1) = 4;23; *(ptr) = 5;24; ++ptr;25; }26; }27 28@A = internal global [16 x [16 x i32]] zeroinitializer, align 32 ; <ptr> [#uses=2]29 30define void @test(i32 signext %row, i32 signext %N.in) nounwind {31; RV32-LABEL: test:32; RV32: # %bb.0: # %entry33; RV32-NEXT: blez a1, .LBB0_334; RV32-NEXT: # %bb.1: # %cond_true.preheader35; RV32-NEXT: slli a2, a0, 636; RV32-NEXT: lui a3, %hi(A)37; RV32-NEXT: addi a3, a3, %lo(A)38; RV32-NEXT: li a0, 439; RV32-NEXT: add a2, a2, a340; RV32-NEXT: addi a2, a2, 841; RV32-NEXT: li a3, 542; RV32-NEXT: .LBB0_2: # %cond_true43; RV32-NEXT: # =>This Inner Loop Header: Depth=144; RV32-NEXT: sw a0, -4(a2)45; RV32-NEXT: sw a3, 0(a2)46; RV32-NEXT: addi a1, a1, -147; RV32-NEXT: addi a2, a2, 448; RV32-NEXT: bnez a1, .LBB0_249; RV32-NEXT: .LBB0_3: # %return50; RV32-NEXT: ret51;52; RV64-LABEL: test:53; RV64: # %bb.0: # %entry54; RV64-NEXT: blez a1, .LBB0_355; RV64-NEXT: # %bb.1: # %cond_true.preheader56; RV64-NEXT: slli a3, a0, 657; RV64-NEXT: lui a4, %hi(A)58; RV64-NEXT: addi a4, a4, %lo(A)59; RV64-NEXT: addiw a1, a1, 260; RV64-NEXT: li a0, 261; RV64-NEXT: li a2, 462; RV64-NEXT: add a3, a3, a463; RV64-NEXT: addi a4, a3, 464; RV64-NEXT: li a5, 565; RV64-NEXT: .LBB0_2: # %cond_true66; RV64-NEXT: # =>This Inner Loop Header: Depth=167; RV64-NEXT: sw a2, 0(a4)68; RV64-NEXT: slli a6, a0, 269; RV64-NEXT: addiw a0, a0, 170; RV64-NEXT: add a6, a3, a671; RV64-NEXT: sw a5, 0(a6)72; RV64-NEXT: addi a4, a4, 473; RV64-NEXT: bne a0, a1, .LBB0_274; RV64-NEXT: .LBB0_3: # %return75; RV64-NEXT: ret76entry:77 %N = bitcast i32 %N.in to i3278 %tmp5 = icmp sgt i32 %N.in, 079 br i1 %tmp5, label %cond_true, label %return80 81cond_true:82 %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ]83 %tmp2 = add i32 %indvar, 184 %tmp = getelementptr [16 x [16 x i32]], ptr @A, i32 0, i32 %row, i32 %tmp285 store i32 4, ptr %tmp86 %tmp5.upgrd.1 = add i32 %indvar, 287 %tmp7 = getelementptr [16 x [16 x i32]], ptr @A, i32 0, i32 %row, i32 %tmp5.upgrd.188 store i32 5, ptr %tmp789 %indvar.next = add i32 %indvar, 190 %exitcond = icmp eq i32 %indvar.next, %N91 br i1 %exitcond, label %return, label %cond_true92 93return:94 ret void95}96