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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \3; RUN: -O1 -riscv-enable-machine-combiner=true \4; RUN: -stop-after machine-combiner < %s | FileCheck %s5 6define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {7 ; CHECK-LABEL: name: test_reassoc_fadd18 ; CHECK: bb.0 (%ir-block.0):9 ; CHECK-NEXT: liveins: $f10_d, $f11_d, $f12_d, $f13_d10 ; CHECK-NEXT: {{ $}}11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f13_d12 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f12_d13 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d14 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $f10_d15 ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FADD_D [[COPY3]], [[COPY2]], 7, implicit $frm16 ; CHECK-NEXT: [[FADD_D1:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FADD_D [[COPY1]], [[COPY]], 7, implicit $frm17 ; CHECK-NEXT: [[FADD_D2:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FADD_D killed [[FADD_D]], killed [[FADD_D1]], 7, implicit $frm18 ; CHECK-NEXT: $f10_d = COPY [[FADD_D2]]19 ; CHECK-NEXT: PseudoRET implicit $f10_d20 %t0 = fadd nsz reassoc double %a0, %a121 %t1 = fadd nsz reassoc double %t0, %a222 %t2 = fadd nsz reassoc double %t1, %a323 ret double %t224}25 26define double @test_reassoc_fmul1(double %a0, double %a1, double %a2, double %a3) {27 ; CHECK-LABEL: name: test_reassoc_fmul128 ; CHECK: bb.0 (%ir-block.0):29 ; CHECK-NEXT: liveins: $f10_d, $f11_d, $f12_d, $f13_d30 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f13_d32 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f12_d33 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d34 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $f10_d35 ; CHECK-NEXT: [[FMUL_D:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FMUL_D [[COPY3]], [[COPY2]], 7, implicit $frm36 ; CHECK-NEXT: [[FMUL_D1:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FMUL_D [[COPY1]], [[COPY]], 7, implicit $frm37 ; CHECK-NEXT: [[FMUL_D2:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FMUL_D killed [[FMUL_D]], killed [[FMUL_D1]], 7, implicit $frm38 ; CHECK-NEXT: $f10_d = COPY [[FMUL_D2]]39 ; CHECK-NEXT: PseudoRET implicit $f10_d40 %t0 = fmul nsz reassoc double %a0, %a141 %t1 = fmul nsz reassoc double %t0, %a242 %t2 = fmul nsz reassoc double %t1, %a343 ret double %t244}45 46; Verify flags intersection47define double @test_reassoc_flags1(double %a0, double %a1, double %a2, double %a3) {48 ; CHECK-LABEL: name: test_reassoc_flags149 ; CHECK: bb.0 (%ir-block.0):50 ; CHECK-NEXT: liveins: $f10_d, $f11_d, $f12_d, $f13_d51 ; CHECK-NEXT: {{ $}}52 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f13_d53 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f12_d54 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d55 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $f10_d56 ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FADD_D [[COPY3]], [[COPY2]], 7, implicit $frm57 ; CHECK-NEXT: [[FADD_D1:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FADD_D [[COPY1]], [[COPY]], 7, implicit $frm58 ; CHECK-NEXT: [[FADD_D2:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FADD_D killed [[FADD_D]], killed [[FADD_D1]], 7, implicit $frm59 ; CHECK-NEXT: $f10_d = COPY [[FADD_D2]]60 ; CHECK-NEXT: PseudoRET implicit $f10_d61 %t0 = fadd nsz reassoc double %a0, %a162 %t1 = fadd contract nsz reassoc double %t0, %a263 %t2 = fadd nsz reassoc double %t1, %a364 ret double %t265}66 67; Verify flags intersection68define double @test_reassoc_flags2(double %a0, double %a1, double %a2, double %a3) {69 ; CHECK-LABEL: name: test_reassoc_flags270 ; CHECK: bb.0 (%ir-block.0):71 ; CHECK-NEXT: liveins: $f10_d, $f11_d, $f12_d, $f13_d72 ; CHECK-NEXT: {{ $}}73 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f13_d74 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f12_d75 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d76 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $f10_d77 ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nsz reassoc nofpexcept FADD_D [[COPY3]], [[COPY2]], 7, implicit $frm78 ; CHECK-NEXT: [[FADD_D1:%[0-9]+]]:fpr64 = nsz contract reassoc nofpexcept FADD_D [[COPY1]], [[COPY]], 7, implicit $frm79 ; CHECK-NEXT: [[FADD_D2:%[0-9]+]]:fpr64 = nsz contract reassoc nofpexcept FADD_D killed [[FADD_D]], killed [[FADD_D1]], 7, implicit $frm80 ; CHECK-NEXT: $f10_d = COPY [[FADD_D2]]81 ; CHECK-NEXT: PseudoRET implicit $f10_d82 %t0 = fadd nsz reassoc double %a0, %a183 %t1 = fadd contract nsz reassoc double %t0, %a284 %t2 = fadd contract nsz reassoc double %t1, %a385 ret double %t286}87 88; Verify FRM89define double @test_fmadd(double %a0, double %a1, double %a2) {90 ; CHECK-LABEL: name: test_fmadd91 ; CHECK: bb.0 (%ir-block.0):92 ; CHECK-NEXT: liveins: $f10_d, $f11_d, $f12_d93 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f12_d95 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d96 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f10_d97 ; CHECK-NEXT: [[FMUL_D:%[0-9]+]]:fpr64 = contract nofpexcept FMUL_D [[COPY2]], [[COPY1]], 7, implicit $frm98 ; CHECK-NEXT: [[FMADD_D:%[0-9]+]]:fpr64 = contract nofpexcept FMADD_D [[COPY2]], [[COPY1]], [[COPY]], 7, implicit $frm99 ; CHECK-NEXT: [[FDIV_D:%[0-9]+]]:fpr64 = nofpexcept FDIV_D killed [[FMADD_D]], [[FMUL_D]], 7, implicit $frm100 ; CHECK-NEXT: $f10_d = COPY [[FDIV_D]]101 ; CHECK-NEXT: PseudoRET implicit $f10_d102 %t0 = fmul contract double %a0, %a1103 %t1 = fadd contract double %t0, %a2104 %t2 = fdiv double %t1, %t0105 ret double %t2106}107 108 109define i64 @test_or_flags(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {110 ; CHECK-LABEL: name: test_or_flags111 ; CHECK: bb.0 (%ir-block.0):112 ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13115 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12116 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11117 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10118 ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY3]], [[COPY2]]119 ; CHECK-NEXT: [[OR1:%[0-9]+]]:gpr = OR [[COPY1]], [[COPY]]120 ; CHECK-NEXT: [[OR2:%[0-9]+]]:gpr = OR killed [[OR]], killed [[OR1]]121 ; CHECK-NEXT: $x10 = COPY [[OR2]]122 ; CHECK-NEXT: PseudoRET implicit $x10123 %t0 = or i64 %a0, %a1124 %t1 = or disjoint i64 %t0, %a2125 %t2 = or disjoint i64 %t1, %a3126 ret i64 %t2127}128 129define i64 @test_add_flags(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {130 ; CHECK-LABEL: name: test_add_flags131 ; CHECK: bb.0 (%ir-block.0):132 ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13135 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12136 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11137 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10138 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY3]], [[COPY2]]139 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY]]140 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD killed [[ADD]], killed [[ADD1]]141 ; CHECK-NEXT: $x10 = COPY [[ADD2]]142 ; CHECK-NEXT: PseudoRET implicit $x10143 %t0 = add i64 %a0, %a1144 %t1 = add nsw i64 %t0, %a2145 %t2 = add nuw i64 %t1, %a3146 ret i64 %t2147}148 149