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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc %s -o - -mtriple=riscv64 -mattr=+f -run-pass=machine-combiner \3# RUN: -verify-machineinstrs | FileCheck %s4 5--- |6 source_filename = "test.ll"7 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"8 target triple = "riscv64"9 10 define void @foo(ptr %0, ptr %1, float %2, float %3, ptr %4, ptr %5) #0 {11 %7 = load float, ptr %0, align 412 %8 = load float, ptr %1, align 413 %9 = fmul fast float %8, %714 %10 = fadd fast float %9, %215 store float %10, ptr %4, align 416 %11 = fsub fast float %3, %917 store float %11, ptr %5, align 418 ret void19 }20 21 attributes #0 = { "target-features"="+f" }22 23...24---25name: foo26alignment: 427tracksRegLiveness: true28registers:29 - { id: 0, class: gpr }30 - { id: 1, class: gpr }31 - { id: 2, class: fpr32 }32 - { id: 3, class: fpr32 }33 - { id: 4, class: gpr }34 - { id: 5, class: gpr }35 - { id: 6, class: fpr32 }36 - { id: 7, class: fpr32 }37 - { id: 8, class: fpr32 }38 - { id: 9, class: fpr32 }39 - { id: 10, class: fpr32 }40liveins:41 - { reg: '$x10', virtual-reg: '%0' }42 - { reg: '$x11', virtual-reg: '%1' }43 - { reg: '$f10_f', virtual-reg: '%2' }44 - { reg: '$f11_f', virtual-reg: '%3' }45 - { reg: '$x12', virtual-reg: '%4' }46 - { reg: '$x13', virtual-reg: '%5' }47frameInfo:48 maxAlignment: 149machineFunctionInfo:50 varArgsFrameIndex: 051 varArgsSaveSize: 052body: |53 bb.0 (%ir-block.6):54 liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x1355 56 ; CHECK-LABEL: name: foo57 ; CHECK: liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x1358 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1360 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1261 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f62 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f63 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x1164 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x1065 ; CHECK-NEXT: [[FLW:%[0-9]+]]:fpr32 = FLW [[COPY5]], 0 :: (load (s32) from %ir.0)66 ; CHECK-NEXT: [[FLW1:%[0-9]+]]:fpr32 = FLW [[COPY4]], 0 :: (load (s32) from %ir.1)67 ; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMADD_S [[FLW1]], [[FLW]], [[COPY3]], 7, implicit $frm68 ; CHECK-NEXT: FSW killed [[FMADD_S]], [[COPY1]], 0 :: (store (s32) into %ir.4)69 ; CHECK-NEXT: [[FNMSUB_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FNMSUB_S [[FLW1]], [[FLW]], [[COPY2]], 7, implicit $frm70 ; CHECK-NEXT: FSW killed [[FNMSUB_S]], [[COPY]], 0 :: (store (s32) into %ir.5)71 ; CHECK-NEXT: PseudoRET72 %5:gpr = COPY $x1373 %4:gpr = COPY $x1274 %3:fpr32 = COPY $f11_f75 %2:fpr32 = COPY $f10_f76 %1:gpr = COPY $x1177 %0:gpr = COPY $x1078 %6:fpr32 = FLW %0, 0 :: (load (s32) from %ir.0)79 %7:fpr32 = FLW %1, 0 :: (load (s32) from %ir.1)80 %8:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMUL_S killed %7, killed %6, 7, implicit $frm81 %9:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADD_S %8, %2, 7, implicit $frm82 FSW killed %9, %4, 0 :: (store (s32) into %ir.4)83 %10:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FSUB_S %3, %8, 7, implicit $frm84 FSW killed %10, %5, 0 :: (store (s32) into %ir.5)85 PseudoRET86 87...88