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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \3# RUN: | FileCheck -check-prefixes=RV32I-MO %s4# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \5# RUN: | FileCheck -check-prefixes=RV64I-MO %s6 7# MIR has been edited by hand to have x5 as live out in @dont_outline8 9---10 11name: outline_012tracksRegLiveness: true13isOutlined: false14body: |15 bb.0:16 liveins: $x10, $x1117 18 ; RV32I-MO-LABEL: name: outline_019 ; RV32I-MO: liveins: $x10, $x1120 ; RV32I-MO-NEXT: {{ $}}21 ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x1122 ; RV32I-MO-NEXT: PseudoRET implicit $x1123 ;24 ; RV64I-MO-LABEL: name: outline_025 ; RV64I-MO: liveins: $x10, $x1126 ; RV64I-MO-NEXT: {{ $}}27 ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x1128 ; RV64I-MO-NEXT: PseudoRET implicit $x1129 $x11 = ORI $x11, 102330 $x12 = ADDI $x10, 1731 $x11 = AND $x12, $x1132 $x10 = SUB $x10, $x1133 PseudoRET implicit $x1134 35...36---37 38name: dont_outline39tracksRegLiveness: true40isOutlined: false41body: |42 ; RV32I-MO-LABEL: name: dont_outline43 ; RV32I-MO: bb.0:44 ; RV32I-MO-NEXT: liveins: $x10, $x1145 ; RV32I-MO-NEXT: {{ $}}46 ; RV32I-MO-NEXT: $x11 = ORI $x11, 102347 ; RV32I-MO-NEXT: $x12 = ADDI $x10, 1748 ; RV32I-MO-NEXT: $x11 = AND $x12, $x1149 ; RV32I-MO-NEXT: $x10 = SUB $x10, $x1150 ; RV32I-MO-NEXT: BEQ $x10, $x11, %bb.151 ; RV32I-MO-NEXT: {{ $}}52 ; RV32I-MO-NEXT: bb.1:53 ; RV32I-MO-NEXT: liveins: $x10, $x554 ; RV32I-MO-NEXT: {{ $}}55 ; RV32I-MO-NEXT: PseudoRET implicit $x10, implicit $x556 ;57 ; RV64I-MO-LABEL: name: dont_outline58 ; RV64I-MO: bb.0:59 ; RV64I-MO-NEXT: liveins: $x10, $x1160 ; RV64I-MO-NEXT: {{ $}}61 ; RV64I-MO-NEXT: $x11 = ORI $x11, 102362 ; RV64I-MO-NEXT: $x12 = ADDI $x10, 1763 ; RV64I-MO-NEXT: $x11 = AND $x12, $x1164 ; RV64I-MO-NEXT: $x10 = SUB $x10, $x1165 ; RV64I-MO-NEXT: BEQ $x10, $x11, %bb.166 ; RV64I-MO-NEXT: {{ $}}67 ; RV64I-MO-NEXT: bb.1:68 ; RV64I-MO-NEXT: liveins: $x10, $x569 ; RV64I-MO-NEXT: {{ $}}70 ; RV64I-MO-NEXT: PseudoRET implicit $x10, implicit $x571 bb.0:72 liveins: $x10, $x1173 74 $x11 = ORI $x11, 102375 $x12 = ADDI $x10, 1776 $x11 = AND $x12, $x1177 $x10 = SUB $x10, $x1178 BEQ $x10, $x11, %bb.179 80 bb.1:81 liveins: $x10, $x582 PseudoRET implicit $x10, implicit $x583 84...85---86 87name: outline_188tracksRegLiveness: true89isOutlined: false90body: |91 bb.0:92 liveins: $x10, $x1193 94 ; RV32I-MO-LABEL: name: outline_195 ; RV32I-MO: liveins: $x10, $x1196 ; RV32I-MO-NEXT: {{ $}}97 ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x1198 ; RV32I-MO-NEXT: PseudoRET implicit $x1099 ;100 ; RV64I-MO-LABEL: name: outline_1101 ; RV64I-MO: liveins: $x10, $x11102 ; RV64I-MO-NEXT: {{ $}}103 ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11104 ; RV64I-MO-NEXT: PseudoRET implicit $x10105 $x11 = ORI $x11, 1023106 $x12 = ADDI $x10, 17107 $x11 = AND $x12, $x11108 $x10 = SUB $x10, $x11109 PseudoRET implicit $x10110 111...112---113name: outline_2114tracksRegLiveness: true115isOutlined: false116body: |117 bb.0:118 liveins: $x10, $x11119 120 ; RV32I-MO-LABEL: name: outline_2121 ; RV32I-MO: liveins: $x10, $x11122 ; RV32I-MO-NEXT: {{ $}}123 ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11124 ; RV32I-MO-NEXT: PseudoRET implicit $x12125 ;126 ; RV64I-MO-LABEL: name: outline_2127 ; RV64I-MO: liveins: $x10, $x11128 ; RV64I-MO-NEXT: {{ $}}129 ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11130 ; RV64I-MO-NEXT: PseudoRET implicit $x12131 $x11 = ORI $x11, 1023132 $x12 = ADDI $x10, 17133 $x11 = AND $x12, $x11134 $x10 = SUB $x10, $x11135 PseudoRET implicit $x12136...137