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1# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \2# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s3# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \4# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s5 6# Combined tests for outlining with CFI instructions on RISC-V:7# 1) All CFIs present in candidate: outline as tail-call and keep CFIs.8# 2) Partial CFIs in function (extra outside candidate): do not outline.9# 3) CFIs present but candidate is not a tail-call: do not outline.10 11--- |12 define void @funcA(i32 %a, i32 %b) nounwind { ret void }13 define void @funcB(i32 %a, i32 %b) nounwind { ret void }14 define void @funcC(i32 %a, i32 %b) nounwind { ret void }15 define void @funcD(i32 %a, i32 %b) nounwind { ret void }16 define void @funcE(i32 %a, i32 %b) nounwind { ret void }17 define void @funcF(i32 %a, i32 %b) nounwind { ret void }18...19 20# Case 1: All CFIs present; expect outlining and CFIs retained in outlined body.21---22name: funcA23tracksRegLiveness: true24body: |25 bb.0:26 liveins: $x10, $x1127 ; RV32I-MO-LABEL: name: funcA28 ; RV32I-MO: liveins: $x10, $x1129 ; RV32I-MO-NEXT: {{ $}}30 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1131 ;32 ; RV64I-MO-LABEL: name: funcA33 ; RV64I-MO: liveins: $x10, $x1134 ; RV64I-MO-NEXT: {{ $}}35 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1136 $x10 = ORI $x10, 102337 CFI_INSTRUCTION offset $x1, 038 $x11 = ORI $x11, 102339 CFI_INSTRUCTION offset $x1, -440 $x12 = ADDI $x10, 1741 CFI_INSTRUCTION offset $x1, -842 $x11 = AND $x12, $x1143 CFI_INSTRUCTION offset $x1, -1244 $x10 = SUB $x10, $x1145 PseudoRET46...47---48name: funcB49tracksRegLiveness: true50body: |51 bb.0:52 liveins: $x10, $x1153 ; RV32I-MO-LABEL: name: funcB54 ; RV32I-MO: liveins: $x10, $x1155 ; RV32I-MO-NEXT: {{ $}}56 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1157 ;58 ; RV64I-MO-LABEL: name: funcB59 ; RV64I-MO: liveins: $x10, $x1160 ; RV64I-MO-NEXT: {{ $}}61 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1162 $x10 = ORI $x10, 102363 CFI_INSTRUCTION offset $x1, 064 $x11 = ORI $x11, 102365 CFI_INSTRUCTION offset $x1, -466 $x12 = ADDI $x10, 1767 CFI_INSTRUCTION offset $x1, -868 $x11 = AND $x12, $x1169 CFI_INSTRUCTION offset $x1, -1270 $x10 = SUB $x10, $x1171 PseudoRET72...73 74# Case 2: Partial CFIs (extra CFI outside candidate in funcD); expect no outlining.75---76name: funcC77tracksRegLiveness: true78body: |79 bb.0:80 liveins: $x10, $x1181 ; RV32I-MO-LABEL: name: funcC82 ; RV32I-MO: liveins: $x10, $x1183 ; RV32I-MO-NEXT: {{ $}}84 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1185 ;86 ; RV64I-MO-LABEL: name: funcC87 ; RV64I-MO: liveins: $x10, $x1188 ; RV64I-MO-NEXT: {{ $}}89 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1190 $x10 = ORI $x10, 102391 CFI_INSTRUCTION offset $x1, 092 $x11 = ORI $x11, 102393 CFI_INSTRUCTION offset $x1, -494 $x12 = ADDI $x10, 1795 CFI_INSTRUCTION offset $x1, -896 $x11 = AND $x12, $x1197 CFI_INSTRUCTION offset $x1, -1298 $x10 = SUB $x10, $x1199 PseudoRET100...101---102name: funcD103tracksRegLiveness: true104body: |105 bb.0:106 liveins: $x10, $x11107 ; RV32I-MO-LABEL: name: funcD108 ; RV32I-MO: liveins: $x10, $x11109 ; RV32I-MO-NEXT: {{ $}}110 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -16111 ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023112 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0113 ; RV32I-MO-NEXT: $x11 = ORI $x11, 1023114 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4115 ; RV32I-MO-NEXT: $x12 = ADDI $x10, 17116 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8117 ; RV32I-MO-NEXT: $x11 = AND $x12, $x11118 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12119 ; RV32I-MO-NEXT: $x10 = SUB $x10, $x11120 ; RV32I-MO-NEXT: PseudoRET121 ;122 ; RV64I-MO-LABEL: name: funcD123 ; RV64I-MO: liveins: $x10, $x11124 ; RV64I-MO-NEXT: {{ $}}125 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -16126 ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023127 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0128 ; RV64I-MO-NEXT: $x11 = ORI $x11, 1023129 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4130 ; RV64I-MO-NEXT: $x12 = ADDI $x10, 17131 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8132 ; RV64I-MO-NEXT: $x11 = AND $x12, $x11133 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12134 ; RV64I-MO-NEXT: $x10 = SUB $x10, $x11135 ; RV64I-MO-NEXT: PseudoRET136 CFI_INSTRUCTION offset $x1, -16137 $x10 = ORI $x10, 1023138 CFI_INSTRUCTION offset $x1, 0139 $x11 = ORI $x11, 1023140 CFI_INSTRUCTION offset $x1, -4141 $x12 = ADDI $x10, 17142 CFI_INSTRUCTION offset $x1, -8143 $x11 = AND $x12, $x11144 CFI_INSTRUCTION offset $x1, -12145 $x10 = SUB $x10, $x11146 PseudoRET147...148 149# Case 3: CFIs present but candidate is not a tail-call; expect no outlining.150---151name: funcE152tracksRegLiveness: true153body: |154 bb.0:155 liveins: $x10, $x11156 ; RV32I-MO-LABEL: name: funcE157 ; RV32I-MO: liveins: $x10, $x11158 ; RV32I-MO-NEXT: {{ $}}159 ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023160 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0161 ; RV32I-MO-NEXT: $x11 = ORI $x11, 1023162 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4163 ; RV32I-MO-NEXT: $x12 = ADDI $x10, 17164 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8165 ; RV32I-MO-NEXT: $x11 = AND $x12, $x11166 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12167 ; RV32I-MO-NEXT: $x10 = SUB $x10, $x11168 ; RV32I-MO-NEXT: $x10 = ADDI $x10, 1169 ; RV32I-MO-NEXT: PseudoRET170 ;171 ; RV64I-MO-LABEL: name: funcE172 ; RV64I-MO: liveins: $x10, $x11173 ; RV64I-MO-NEXT: {{ $}}174 ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023175 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0176 ; RV64I-MO-NEXT: $x11 = ORI $x11, 1023177 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4178 ; RV64I-MO-NEXT: $x12 = ADDI $x10, 17179 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8180 ; RV64I-MO-NEXT: $x11 = AND $x12, $x11181 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12182 ; RV64I-MO-NEXT: $x10 = SUB $x10, $x11183 ; RV64I-MO-NEXT: $x10 = ADDI $x10, 1184 ; RV64I-MO-NEXT: PseudoRET185 $x10 = ORI $x10, 1023186 CFI_INSTRUCTION offset $x1, 0187 $x11 = ORI $x11, 1023188 CFI_INSTRUCTION offset $x1, -4189 $x12 = ADDI $x10, 17190 CFI_INSTRUCTION offset $x1, -8191 $x11 = AND $x12, $x11192 CFI_INSTRUCTION offset $x1, -12193 $x10 = SUB $x10, $x11194 $x10 = ADDI $x10, 1195 PseudoRET196...197---198name: funcF199tracksRegLiveness: true200body: |201 bb.0:202 liveins: $x10, $x11203 ; RV32I-MO-LABEL: name: funcF204 ; RV32I-MO: liveins: $x10, $x11205 ; RV32I-MO-NEXT: {{ $}}206 ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023207 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0208 ; RV32I-MO-NEXT: $x11 = ORI $x11, 1023209 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4210 ; RV32I-MO-NEXT: $x12 = ADDI $x10, 17211 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8212 ; RV32I-MO-NEXT: $x11 = AND $x12, $x11213 ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12214 ; RV32I-MO-NEXT: $x10 = SUB $x10, $x11215 ; RV32I-MO-NEXT: $x10 = ADDI $x10, 2216 ; RV32I-MO-NEXT: PseudoRET217 ;218 ; RV64I-MO-LABEL: name: funcF219 ; RV64I-MO: liveins: $x10, $x11220 ; RV64I-MO-NEXT: {{ $}}221 ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023222 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0223 ; RV64I-MO-NEXT: $x11 = ORI $x11, 1023224 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4225 ; RV64I-MO-NEXT: $x12 = ADDI $x10, 17226 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8227 ; RV64I-MO-NEXT: $x11 = AND $x12, $x11228 ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12229 ; RV64I-MO-NEXT: $x10 = SUB $x10, $x11230 ; RV64I-MO-NEXT: $x10 = ADDI $x10, 2231 ; RV64I-MO-NEXT: PseudoRET232 $x10 = ORI $x10, 1023233 CFI_INSTRUCTION offset $x1, 0234 $x11 = ORI $x11, 1023235 CFI_INSTRUCTION offset $x1, -4236 $x12 = ADDI $x10, 17237 CFI_INSTRUCTION offset $x1, -8238 $x11 = AND $x12, $x11239 CFI_INSTRUCTION offset $x1, -12240 $x10 = SUB $x10, $x11241 $x10 = ADDI $x10, 2242 PseudoRET243...244 245# OUTLINED-LABEL: name: OUTLINED_FUNCTION_0246# OUTLINED: liveins: $x11, $x10247# OUTLINED-NEXT: {{ $}}248# OUTLINED-NEXT: $x10 = ORI $x10, 1023249# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, 0250# OUTLINED-NEXT: $x11 = ORI $x11, 1023251# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -4252# OUTLINED-NEXT: $x12 = ADDI $x10, 17253# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -8254# OUTLINED-NEXT: $x11 = AND $x12, $x11255# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -12256# OUTLINED-NEXT: $x10 = SUB $x10, $x11257# OUTLINED-NEXT: PseudoRET258