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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \3# RUN: | FileCheck -check-prefixes=RV32I-MO %s4# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \5# RUN: | FileCheck -check-prefixes=RV64I-MO %s6 7# Position instructions are illegal to outline. The first instruction won't be outlined8# because position instructions break the sequence.9 10--- |11 define void @func1(i32 %a, i32 %b) { ret void }12 13 define void @func2(i32 %a, i32 %b) { ret void }14 15 define void @func3(i32 %a, i32 %b) { ret void }16...17---18name: func119tracksRegLiveness: true20body: |21 bb.0:22 liveins: $x10, $x1123 ; RV32I-MO-LABEL: name: func124 ; RV32I-MO: liveins: $x10, $x1125 ; RV32I-MO-NEXT: {{ $}}26 ; RV32I-MO-NEXT: $x10 = ORI $x10, 102327 ; RV32I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>28 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1129 ;30 ; RV64I-MO-LABEL: name: func131 ; RV64I-MO: liveins: $x10, $x1132 ; RV64I-MO-NEXT: {{ $}}33 ; RV64I-MO-NEXT: $x10 = ORI $x10, 102334 ; RV64I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>35 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1136 $x10 = ORI $x10, 102337 EH_LABEL <mcsymbol .Ltmp0>38 $x11 = ORI $x11, 102339 $x12 = ADDI $x10, 1740 $x11 = AND $x12, $x1141 $x10 = SUB $x10, $x1142 PseudoRET43...44---45name: func246tracksRegLiveness: true47body: |48 bb.0:49 liveins: $x10, $x1150 ; RV32I-MO-LABEL: name: func251 ; RV32I-MO: liveins: $x10, $x1152 ; RV32I-MO-NEXT: {{ $}}53 ; RV32I-MO-NEXT: $x10 = ORI $x10, 102354 ; RV32I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>55 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1156 ;57 ; RV64I-MO-LABEL: name: func258 ; RV64I-MO: liveins: $x10, $x1159 ; RV64I-MO-NEXT: {{ $}}60 ; RV64I-MO-NEXT: $x10 = ORI $x10, 102361 ; RV64I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>62 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1163 $x10 = ORI $x10, 102364 GC_LABEL <mcsymbol .Ltmp1>65 $x11 = ORI $x11, 102366 $x12 = ADDI $x10, 1767 $x11 = AND $x12, $x1168 $x10 = SUB $x10, $x1169 PseudoRET70...71---72name: func373tracksRegLiveness: true74body: |75 bb.0:76 liveins: $x10, $x1177 ; RV32I-MO-LABEL: name: func378 ; RV32I-MO: liveins: $x10, $x1179 ; RV32I-MO-NEXT: {{ $}}80 ; RV32I-MO-NEXT: $x10 = ORI $x10, 102381 ; RV32I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>82 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1183 ;84 ; RV64I-MO-LABEL: name: func385 ; RV64I-MO: liveins: $x10, $x1186 ; RV64I-MO-NEXT: {{ $}}87 ; RV64I-MO-NEXT: $x10 = ORI $x10, 102388 ; RV64I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>89 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1190 $x10 = ORI $x10, 102391 ANNOTATION_LABEL <mcsymbol .Ltmp2>92 $x11 = ORI $x11, 102393 $x12 = ADDI $x10, 1794 $x11 = AND $x12, $x1195 $x10 = SUB $x10, $x1196 PseudoRET97