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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefixes=RV32I,RV32NOFUSION %s4; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefixes=RV64I,RV64NOFUSION %s6; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \7; RUN: -mattr=+auipc-addi-fusion | FileCheck -check-prefixes=RV32I,RV32FUSION %s8; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \9; RUN: -mattr=+auipc-addi-fusion | FileCheck -check-prefixes=RV64I,RV64FUSION %s10 11; Verifies that MachineLICM can hoist address generation pseudos out of loops.12 13@l = protected global i32 0, align 414 15define void @test_lla(i32 signext %n) {16; RV32I-LABEL: test_lla:17; RV32I: # %bb.0: # %entry18; RV32I-NEXT: li a1, 019; RV32I-NEXT: .Lpcrel_hi0:20; RV32I-NEXT: auipc a2, %pcrel_hi(l)21; RV32I-NEXT: .LBB0_1: # %loop22; RV32I-NEXT: # =>This Inner Loop Header: Depth=123; RV32I-NEXT: lw zero, %pcrel_lo(.Lpcrel_hi0)(a2)24; RV32I-NEXT: addi a1, a1, 125; RV32I-NEXT: blt a1, a0, .LBB0_126; RV32I-NEXT: # %bb.2: # %ret27; RV32I-NEXT: ret28;29; RV64I-LABEL: test_lla:30; RV64I: # %bb.0: # %entry31; RV64I-NEXT: li a1, 032; RV64I-NEXT: .Lpcrel_hi0:33; RV64I-NEXT: auipc a2, %pcrel_hi(l)34; RV64I-NEXT: .LBB0_1: # %loop35; RV64I-NEXT: # =>This Inner Loop Header: Depth=136; RV64I-NEXT: lw zero, %pcrel_lo(.Lpcrel_hi0)(a2)37; RV64I-NEXT: addiw a1, a1, 138; RV64I-NEXT: blt a1, a0, .LBB0_139; RV64I-NEXT: # %bb.2: # %ret40; RV64I-NEXT: ret41entry:42 br label %loop43 44loop:45 %i = phi i32 [ %inc, %loop ], [ 0, %entry ]46 %0 = load volatile i32, ptr @l, align 447 %inc = add nuw nsw i32 %i, 148 %cmp = icmp slt i32 %inc, %n49 br i1 %cmp, label %loop, label %ret50 51ret:52 ret void53}54 55@g = global i32 0, align 456 57define void @test_la(i32 signext %n) {58; RV32I-LABEL: test_la:59; RV32I: # %bb.0: # %entry60; RV32I-NEXT: .Lpcrel_hi1:61; RV32I-NEXT: auipc a1, %got_pcrel_hi(g)62; RV32I-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi1)(a1)63; RV32I-NEXT: li a2, 064; RV32I-NEXT: .LBB1_1: # %loop65; RV32I-NEXT: # =>This Inner Loop Header: Depth=166; RV32I-NEXT: lw zero, 0(a1)67; RV32I-NEXT: addi a2, a2, 168; RV32I-NEXT: blt a2, a0, .LBB1_169; RV32I-NEXT: # %bb.2: # %ret70; RV32I-NEXT: ret71;72; RV64I-LABEL: test_la:73; RV64I: # %bb.0: # %entry74; RV64I-NEXT: .Lpcrel_hi1:75; RV64I-NEXT: auipc a1, %got_pcrel_hi(g)76; RV64I-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)77; RV64I-NEXT: li a2, 078; RV64I-NEXT: .LBB1_1: # %loop79; RV64I-NEXT: # =>This Inner Loop Header: Depth=180; RV64I-NEXT: lw zero, 0(a1)81; RV64I-NEXT: addiw a2, a2, 182; RV64I-NEXT: blt a2, a0, .LBB1_183; RV64I-NEXT: # %bb.2: # %ret84; RV64I-NEXT: ret85entry:86 br label %loop87 88loop:89 %i = phi i32 [ %inc, %loop ], [ 0, %entry ]90 %0 = load volatile i32, ptr @g, align 491 %inc = add nuw nsw i32 %i, 192 %cmp = icmp slt i32 %inc, %n93 br i1 %cmp, label %loop, label %ret94 95ret:96 ret void97}98 99@ie = external thread_local(initialexec) global i32100 101define void @test_la_tls_ie(i32 signext %n) {102; RV32I-LABEL: test_la_tls_ie:103; RV32I: # %bb.0: # %entry104; RV32I-NEXT: li a1, 0105; RV32I-NEXT: .Lpcrel_hi2:106; RV32I-NEXT: auipc a2, %tls_ie_pcrel_hi(ie)107; RV32I-NEXT: lw a2, %pcrel_lo(.Lpcrel_hi2)(a2)108; RV32I-NEXT: add a2, a2, tp109; RV32I-NEXT: .LBB2_1: # %loop110; RV32I-NEXT: # =>This Inner Loop Header: Depth=1111; RV32I-NEXT: lw zero, 0(a2)112; RV32I-NEXT: addi a1, a1, 1113; RV32I-NEXT: blt a1, a0, .LBB2_1114; RV32I-NEXT: # %bb.2: # %ret115; RV32I-NEXT: ret116;117; RV64I-LABEL: test_la_tls_ie:118; RV64I: # %bb.0: # %entry119; RV64I-NEXT: li a1, 0120; RV64I-NEXT: .Lpcrel_hi2:121; RV64I-NEXT: auipc a2, %tls_ie_pcrel_hi(ie)122; RV64I-NEXT: ld a2, %pcrel_lo(.Lpcrel_hi2)(a2)123; RV64I-NEXT: add a2, a2, tp124; RV64I-NEXT: .LBB2_1: # %loop125; RV64I-NEXT: # =>This Inner Loop Header: Depth=1126; RV64I-NEXT: lw zero, 0(a2)127; RV64I-NEXT: addiw a1, a1, 1128; RV64I-NEXT: blt a1, a0, .LBB2_1129; RV64I-NEXT: # %bb.2: # %ret130; RV64I-NEXT: ret131entry:132 br label %loop133 134loop:135 %i = phi i32 [ %inc, %loop ], [ 0, %entry ]136 %0 = load volatile i32, ptr @ie, align 4137 %inc = add nuw nsw i32 %i, 1138 %cmp = icmp slt i32 %inc, %n139 br i1 %cmp, label %loop, label %ret140 141ret:142 ret void143}144 145@gd = external thread_local global i32146 147define void @test_la_tls_gd(i32 signext %n) nounwind {148; RV32I-LABEL: test_la_tls_gd:149; RV32I: # %bb.0: # %entry150; RV32I-NEXT: addi sp, sp, -16151; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill152; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill153; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill154; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill155; RV32I-NEXT: mv s0, a0156; RV32I-NEXT: li s2, 0157; RV32I-NEXT: .Lpcrel_hi3:158; RV32I-NEXT: auipc s1, %tls_gd_pcrel_hi(gd)159; RV32I-NEXT: addi s1, s1, %pcrel_lo(.Lpcrel_hi3)160; RV32I-NEXT: .LBB3_1: # %loop161; RV32I-NEXT: # =>This Inner Loop Header: Depth=1162; RV32I-NEXT: mv a0, s1163; RV32I-NEXT: call __tls_get_addr164; RV32I-NEXT: lw zero, 0(a0)165; RV32I-NEXT: addi s2, s2, 1166; RV32I-NEXT: blt s2, s0, .LBB3_1167; RV32I-NEXT: # %bb.2: # %ret168; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload169; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload170; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload171; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload172; RV32I-NEXT: addi sp, sp, 16173; RV32I-NEXT: ret174;175; RV64I-LABEL: test_la_tls_gd:176; RV64I: # %bb.0: # %entry177; RV64I-NEXT: addi sp, sp, -32178; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill179; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill180; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill181; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill182; RV64I-NEXT: mv s0, a0183; RV64I-NEXT: li s2, 0184; RV64I-NEXT: .Lpcrel_hi3:185; RV64I-NEXT: auipc s1, %tls_gd_pcrel_hi(gd)186; RV64I-NEXT: addi s1, s1, %pcrel_lo(.Lpcrel_hi3)187; RV64I-NEXT: .LBB3_1: # %loop188; RV64I-NEXT: # =>This Inner Loop Header: Depth=1189; RV64I-NEXT: mv a0, s1190; RV64I-NEXT: call __tls_get_addr191; RV64I-NEXT: lw zero, 0(a0)192; RV64I-NEXT: addiw s2, s2, 1193; RV64I-NEXT: blt s2, s0, .LBB3_1194; RV64I-NEXT: # %bb.2: # %ret195; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload196; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload197; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload198; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload199; RV64I-NEXT: addi sp, sp, 32200; RV64I-NEXT: ret201entry:202 br label %loop203 204loop:205 %i = phi i32 [ %inc, %loop ], [ 0, %entry ]206 %0 = load volatile i32, ptr @gd, align 4207 %inc = add nuw nsw i32 %i, 1208 %cmp = icmp slt i32 %inc, %n209 br i1 %cmp, label %loop, label %ret210 211ret:212 ret void213}214;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:215; RV32FUSION: {{.*}}216; RV32NOFUSION: {{.*}}217; RV64FUSION: {{.*}}218; RV64NOFUSION: {{.*}}219