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1# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \2# RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s3# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \4# RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s5 6--- |7 define i32 @outline_0(i32 %a, i32 %b) { ret i32 0 }8 9 define i32 @outline_1(i32 %a, i32 %b) { ret i32 0 }10 11 define i32 @outline_2(i32 %a, i32 %b) { ret i32 0 }12 13 ; Should not outline linkonce_odr functions which could be deduplicated by the14 ; linker.15 define linkonce_odr i32 @dont_outline_0(i32 %a, i32 %b) { ret i32 0 }16 17 ; Should not outline functions with named linker sections18 define i32 @dont_outline_1(i32 %a, i32 %b) section "named" { ret i32 0 }19 20 ; Cannot outline if the X5 (t0) register is not free21 define i32 @dont_outline_2(i32 %a, i32 %b) { ret i32 0 }22 23...24---25name: outline_026tracksRegLiveness: true27isOutlined: false28body: |29 bb.0:30 liveins: $x10, $x1131 ; RV32I-MO-LABEL: name: outline_032 ; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1133 ;34 ; RV64I-MO-LABEL: name: outline_035 ; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1136 $x11 = ORI $x11, 102337 $x12 = ADDI $x10, 1738 $x11 = AND $x12, $x1139 $x10 = SUB $x10, $x1140 PseudoRET implicit $x1041 42...43---44name: outline_145tracksRegLiveness: true46isOutlined: false47body: |48 bb.0:49 liveins: $x10, $x1150 ; RV32I-MO-LABEL: name: outline_151 ; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1152 ;53 ; RV64I-MO-LABEL: name: outline_154 ; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1155 $x11 = ORI $x11, 102356 $x12 = ADDI $x10, 1757 $x11 = AND $x12, $x1158 $x10 = SUB $x10, $x1159 PseudoRET implicit $x1060 61...62---63name: outline_264tracksRegLiveness: true65isOutlined: false66body: |67 bb.0:68 liveins: $x10, $x1169 ; RV32I-MO-LABEL: name: outline_270 ; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1171 ;72 ; RV64I-MO-LABEL: name: outline_273 ; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1174 $x11 = ORI $x11, 102375 $x12 = ADDI $x10, 1776 $x11 = AND $x12, $x1177 $x10 = SUB $x10, $x1178 PseudoRET implicit $x1079 80...81---82name: dont_outline_083tracksRegLiveness: true84isOutlined: false85body: |86 bb.0:87 liveins: $x10, $x1188 ; RV32I-MO-LABEL: name: dont_outline_089 ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_090 ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1191 ;92 ; RV64I-MO-LABEL: name: dont_outline_093 ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_094 ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x1195 $x11 = ORI $x11, 102396 $x12 = ADDI $x10, 1797 $x11 = AND $x12, $x1198 $x10 = SUB $x10, $x1199 PseudoRET implicit $x10100 101...102---103name: dont_outline_1104tracksRegLiveness: true105isOutlined: false106body: |107 bb.0:108 liveins: $x10, $x11109 ; RV32I-MO-LABEL: name: dont_outline_1110 ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0111 ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11112 ;113 ; RV64I-MO-LABEL: name: dont_outline_1114 ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0115 ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11116 $x11 = ORI $x11, 1023117 $x12 = ADDI $x10, 17118 $x11 = AND $x12, $x11119 $x10 = SUB $x10, $x11120 PseudoRET implicit $x10121 122...123---124name: dont_outline_2125tracksRegLiveness: true126isOutlined: false127body: |128 bb.0:129 liveins: $x10, $x11, $x5130 ; RV32I-MO-LABEL: name: dont_outline_2131 ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0132 ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11133 ;134 ; RV64I-MO-LABEL: name: dont_outline_2135 ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0136 ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11137 $x11 = ORI $x11, 1023138 $x12 = ADDI $x10, 17139 $x11 = AND $x12, $x11140 $x10 = SUB $x10, $x11141 $x10 = ADD $x10, $x5142 PseudoRET implicit $x10143 144...145 146# CHECK-LABEL: name: OUTLINED_FUNCTION_0147# CHECK: isOutlined: true148