133 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=RV323; RUN: llc -mtriple=riscv64-none-elf -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=RV644 5define i32 @mask_pair(i32 %x, i32 %y) {6; RV32-LABEL: mask_pair:7; RV32: # %bb.0:8; RV32-NEXT: srl a0, a0, a19; RV32-NEXT: sll a0, a0, a110; RV32-NEXT: ret11;12; RV64-LABEL: mask_pair:13; RV64: # %bb.0:14; RV64-NEXT: srlw a0, a0, a115; RV64-NEXT: sllw a0, a0, a116; RV64-NEXT: ret17 %shl = shl nsw i32 -1, %y18 %and = and i32 %shl, %x19 ret i32 %and20}21 22define i64 @mask_pair_64(i64 %x, i64 %y) {23; RV32-LABEL: mask_pair_64:24; RV32: # %bb.0:25; RV32-NEXT: li a3, -126; RV32-NEXT: addi a4, a2, -3227; RV32-NEXT: sll a3, a3, a228; RV32-NEXT: bltz a4, .LBB1_229; RV32-NEXT: # %bb.1:30; RV32-NEXT: mv a2, a331; RV32-NEXT: j .LBB1_332; RV32-NEXT: .LBB1_2:33; RV32-NEXT: not a2, a234; RV32-NEXT: lui a5, 52428835; RV32-NEXT: addi a5, a5, -136; RV32-NEXT: srl a2, a5, a237; RV32-NEXT: or a2, a3, a238; RV32-NEXT: .LBB1_3:39; RV32-NEXT: srai a4, a4, 3140; RV32-NEXT: and a3, a4, a341; RV32-NEXT: and a1, a2, a142; RV32-NEXT: and a0, a3, a043; RV32-NEXT: ret44;45; RV64-LABEL: mask_pair_64:46; RV64: # %bb.0:47; RV64-NEXT: srl a0, a0, a148; RV64-NEXT: sll a0, a0, a149; RV64-NEXT: ret50 %shl = shl nsw i64 -1, %y51 %and = and i64 %shl, %x52 ret i64 %and53}54 55define i128 @mask_pair_128(i128 %x, i128 %y) {56; RV32-LABEL: mask_pair_128:57; RV32: # %bb.0:58; RV32-NEXT: addi sp, sp, -3259; RV32-NEXT: .cfi_def_cfa_offset 3260; RV32-NEXT: lw a5, 0(a1)61; RV32-NEXT: lw a4, 4(a1)62; RV32-NEXT: lw a3, 8(a1)63; RV32-NEXT: lw a1, 12(a1)64; RV32-NEXT: lw a2, 0(a2)65; RV32-NEXT: li a6, -166; RV32-NEXT: sw zero, 0(sp)67; RV32-NEXT: sw zero, 4(sp)68; RV32-NEXT: sw zero, 8(sp)69; RV32-NEXT: sw zero, 12(sp)70; RV32-NEXT: addi a7, sp, 1671; RV32-NEXT: sw a6, 16(sp)72; RV32-NEXT: sw a6, 20(sp)73; RV32-NEXT: sw a6, 24(sp)74; RV32-NEXT: sw a6, 28(sp)75; RV32-NEXT: srli a6, a2, 376; RV32-NEXT: andi a6, a6, 1277; RV32-NEXT: sub a6, a7, a678; RV32-NEXT: lw a7, 4(a6)79; RV32-NEXT: lw t0, 8(a6)80; RV32-NEXT: lw t1, 12(a6)81; RV32-NEXT: lw a6, 0(a6)82; RV32-NEXT: andi t2, a2, 3183; RV32-NEXT: xori t2, t2, 3184; RV32-NEXT: sll t1, t1, a285; RV32-NEXT: srli t3, t0, 186; RV32-NEXT: sll t0, t0, a287; RV32-NEXT: srli t4, a7, 188; RV32-NEXT: sll a7, a7, a289; RV32-NEXT: sll a2, a6, a290; RV32-NEXT: srli a6, a6, 191; RV32-NEXT: srl t3, t3, t292; RV32-NEXT: srl t4, t4, t293; RV32-NEXT: srl a6, a6, t294; RV32-NEXT: and a2, a2, a595; RV32-NEXT: or a5, t1, t396; RV32-NEXT: or t0, t0, t497; RV32-NEXT: or a6, a7, a698; RV32-NEXT: and a4, a6, a499; RV32-NEXT: and a3, t0, a3100; RV32-NEXT: and a1, a5, a1101; RV32-NEXT: sw a2, 0(a0)102; RV32-NEXT: sw a4, 4(a0)103; RV32-NEXT: sw a3, 8(a0)104; RV32-NEXT: sw a1, 12(a0)105; RV32-NEXT: addi sp, sp, 32106; RV32-NEXT: .cfi_def_cfa_offset 0107; RV32-NEXT: ret108;109; RV64-LABEL: mask_pair_128:110; RV64: # %bb.0:111; RV64-NEXT: li a5, -1112; RV64-NEXT: addi a4, a2, -64113; RV64-NEXT: sll a3, a5, a2114; RV64-NEXT: bltz a4, .LBB2_2115; RV64-NEXT: # %bb.1:116; RV64-NEXT: mv a2, a3117; RV64-NEXT: j .LBB2_3118; RV64-NEXT: .LBB2_2:119; RV64-NEXT: not a2, a2120; RV64-NEXT: srli a5, a5, 1121; RV64-NEXT: srl a2, a5, a2122; RV64-NEXT: or a2, a3, a2123; RV64-NEXT: .LBB2_3:124; RV64-NEXT: srai a4, a4, 63125; RV64-NEXT: and a3, a4, a3126; RV64-NEXT: and a1, a2, a1127; RV64-NEXT: and a0, a3, a0128; RV64-NEXT: ret129 %shl = shl nsw i128 -1, %y130 %and = and i128 %shl, %x131 ret i128 %and132}133