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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=NOZBB,RV32I3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=NOZBB,RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | \5; RUN: FileCheck %s --check-prefixes=ZBB,RV32ZBB6; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | \7; RUN: FileCheck %s --check-prefixes=ZBB,RV64ZBB8; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s | \9; RUN: FileCheck %s --check-prefixes=XQCI10; RUN: llc < %s -mtriple=riscv32 -mattr=+short-forward-branch-ialu | \11; RUN: FileCheck %s --check-prefixes=RV32I-SFB12; RUN: llc < %s -mtriple=riscv64 -mattr=+short-forward-branch-ialu | \13; RUN: FileCheck %s --check-prefixes=RV64I-SFB14 15; Basic tests.16 17define signext i8 @smax_i8(i8 signext %a, i8 signext %b) {18; NOZBB-LABEL: smax_i8:19; NOZBB: # %bb.0:20; NOZBB-NEXT: blt a1, a0, .LBB0_221; NOZBB-NEXT: # %bb.1:22; NOZBB-NEXT: mv a0, a123; NOZBB-NEXT: .LBB0_2:24; NOZBB-NEXT: ret25;26; ZBB-LABEL: smax_i8:27; ZBB: # %bb.0:28; ZBB-NEXT: max a0, a0, a129; ZBB-NEXT: ret30;31; XQCI-LABEL: smax_i8:32; XQCI: # %bb.0:33; XQCI-NEXT: qc.mvge a0, a1, a0, a134; XQCI-NEXT: ret35;36; RV32I-SFB-LABEL: smax_i8:37; RV32I-SFB: # %bb.0:38; RV32I-SFB-NEXT: blt a1, a0, .LBB0_239; RV32I-SFB-NEXT: # %bb.1:40; RV32I-SFB-NEXT: mv a0, a141; RV32I-SFB-NEXT: .LBB0_2:42; RV32I-SFB-NEXT: ret43;44; RV64I-SFB-LABEL: smax_i8:45; RV64I-SFB: # %bb.0:46; RV64I-SFB-NEXT: blt a1, a0, .LBB0_247; RV64I-SFB-NEXT: # %bb.1:48; RV64I-SFB-NEXT: mv a0, a149; RV64I-SFB-NEXT: .LBB0_2:50; RV64I-SFB-NEXT: ret51 %c = call i8 @llvm.smax.i8(i8 %a, i8 %b)52 ret i8 %c53}54 55define signext i16 @smax_i16(i16 signext %a, i16 signext %b) {56; NOZBB-LABEL: smax_i16:57; NOZBB: # %bb.0:58; NOZBB-NEXT: blt a1, a0, .LBB1_259; NOZBB-NEXT: # %bb.1:60; NOZBB-NEXT: mv a0, a161; NOZBB-NEXT: .LBB1_2:62; NOZBB-NEXT: ret63;64; ZBB-LABEL: smax_i16:65; ZBB: # %bb.0:66; ZBB-NEXT: max a0, a0, a167; ZBB-NEXT: ret68;69; XQCI-LABEL: smax_i16:70; XQCI: # %bb.0:71; XQCI-NEXT: qc.mvge a0, a1, a0, a172; XQCI-NEXT: ret73;74; RV32I-SFB-LABEL: smax_i16:75; RV32I-SFB: # %bb.0:76; RV32I-SFB-NEXT: blt a1, a0, .LBB1_277; RV32I-SFB-NEXT: # %bb.1:78; RV32I-SFB-NEXT: mv a0, a179; RV32I-SFB-NEXT: .LBB1_2:80; RV32I-SFB-NEXT: ret81;82; RV64I-SFB-LABEL: smax_i16:83; RV64I-SFB: # %bb.0:84; RV64I-SFB-NEXT: blt a1, a0, .LBB1_285; RV64I-SFB-NEXT: # %bb.1:86; RV64I-SFB-NEXT: mv a0, a187; RV64I-SFB-NEXT: .LBB1_2:88; RV64I-SFB-NEXT: ret89 %c = call i16 @llvm.smax.i16(i16 %a, i16 %b)90 ret i16 %c91}92 93define signext i32 @smax_i32(i32 signext %a, i32 signext %b) {94; NOZBB-LABEL: smax_i32:95; NOZBB: # %bb.0:96; NOZBB-NEXT: blt a1, a0, .LBB2_297; NOZBB-NEXT: # %bb.1:98; NOZBB-NEXT: mv a0, a199; NOZBB-NEXT: .LBB2_2:100; NOZBB-NEXT: ret101;102; ZBB-LABEL: smax_i32:103; ZBB: # %bb.0:104; ZBB-NEXT: max a0, a0, a1105; ZBB-NEXT: ret106;107; XQCI-LABEL: smax_i32:108; XQCI: # %bb.0:109; XQCI-NEXT: qc.mvge a0, a1, a0, a1110; XQCI-NEXT: ret111;112; RV32I-SFB-LABEL: smax_i32:113; RV32I-SFB: # %bb.0:114; RV32I-SFB-NEXT: blt a1, a0, .LBB2_2115; RV32I-SFB-NEXT: # %bb.1:116; RV32I-SFB-NEXT: mv a0, a1117; RV32I-SFB-NEXT: .LBB2_2:118; RV32I-SFB-NEXT: ret119;120; RV64I-SFB-LABEL: smax_i32:121; RV64I-SFB: # %bb.0:122; RV64I-SFB-NEXT: blt a1, a0, .LBB2_2123; RV64I-SFB-NEXT: # %bb.1:124; RV64I-SFB-NEXT: mv a0, a1125; RV64I-SFB-NEXT: .LBB2_2:126; RV64I-SFB-NEXT: ret127 %c = call i32 @llvm.smax.i32(i32 %a, i32 %b)128 ret i32 %c129}130 131define i64 @smax_i64(i64 %a, i64 %b) {132; RV32I-LABEL: smax_i64:133; RV32I: # %bb.0:134; RV32I-NEXT: beq a1, a3, .LBB3_2135; RV32I-NEXT: # %bb.1:136; RV32I-NEXT: slt a4, a3, a1137; RV32I-NEXT: beqz a4, .LBB3_3138; RV32I-NEXT: j .LBB3_4139; RV32I-NEXT: .LBB3_2:140; RV32I-NEXT: sltu a4, a2, a0141; RV32I-NEXT: bnez a4, .LBB3_4142; RV32I-NEXT: .LBB3_3:143; RV32I-NEXT: mv a0, a2144; RV32I-NEXT: mv a1, a3145; RV32I-NEXT: .LBB3_4:146; RV32I-NEXT: ret147;148; RV64I-LABEL: smax_i64:149; RV64I: # %bb.0:150; RV64I-NEXT: blt a1, a0, .LBB3_2151; RV64I-NEXT: # %bb.1:152; RV64I-NEXT: mv a0, a1153; RV64I-NEXT: .LBB3_2:154; RV64I-NEXT: ret155;156; RV32ZBB-LABEL: smax_i64:157; RV32ZBB: # %bb.0:158; RV32ZBB-NEXT: beq a1, a3, .LBB3_2159; RV32ZBB-NEXT: # %bb.1:160; RV32ZBB-NEXT: slt a4, a3, a1161; RV32ZBB-NEXT: beqz a4, .LBB3_3162; RV32ZBB-NEXT: j .LBB3_4163; RV32ZBB-NEXT: .LBB3_2:164; RV32ZBB-NEXT: sltu a4, a2, a0165; RV32ZBB-NEXT: bnez a4, .LBB3_4166; RV32ZBB-NEXT: .LBB3_3:167; RV32ZBB-NEXT: mv a0, a2168; RV32ZBB-NEXT: mv a1, a3169; RV32ZBB-NEXT: .LBB3_4:170; RV32ZBB-NEXT: ret171;172; RV64ZBB-LABEL: smax_i64:173; RV64ZBB: # %bb.0:174; RV64ZBB-NEXT: max a0, a0, a1175; RV64ZBB-NEXT: ret176;177; XQCI-LABEL: smax_i64:178; XQCI: # %bb.0:179; XQCI-NEXT: sltu a4, a2, a0180; XQCI-NEXT: slt a5, a3, a1181; XQCI-NEXT: qc.mveq a5, a1, a3, a4182; XQCI-NEXT: qc.mveqi a0, a5, 0, a2183; XQCI-NEXT: qc.mveqi a1, a5, 0, a3184; XQCI-NEXT: ret185;186; RV32I-SFB-LABEL: smax_i64:187; RV32I-SFB: # %bb.0:188; RV32I-SFB-NEXT: sltu a4, a2, a0189; RV32I-SFB-NEXT: slt a5, a3, a1190; RV32I-SFB-NEXT: bne a1, a3, .LBB3_2191; RV32I-SFB-NEXT: # %bb.1:192; RV32I-SFB-NEXT: mv a5, a4193; RV32I-SFB-NEXT: .LBB3_2:194; RV32I-SFB-NEXT: bnez a5, .LBB3_4195; RV32I-SFB-NEXT: # %bb.3:196; RV32I-SFB-NEXT: mv a0, a2197; RV32I-SFB-NEXT: .LBB3_4:198; RV32I-SFB-NEXT: bnez a5, .LBB3_6199; RV32I-SFB-NEXT: # %bb.5:200; RV32I-SFB-NEXT: mv a1, a3201; RV32I-SFB-NEXT: .LBB3_6:202; RV32I-SFB-NEXT: ret203;204; RV64I-SFB-LABEL: smax_i64:205; RV64I-SFB: # %bb.0:206; RV64I-SFB-NEXT: blt a1, a0, .LBB3_2207; RV64I-SFB-NEXT: # %bb.1:208; RV64I-SFB-NEXT: mv a0, a1209; RV64I-SFB-NEXT: .LBB3_2:210; RV64I-SFB-NEXT: ret211 %c = call i64 @llvm.smax.i64(i64 %a, i64 %b)212 ret i64 %c213}214 215define signext i8 @smin_i8(i8 signext %a, i8 signext %b) {216; NOZBB-LABEL: smin_i8:217; NOZBB: # %bb.0:218; NOZBB-NEXT: blt a0, a1, .LBB4_2219; NOZBB-NEXT: # %bb.1:220; NOZBB-NEXT: mv a0, a1221; NOZBB-NEXT: .LBB4_2:222; NOZBB-NEXT: ret223;224; ZBB-LABEL: smin_i8:225; ZBB: # %bb.0:226; ZBB-NEXT: min a0, a0, a1227; ZBB-NEXT: ret228;229; XQCI-LABEL: smin_i8:230; XQCI: # %bb.0:231; XQCI-NEXT: qc.mvge a0, a0, a1, a1232; XQCI-NEXT: ret233;234; RV32I-SFB-LABEL: smin_i8:235; RV32I-SFB: # %bb.0:236; RV32I-SFB-NEXT: blt a0, a1, .LBB4_2237; RV32I-SFB-NEXT: # %bb.1:238; RV32I-SFB-NEXT: mv a0, a1239; RV32I-SFB-NEXT: .LBB4_2:240; RV32I-SFB-NEXT: ret241;242; RV64I-SFB-LABEL: smin_i8:243; RV64I-SFB: # %bb.0:244; RV64I-SFB-NEXT: blt a0, a1, .LBB4_2245; RV64I-SFB-NEXT: # %bb.1:246; RV64I-SFB-NEXT: mv a0, a1247; RV64I-SFB-NEXT: .LBB4_2:248; RV64I-SFB-NEXT: ret249 %c = call i8 @llvm.smin.i8(i8 %a, i8 %b)250 ret i8 %c251}252 253define signext i16 @smin_i16(i16 signext %a, i16 signext %b) {254; NOZBB-LABEL: smin_i16:255; NOZBB: # %bb.0:256; NOZBB-NEXT: blt a0, a1, .LBB5_2257; NOZBB-NEXT: # %bb.1:258; NOZBB-NEXT: mv a0, a1259; NOZBB-NEXT: .LBB5_2:260; NOZBB-NEXT: ret261;262; ZBB-LABEL: smin_i16:263; ZBB: # %bb.0:264; ZBB-NEXT: min a0, a0, a1265; ZBB-NEXT: ret266;267; XQCI-LABEL: smin_i16:268; XQCI: # %bb.0:269; XQCI-NEXT: qc.mvge a0, a0, a1, a1270; XQCI-NEXT: ret271;272; RV32I-SFB-LABEL: smin_i16:273; RV32I-SFB: # %bb.0:274; RV32I-SFB-NEXT: blt a0, a1, .LBB5_2275; RV32I-SFB-NEXT: # %bb.1:276; RV32I-SFB-NEXT: mv a0, a1277; RV32I-SFB-NEXT: .LBB5_2:278; RV32I-SFB-NEXT: ret279;280; RV64I-SFB-LABEL: smin_i16:281; RV64I-SFB: # %bb.0:282; RV64I-SFB-NEXT: blt a0, a1, .LBB5_2283; RV64I-SFB-NEXT: # %bb.1:284; RV64I-SFB-NEXT: mv a0, a1285; RV64I-SFB-NEXT: .LBB5_2:286; RV64I-SFB-NEXT: ret287 %c = call i16 @llvm.smin.i16(i16 %a, i16 %b)288 ret i16 %c289}290 291define signext i32 @smin_i32(i32 signext %a, i32 signext %b) {292; NOZBB-LABEL: smin_i32:293; NOZBB: # %bb.0:294; NOZBB-NEXT: blt a0, a1, .LBB6_2295; NOZBB-NEXT: # %bb.1:296; NOZBB-NEXT: mv a0, a1297; NOZBB-NEXT: .LBB6_2:298; NOZBB-NEXT: ret299;300; ZBB-LABEL: smin_i32:301; ZBB: # %bb.0:302; ZBB-NEXT: min a0, a0, a1303; ZBB-NEXT: ret304;305; XQCI-LABEL: smin_i32:306; XQCI: # %bb.0:307; XQCI-NEXT: qc.mvge a0, a0, a1, a1308; XQCI-NEXT: ret309;310; RV32I-SFB-LABEL: smin_i32:311; RV32I-SFB: # %bb.0:312; RV32I-SFB-NEXT: blt a0, a1, .LBB6_2313; RV32I-SFB-NEXT: # %bb.1:314; RV32I-SFB-NEXT: mv a0, a1315; RV32I-SFB-NEXT: .LBB6_2:316; RV32I-SFB-NEXT: ret317;318; RV64I-SFB-LABEL: smin_i32:319; RV64I-SFB: # %bb.0:320; RV64I-SFB-NEXT: blt a0, a1, .LBB6_2321; RV64I-SFB-NEXT: # %bb.1:322; RV64I-SFB-NEXT: mv a0, a1323; RV64I-SFB-NEXT: .LBB6_2:324; RV64I-SFB-NEXT: ret325 %c = call i32 @llvm.smin.i32(i32 %a, i32 %b)326 ret i32 %c327}328 329define i64 @smin_i64(i64 %a, i64 %b) {330; RV32I-LABEL: smin_i64:331; RV32I: # %bb.0:332; RV32I-NEXT: beq a1, a3, .LBB7_2333; RV32I-NEXT: # %bb.1:334; RV32I-NEXT: slt a4, a1, a3335; RV32I-NEXT: beqz a4, .LBB7_3336; RV32I-NEXT: j .LBB7_4337; RV32I-NEXT: .LBB7_2:338; RV32I-NEXT: sltu a4, a0, a2339; RV32I-NEXT: bnez a4, .LBB7_4340; RV32I-NEXT: .LBB7_3:341; RV32I-NEXT: mv a0, a2342; RV32I-NEXT: mv a1, a3343; RV32I-NEXT: .LBB7_4:344; RV32I-NEXT: ret345;346; RV64I-LABEL: smin_i64:347; RV64I: # %bb.0:348; RV64I-NEXT: blt a0, a1, .LBB7_2349; RV64I-NEXT: # %bb.1:350; RV64I-NEXT: mv a0, a1351; RV64I-NEXT: .LBB7_2:352; RV64I-NEXT: ret353;354; RV32ZBB-LABEL: smin_i64:355; RV32ZBB: # %bb.0:356; RV32ZBB-NEXT: beq a1, a3, .LBB7_2357; RV32ZBB-NEXT: # %bb.1:358; RV32ZBB-NEXT: slt a4, a1, a3359; RV32ZBB-NEXT: beqz a4, .LBB7_3360; RV32ZBB-NEXT: j .LBB7_4361; RV32ZBB-NEXT: .LBB7_2:362; RV32ZBB-NEXT: sltu a4, a0, a2363; RV32ZBB-NEXT: bnez a4, .LBB7_4364; RV32ZBB-NEXT: .LBB7_3:365; RV32ZBB-NEXT: mv a0, a2366; RV32ZBB-NEXT: mv a1, a3367; RV32ZBB-NEXT: .LBB7_4:368; RV32ZBB-NEXT: ret369;370; RV64ZBB-LABEL: smin_i64:371; RV64ZBB: # %bb.0:372; RV64ZBB-NEXT: min a0, a0, a1373; RV64ZBB-NEXT: ret374;375; XQCI-LABEL: smin_i64:376; XQCI: # %bb.0:377; XQCI-NEXT: sltu a4, a0, a2378; XQCI-NEXT: slt a5, a1, a3379; XQCI-NEXT: qc.mveq a5, a1, a3, a4380; XQCI-NEXT: qc.mveqi a0, a5, 0, a2381; XQCI-NEXT: qc.mveqi a1, a5, 0, a3382; XQCI-NEXT: ret383;384; RV32I-SFB-LABEL: smin_i64:385; RV32I-SFB: # %bb.0:386; RV32I-SFB-NEXT: sltu a4, a0, a2387; RV32I-SFB-NEXT: slt a5, a1, a3388; RV32I-SFB-NEXT: bne a1, a3, .LBB7_2389; RV32I-SFB-NEXT: # %bb.1:390; RV32I-SFB-NEXT: mv a5, a4391; RV32I-SFB-NEXT: .LBB7_2:392; RV32I-SFB-NEXT: bnez a5, .LBB7_4393; RV32I-SFB-NEXT: # %bb.3:394; RV32I-SFB-NEXT: mv a0, a2395; RV32I-SFB-NEXT: .LBB7_4:396; RV32I-SFB-NEXT: bnez a5, .LBB7_6397; RV32I-SFB-NEXT: # %bb.5:398; RV32I-SFB-NEXT: mv a1, a3399; RV32I-SFB-NEXT: .LBB7_6:400; RV32I-SFB-NEXT: ret401;402; RV64I-SFB-LABEL: smin_i64:403; RV64I-SFB: # %bb.0:404; RV64I-SFB-NEXT: blt a0, a1, .LBB7_2405; RV64I-SFB-NEXT: # %bb.1:406; RV64I-SFB-NEXT: mv a0, a1407; RV64I-SFB-NEXT: .LBB7_2:408; RV64I-SFB-NEXT: ret409 %c = call i64 @llvm.smin.i64(i64 %a, i64 %b)410 ret i64 %c411}412 413define i8 @umax_i8(i8 zeroext %a, i8 zeroext %b) {414; NOZBB-LABEL: umax_i8:415; NOZBB: # %bb.0:416; NOZBB-NEXT: bltu a1, a0, .LBB8_2417; NOZBB-NEXT: # %bb.1:418; NOZBB-NEXT: mv a0, a1419; NOZBB-NEXT: .LBB8_2:420; NOZBB-NEXT: ret421;422; ZBB-LABEL: umax_i8:423; ZBB: # %bb.0:424; ZBB-NEXT: maxu a0, a0, a1425; ZBB-NEXT: ret426;427; XQCI-LABEL: umax_i8:428; XQCI: # %bb.0:429; XQCI-NEXT: qc.mvgeu a0, a1, a0, a1430; XQCI-NEXT: ret431;432; RV32I-SFB-LABEL: umax_i8:433; RV32I-SFB: # %bb.0:434; RV32I-SFB-NEXT: bltu a1, a0, .LBB8_2435; RV32I-SFB-NEXT: # %bb.1:436; RV32I-SFB-NEXT: mv a0, a1437; RV32I-SFB-NEXT: .LBB8_2:438; RV32I-SFB-NEXT: ret439;440; RV64I-SFB-LABEL: umax_i8:441; RV64I-SFB: # %bb.0:442; RV64I-SFB-NEXT: bltu a1, a0, .LBB8_2443; RV64I-SFB-NEXT: # %bb.1:444; RV64I-SFB-NEXT: mv a0, a1445; RV64I-SFB-NEXT: .LBB8_2:446; RV64I-SFB-NEXT: ret447 %c = call i8 @llvm.umax.i8(i8 %a, i8 %b)448 ret i8 %c449}450 451define i16 @umax_i16(i16 zeroext %a, i16 zeroext %b) {452; NOZBB-LABEL: umax_i16:453; NOZBB: # %bb.0:454; NOZBB-NEXT: bltu a1, a0, .LBB9_2455; NOZBB-NEXT: # %bb.1:456; NOZBB-NEXT: mv a0, a1457; NOZBB-NEXT: .LBB9_2:458; NOZBB-NEXT: ret459;460; ZBB-LABEL: umax_i16:461; ZBB: # %bb.0:462; ZBB-NEXT: maxu a0, a0, a1463; ZBB-NEXT: ret464;465; XQCI-LABEL: umax_i16:466; XQCI: # %bb.0:467; XQCI-NEXT: qc.mvgeu a0, a1, a0, a1468; XQCI-NEXT: ret469;470; RV32I-SFB-LABEL: umax_i16:471; RV32I-SFB: # %bb.0:472; RV32I-SFB-NEXT: bltu a1, a0, .LBB9_2473; RV32I-SFB-NEXT: # %bb.1:474; RV32I-SFB-NEXT: mv a0, a1475; RV32I-SFB-NEXT: .LBB9_2:476; RV32I-SFB-NEXT: ret477;478; RV64I-SFB-LABEL: umax_i16:479; RV64I-SFB: # %bb.0:480; RV64I-SFB-NEXT: bltu a1, a0, .LBB9_2481; RV64I-SFB-NEXT: # %bb.1:482; RV64I-SFB-NEXT: mv a0, a1483; RV64I-SFB-NEXT: .LBB9_2:484; RV64I-SFB-NEXT: ret485 %c = call i16 @llvm.umax.i16(i16 %a, i16 %b)486 ret i16 %c487}488 489define signext i32 @umax_i32(i32 signext %a, i32 signext %b) {490; NOZBB-LABEL: umax_i32:491; NOZBB: # %bb.0:492; NOZBB-NEXT: bltu a1, a0, .LBB10_2493; NOZBB-NEXT: # %bb.1:494; NOZBB-NEXT: mv a0, a1495; NOZBB-NEXT: .LBB10_2:496; NOZBB-NEXT: ret497;498; ZBB-LABEL: umax_i32:499; ZBB: # %bb.0:500; ZBB-NEXT: maxu a0, a0, a1501; ZBB-NEXT: ret502;503; XQCI-LABEL: umax_i32:504; XQCI: # %bb.0:505; XQCI-NEXT: qc.mvgeu a0, a1, a0, a1506; XQCI-NEXT: ret507;508; RV32I-SFB-LABEL: umax_i32:509; RV32I-SFB: # %bb.0:510; RV32I-SFB-NEXT: bltu a1, a0, .LBB10_2511; RV32I-SFB-NEXT: # %bb.1:512; RV32I-SFB-NEXT: mv a0, a1513; RV32I-SFB-NEXT: .LBB10_2:514; RV32I-SFB-NEXT: ret515;516; RV64I-SFB-LABEL: umax_i32:517; RV64I-SFB: # %bb.0:518; RV64I-SFB-NEXT: bltu a1, a0, .LBB10_2519; RV64I-SFB-NEXT: # %bb.1:520; RV64I-SFB-NEXT: mv a0, a1521; RV64I-SFB-NEXT: .LBB10_2:522; RV64I-SFB-NEXT: ret523 %c = call i32 @llvm.umax.i32(i32 %a, i32 %b)524 ret i32 %c525}526 527define i64 @umax_i64(i64 %a, i64 %b) {528; RV32I-LABEL: umax_i64:529; RV32I: # %bb.0:530; RV32I-NEXT: beq a1, a3, .LBB11_2531; RV32I-NEXT: # %bb.1:532; RV32I-NEXT: sltu a4, a3, a1533; RV32I-NEXT: beqz a4, .LBB11_3534; RV32I-NEXT: j .LBB11_4535; RV32I-NEXT: .LBB11_2:536; RV32I-NEXT: sltu a4, a2, a0537; RV32I-NEXT: bnez a4, .LBB11_4538; RV32I-NEXT: .LBB11_3:539; RV32I-NEXT: mv a0, a2540; RV32I-NEXT: mv a1, a3541; RV32I-NEXT: .LBB11_4:542; RV32I-NEXT: ret543;544; RV64I-LABEL: umax_i64:545; RV64I: # %bb.0:546; RV64I-NEXT: bltu a1, a0, .LBB11_2547; RV64I-NEXT: # %bb.1:548; RV64I-NEXT: mv a0, a1549; RV64I-NEXT: .LBB11_2:550; RV64I-NEXT: ret551;552; RV32ZBB-LABEL: umax_i64:553; RV32ZBB: # %bb.0:554; RV32ZBB-NEXT: beq a1, a3, .LBB11_2555; RV32ZBB-NEXT: # %bb.1:556; RV32ZBB-NEXT: sltu a4, a3, a1557; RV32ZBB-NEXT: beqz a4, .LBB11_3558; RV32ZBB-NEXT: j .LBB11_4559; RV32ZBB-NEXT: .LBB11_2:560; RV32ZBB-NEXT: sltu a4, a2, a0561; RV32ZBB-NEXT: bnez a4, .LBB11_4562; RV32ZBB-NEXT: .LBB11_3:563; RV32ZBB-NEXT: mv a0, a2564; RV32ZBB-NEXT: mv a1, a3565; RV32ZBB-NEXT: .LBB11_4:566; RV32ZBB-NEXT: ret567;568; RV64ZBB-LABEL: umax_i64:569; RV64ZBB: # %bb.0:570; RV64ZBB-NEXT: maxu a0, a0, a1571; RV64ZBB-NEXT: ret572;573; XQCI-LABEL: umax_i64:574; XQCI: # %bb.0:575; XQCI-NEXT: sltu a4, a2, a0576; XQCI-NEXT: sltu a5, a3, a1577; XQCI-NEXT: qc.mveq a5, a1, a3, a4578; XQCI-NEXT: qc.mveqi a0, a5, 0, a2579; XQCI-NEXT: qc.mveqi a1, a5, 0, a3580; XQCI-NEXT: ret581;582; RV32I-SFB-LABEL: umax_i64:583; RV32I-SFB: # %bb.0:584; RV32I-SFB-NEXT: sltu a4, a2, a0585; RV32I-SFB-NEXT: sltu a5, a3, a1586; RV32I-SFB-NEXT: bne a1, a3, .LBB11_2587; RV32I-SFB-NEXT: # %bb.1:588; RV32I-SFB-NEXT: mv a5, a4589; RV32I-SFB-NEXT: .LBB11_2:590; RV32I-SFB-NEXT: bnez a5, .LBB11_4591; RV32I-SFB-NEXT: # %bb.3:592; RV32I-SFB-NEXT: mv a0, a2593; RV32I-SFB-NEXT: .LBB11_4:594; RV32I-SFB-NEXT: bnez a5, .LBB11_6595; RV32I-SFB-NEXT: # %bb.5:596; RV32I-SFB-NEXT: mv a1, a3597; RV32I-SFB-NEXT: .LBB11_6:598; RV32I-SFB-NEXT: ret599;600; RV64I-SFB-LABEL: umax_i64:601; RV64I-SFB: # %bb.0:602; RV64I-SFB-NEXT: bltu a1, a0, .LBB11_2603; RV64I-SFB-NEXT: # %bb.1:604; RV64I-SFB-NEXT: mv a0, a1605; RV64I-SFB-NEXT: .LBB11_2:606; RV64I-SFB-NEXT: ret607 %c = call i64 @llvm.umax.i64(i64 %a, i64 %b)608 ret i64 %c609}610 611define zeroext i8 @umin_i8(i8 zeroext %a, i8 zeroext %b) {612; NOZBB-LABEL: umin_i8:613; NOZBB: # %bb.0:614; NOZBB-NEXT: bltu a0, a1, .LBB12_2615; NOZBB-NEXT: # %bb.1:616; NOZBB-NEXT: mv a0, a1617; NOZBB-NEXT: .LBB12_2:618; NOZBB-NEXT: ret619;620; ZBB-LABEL: umin_i8:621; ZBB: # %bb.0:622; ZBB-NEXT: minu a0, a0, a1623; ZBB-NEXT: ret624;625; XQCI-LABEL: umin_i8:626; XQCI: # %bb.0:627; XQCI-NEXT: qc.mvgeu a0, a0, a1, a1628; XQCI-NEXT: ret629;630; RV32I-SFB-LABEL: umin_i8:631; RV32I-SFB: # %bb.0:632; RV32I-SFB-NEXT: bltu a0, a1, .LBB12_2633; RV32I-SFB-NEXT: # %bb.1:634; RV32I-SFB-NEXT: mv a0, a1635; RV32I-SFB-NEXT: .LBB12_2:636; RV32I-SFB-NEXT: ret637;638; RV64I-SFB-LABEL: umin_i8:639; RV64I-SFB: # %bb.0:640; RV64I-SFB-NEXT: bltu a0, a1, .LBB12_2641; RV64I-SFB-NEXT: # %bb.1:642; RV64I-SFB-NEXT: mv a0, a1643; RV64I-SFB-NEXT: .LBB12_2:644; RV64I-SFB-NEXT: ret645 %c = call i8 @llvm.umin.i8(i8 %a, i8 %b)646 ret i8 %c647}648 649define zeroext i16 @umin_i16(i16 zeroext %a, i16 zeroext %b) {650; NOZBB-LABEL: umin_i16:651; NOZBB: # %bb.0:652; NOZBB-NEXT: bltu a0, a1, .LBB13_2653; NOZBB-NEXT: # %bb.1:654; NOZBB-NEXT: mv a0, a1655; NOZBB-NEXT: .LBB13_2:656; NOZBB-NEXT: ret657;658; ZBB-LABEL: umin_i16:659; ZBB: # %bb.0:660; ZBB-NEXT: minu a0, a0, a1661; ZBB-NEXT: ret662;663; XQCI-LABEL: umin_i16:664; XQCI: # %bb.0:665; XQCI-NEXT: qc.mvgeu a0, a0, a1, a1666; XQCI-NEXT: ret667;668; RV32I-SFB-LABEL: umin_i16:669; RV32I-SFB: # %bb.0:670; RV32I-SFB-NEXT: bltu a0, a1, .LBB13_2671; RV32I-SFB-NEXT: # %bb.1:672; RV32I-SFB-NEXT: mv a0, a1673; RV32I-SFB-NEXT: .LBB13_2:674; RV32I-SFB-NEXT: ret675;676; RV64I-SFB-LABEL: umin_i16:677; RV64I-SFB: # %bb.0:678; RV64I-SFB-NEXT: bltu a0, a1, .LBB13_2679; RV64I-SFB-NEXT: # %bb.1:680; RV64I-SFB-NEXT: mv a0, a1681; RV64I-SFB-NEXT: .LBB13_2:682; RV64I-SFB-NEXT: ret683 %c = call i16 @llvm.umin.i16(i16 %a, i16 %b)684 ret i16 %c685}686 687define signext i32 @umin_i32(i32 signext %a, i32 signext %b) {688; NOZBB-LABEL: umin_i32:689; NOZBB: # %bb.0:690; NOZBB-NEXT: bltu a0, a1, .LBB14_2691; NOZBB-NEXT: # %bb.1:692; NOZBB-NEXT: mv a0, a1693; NOZBB-NEXT: .LBB14_2:694; NOZBB-NEXT: ret695;696; ZBB-LABEL: umin_i32:697; ZBB: # %bb.0:698; ZBB-NEXT: minu a0, a0, a1699; ZBB-NEXT: ret700;701; XQCI-LABEL: umin_i32:702; XQCI: # %bb.0:703; XQCI-NEXT: qc.mvgeu a0, a0, a1, a1704; XQCI-NEXT: ret705;706; RV32I-SFB-LABEL: umin_i32:707; RV32I-SFB: # %bb.0:708; RV32I-SFB-NEXT: bltu a0, a1, .LBB14_2709; RV32I-SFB-NEXT: # %bb.1:710; RV32I-SFB-NEXT: mv a0, a1711; RV32I-SFB-NEXT: .LBB14_2:712; RV32I-SFB-NEXT: ret713;714; RV64I-SFB-LABEL: umin_i32:715; RV64I-SFB: # %bb.0:716; RV64I-SFB-NEXT: bltu a0, a1, .LBB14_2717; RV64I-SFB-NEXT: # %bb.1:718; RV64I-SFB-NEXT: mv a0, a1719; RV64I-SFB-NEXT: .LBB14_2:720; RV64I-SFB-NEXT: ret721 %c = call i32 @llvm.umin.i32(i32 %a, i32 %b)722 ret i32 %c723}724 725define i64 @umin_i64(i64 %a, i64 %b) {726; RV32I-LABEL: umin_i64:727; RV32I: # %bb.0:728; RV32I-NEXT: beq a1, a3, .LBB15_2729; RV32I-NEXT: # %bb.1:730; RV32I-NEXT: sltu a4, a1, a3731; RV32I-NEXT: beqz a4, .LBB15_3732; RV32I-NEXT: j .LBB15_4733; RV32I-NEXT: .LBB15_2:734; RV32I-NEXT: sltu a4, a0, a2735; RV32I-NEXT: bnez a4, .LBB15_4736; RV32I-NEXT: .LBB15_3:737; RV32I-NEXT: mv a0, a2738; RV32I-NEXT: mv a1, a3739; RV32I-NEXT: .LBB15_4:740; RV32I-NEXT: ret741;742; RV64I-LABEL: umin_i64:743; RV64I: # %bb.0:744; RV64I-NEXT: bltu a0, a1, .LBB15_2745; RV64I-NEXT: # %bb.1:746; RV64I-NEXT: mv a0, a1747; RV64I-NEXT: .LBB15_2:748; RV64I-NEXT: ret749;750; RV32ZBB-LABEL: umin_i64:751; RV32ZBB: # %bb.0:752; RV32ZBB-NEXT: beq a1, a3, .LBB15_2753; RV32ZBB-NEXT: # %bb.1:754; RV32ZBB-NEXT: sltu a4, a1, a3755; RV32ZBB-NEXT: beqz a4, .LBB15_3756; RV32ZBB-NEXT: j .LBB15_4757; RV32ZBB-NEXT: .LBB15_2:758; RV32ZBB-NEXT: sltu a4, a0, a2759; RV32ZBB-NEXT: bnez a4, .LBB15_4760; RV32ZBB-NEXT: .LBB15_3:761; RV32ZBB-NEXT: mv a0, a2762; RV32ZBB-NEXT: mv a1, a3763; RV32ZBB-NEXT: .LBB15_4:764; RV32ZBB-NEXT: ret765;766; RV64ZBB-LABEL: umin_i64:767; RV64ZBB: # %bb.0:768; RV64ZBB-NEXT: minu a0, a0, a1769; RV64ZBB-NEXT: ret770;771; XQCI-LABEL: umin_i64:772; XQCI: # %bb.0:773; XQCI-NEXT: sltu a4, a0, a2774; XQCI-NEXT: sltu a5, a1, a3775; XQCI-NEXT: qc.mveq a5, a1, a3, a4776; XQCI-NEXT: qc.mveqi a0, a5, 0, a2777; XQCI-NEXT: qc.mveqi a1, a5, 0, a3778; XQCI-NEXT: ret779;780; RV32I-SFB-LABEL: umin_i64:781; RV32I-SFB: # %bb.0:782; RV32I-SFB-NEXT: sltu a4, a0, a2783; RV32I-SFB-NEXT: sltu a5, a1, a3784; RV32I-SFB-NEXT: bne a1, a3, .LBB15_2785; RV32I-SFB-NEXT: # %bb.1:786; RV32I-SFB-NEXT: mv a5, a4787; RV32I-SFB-NEXT: .LBB15_2:788; RV32I-SFB-NEXT: bnez a5, .LBB15_4789; RV32I-SFB-NEXT: # %bb.3:790; RV32I-SFB-NEXT: mv a0, a2791; RV32I-SFB-NEXT: .LBB15_4:792; RV32I-SFB-NEXT: bnez a5, .LBB15_6793; RV32I-SFB-NEXT: # %bb.5:794; RV32I-SFB-NEXT: mv a1, a3795; RV32I-SFB-NEXT: .LBB15_6:796; RV32I-SFB-NEXT: ret797;798; RV64I-SFB-LABEL: umin_i64:799; RV64I-SFB: # %bb.0:800; RV64I-SFB-NEXT: bltu a0, a1, .LBB15_2801; RV64I-SFB-NEXT: # %bb.1:802; RV64I-SFB-NEXT: mv a0, a1803; RV64I-SFB-NEXT: .LBB15_2:804; RV64I-SFB-NEXT: ret805 %c = call i64 @llvm.umin.i64(i64 %a, i64 %b)806 ret i64 %c807}808 809; Tests with the same operand used twice. These should fold away.810 811define signext i32 @smin_same_op_i32(i32 signext %a) {812; NOZBB-LABEL: smin_same_op_i32:813; NOZBB: # %bb.0:814; NOZBB-NEXT: ret815;816; ZBB-LABEL: smin_same_op_i32:817; ZBB: # %bb.0:818; ZBB-NEXT: ret819;820; XQCI-LABEL: smin_same_op_i32:821; XQCI: # %bb.0:822; XQCI-NEXT: ret823;824; RV32I-SFB-LABEL: smin_same_op_i32:825; RV32I-SFB: # %bb.0:826; RV32I-SFB-NEXT: ret827;828; RV64I-SFB-LABEL: smin_same_op_i32:829; RV64I-SFB: # %bb.0:830; RV64I-SFB-NEXT: ret831 %c = call i32 @llvm.smin.i32(i32 %a, i32 %a)832 ret i32 %c833}834 835define signext i32 @smax_same_op_i32(i32 signext %a) {836; NOZBB-LABEL: smax_same_op_i32:837; NOZBB: # %bb.0:838; NOZBB-NEXT: ret839;840; ZBB-LABEL: smax_same_op_i32:841; ZBB: # %bb.0:842; ZBB-NEXT: ret843;844; XQCI-LABEL: smax_same_op_i32:845; XQCI: # %bb.0:846; XQCI-NEXT: ret847;848; RV32I-SFB-LABEL: smax_same_op_i32:849; RV32I-SFB: # %bb.0:850; RV32I-SFB-NEXT: ret851;852; RV64I-SFB-LABEL: smax_same_op_i32:853; RV64I-SFB: # %bb.0:854; RV64I-SFB-NEXT: ret855 %c = call i32 @llvm.smax.i32(i32 %a, i32 %a)856 ret i32 %c857}858 859define signext i32 @umin_same_op_i32(i32 signext %a) {860; NOZBB-LABEL: umin_same_op_i32:861; NOZBB: # %bb.0:862; NOZBB-NEXT: ret863;864; ZBB-LABEL: umin_same_op_i32:865; ZBB: # %bb.0:866; ZBB-NEXT: ret867;868; XQCI-LABEL: umin_same_op_i32:869; XQCI: # %bb.0:870; XQCI-NEXT: ret871;872; RV32I-SFB-LABEL: umin_same_op_i32:873; RV32I-SFB: # %bb.0:874; RV32I-SFB-NEXT: ret875;876; RV64I-SFB-LABEL: umin_same_op_i32:877; RV64I-SFB: # %bb.0:878; RV64I-SFB-NEXT: ret879 %c = call i32 @llvm.umin.i32(i32 %a, i32 %a)880 ret i32 %c881}882 883define signext i32 @umax_same_op_i32(i32 signext %a) {884; NOZBB-LABEL: umax_same_op_i32:885; NOZBB: # %bb.0:886; NOZBB-NEXT: ret887;888; ZBB-LABEL: umax_same_op_i32:889; ZBB: # %bb.0:890; ZBB-NEXT: ret891;892; XQCI-LABEL: umax_same_op_i32:893; XQCI: # %bb.0:894; XQCI-NEXT: ret895;896; RV32I-SFB-LABEL: umax_same_op_i32:897; RV32I-SFB: # %bb.0:898; RV32I-SFB-NEXT: ret899;900; RV64I-SFB-LABEL: umax_same_op_i32:901; RV64I-SFB: # %bb.0:902; RV64I-SFB-NEXT: ret903 %c = call i32 @llvm.umax.i32(i32 %a, i32 %a)904 ret i32 %c905}906 907; Tests with undef operands. These should fold to undef for RV32 or 0 for RV64.908 909define signext i32 @smin_undef_i32() {910; RV32I-LABEL: smin_undef_i32:911; RV32I: # %bb.0:912; RV32I-NEXT: ret913;914; RV64I-LABEL: smin_undef_i32:915; RV64I: # %bb.0:916; RV64I-NEXT: li a0, 0917; RV64I-NEXT: ret918;919; RV32ZBB-LABEL: smin_undef_i32:920; RV32ZBB: # %bb.0:921; RV32ZBB-NEXT: ret922;923; RV64ZBB-LABEL: smin_undef_i32:924; RV64ZBB: # %bb.0:925; RV64ZBB-NEXT: li a0, 0926; RV64ZBB-NEXT: ret927;928; XQCI-LABEL: smin_undef_i32:929; XQCI: # %bb.0:930; XQCI-NEXT: ret931;932; RV32I-SFB-LABEL: smin_undef_i32:933; RV32I-SFB: # %bb.0:934; RV32I-SFB-NEXT: ret935;936; RV64I-SFB-LABEL: smin_undef_i32:937; RV64I-SFB: # %bb.0:938; RV64I-SFB-NEXT: li a0, 0939; RV64I-SFB-NEXT: ret940 %c = call i32 @llvm.smin.i32(i32 undef, i32 undef)941 ret i32 %c942}943 944define signext i32 @smax_undef_i32() {945; RV32I-LABEL: smax_undef_i32:946; RV32I: # %bb.0:947; RV32I-NEXT: ret948;949; RV64I-LABEL: smax_undef_i32:950; RV64I: # %bb.0:951; RV64I-NEXT: li a0, 0952; RV64I-NEXT: ret953;954; RV32ZBB-LABEL: smax_undef_i32:955; RV32ZBB: # %bb.0:956; RV32ZBB-NEXT: ret957;958; RV64ZBB-LABEL: smax_undef_i32:959; RV64ZBB: # %bb.0:960; RV64ZBB-NEXT: li a0, 0961; RV64ZBB-NEXT: ret962;963; XQCI-LABEL: smax_undef_i32:964; XQCI: # %bb.0:965; XQCI-NEXT: ret966;967; RV32I-SFB-LABEL: smax_undef_i32:968; RV32I-SFB: # %bb.0:969; RV32I-SFB-NEXT: ret970;971; RV64I-SFB-LABEL: smax_undef_i32:972; RV64I-SFB: # %bb.0:973; RV64I-SFB-NEXT: li a0, 0974; RV64I-SFB-NEXT: ret975 %c = call i32 @llvm.smax.i32(i32 undef, i32 undef)976 ret i32 %c977}978 979define signext i32 @umin_undef_i32() {980; RV32I-LABEL: umin_undef_i32:981; RV32I: # %bb.0:982; RV32I-NEXT: ret983;984; RV64I-LABEL: umin_undef_i32:985; RV64I: # %bb.0:986; RV64I-NEXT: li a0, 0987; RV64I-NEXT: ret988;989; RV32ZBB-LABEL: umin_undef_i32:990; RV32ZBB: # %bb.0:991; RV32ZBB-NEXT: ret992;993; RV64ZBB-LABEL: umin_undef_i32:994; RV64ZBB: # %bb.0:995; RV64ZBB-NEXT: li a0, 0996; RV64ZBB-NEXT: ret997;998; XQCI-LABEL: umin_undef_i32:999; XQCI: # %bb.0:1000; XQCI-NEXT: ret1001;1002; RV32I-SFB-LABEL: umin_undef_i32:1003; RV32I-SFB: # %bb.0:1004; RV32I-SFB-NEXT: ret1005;1006; RV64I-SFB-LABEL: umin_undef_i32:1007; RV64I-SFB: # %bb.0:1008; RV64I-SFB-NEXT: li a0, 01009; RV64I-SFB-NEXT: ret1010 %c = call i32 @llvm.umin.i32(i32 undef, i32 undef)1011 ret i32 %c1012}1013 1014define signext i32 @umax_undef_i32() {1015; RV32I-LABEL: umax_undef_i32:1016; RV32I: # %bb.0:1017; RV32I-NEXT: ret1018;1019; RV64I-LABEL: umax_undef_i32:1020; RV64I: # %bb.0:1021; RV64I-NEXT: li a0, 01022; RV64I-NEXT: ret1023;1024; RV32ZBB-LABEL: umax_undef_i32:1025; RV32ZBB: # %bb.0:1026; RV32ZBB-NEXT: ret1027;1028; RV64ZBB-LABEL: umax_undef_i32:1029; RV64ZBB: # %bb.0:1030; RV64ZBB-NEXT: li a0, 01031; RV64ZBB-NEXT: ret1032;1033; XQCI-LABEL: umax_undef_i32:1034; XQCI: # %bb.0:1035; XQCI-NEXT: ret1036;1037; RV32I-SFB-LABEL: umax_undef_i32:1038; RV32I-SFB: # %bb.0:1039; RV32I-SFB-NEXT: ret1040;1041; RV64I-SFB-LABEL: umax_undef_i32:1042; RV64I-SFB: # %bb.0:1043; RV64I-SFB-NEXT: li a0, 01044; RV64I-SFB-NEXT: ret1045 %c = call i32 @llvm.umax.i32(i32 undef, i32 undef)1046 ret i32 %c1047}1048 1049define signext i32 @smax_i32_pos_constant(i32 signext %a) {1050; NOZBB-LABEL: smax_i32_pos_constant:1051; NOZBB: # %bb.0:1052; NOZBB-NEXT: li a1, 101053; NOZBB-NEXT: blt a1, a0, .LBB24_21054; NOZBB-NEXT: # %bb.1:1055; NOZBB-NEXT: li a0, 101056; NOZBB-NEXT: .LBB24_2:1057; NOZBB-NEXT: ret1058;1059; ZBB-LABEL: smax_i32_pos_constant:1060; ZBB: # %bb.0:1061; ZBB-NEXT: li a1, 101062; ZBB-NEXT: max a0, a0, a11063; ZBB-NEXT: ret1064;1065; XQCI-LABEL: smax_i32_pos_constant:1066; XQCI: # %bb.0:1067; XQCI-NEXT: qc.lilti a0, a0, 11, 101068; XQCI-NEXT: ret1069;1070; RV32I-SFB-LABEL: smax_i32_pos_constant:1071; RV32I-SFB: # %bb.0:1072; RV32I-SFB-NEXT: li a1, 101073; RV32I-SFB-NEXT: blt a1, a0, .LBB24_21074; RV32I-SFB-NEXT: # %bb.1:1075; RV32I-SFB-NEXT: mv a0, a11076; RV32I-SFB-NEXT: .LBB24_2:1077; RV32I-SFB-NEXT: ret1078;1079; RV64I-SFB-LABEL: smax_i32_pos_constant:1080; RV64I-SFB: # %bb.0:1081; RV64I-SFB-NEXT: li a1, 101082; RV64I-SFB-NEXT: blt a1, a0, .LBB24_21083; RV64I-SFB-NEXT: # %bb.1:1084; RV64I-SFB-NEXT: mv a0, a11085; RV64I-SFB-NEXT: .LBB24_2:1086; RV64I-SFB-NEXT: ret1087 %c = call i32 @llvm.smax.i32(i32 %a, i32 10)1088 ret i32 %c1089}1090 1091define signext i32 @smax_i32_pos_constant_trailing_zeros(i32 signext %a) {1092; NOZBB-LABEL: smax_i32_pos_constant_trailing_zeros:1093; NOZBB: # %bb.0:1094; NOZBB-NEXT: andi a0, a0, -81095; NOZBB-NEXT: li a1, 161096; NOZBB-NEXT: blt a1, a0, .LBB25_21097; NOZBB-NEXT: # %bb.1:1098; NOZBB-NEXT: li a0, 161099; NOZBB-NEXT: .LBB25_2:1100; NOZBB-NEXT: ret1101;1102; ZBB-LABEL: smax_i32_pos_constant_trailing_zeros:1103; ZBB: # %bb.0:1104; ZBB-NEXT: andi a0, a0, -81105; ZBB-NEXT: li a1, 161106; ZBB-NEXT: max a0, a0, a11107; ZBB-NEXT: ret1108;1109; XQCI-LABEL: smax_i32_pos_constant_trailing_zeros:1110; XQCI: # %bb.0:1111; XQCI-NEXT: andi a1, a0, -81112; XQCI-NEXT: li a0, 161113; XQCI-NEXT: qc.mvlt a0, a0, a1, a11114; XQCI-NEXT: ret1115;1116; RV32I-SFB-LABEL: smax_i32_pos_constant_trailing_zeros:1117; RV32I-SFB: # %bb.0:1118; RV32I-SFB-NEXT: andi a1, a0, -81119; RV32I-SFB-NEXT: li a0, 161120; RV32I-SFB-NEXT: bge a0, a1, .LBB25_21121; RV32I-SFB-NEXT: # %bb.1:1122; RV32I-SFB-NEXT: mv a0, a11123; RV32I-SFB-NEXT: .LBB25_2:1124; RV32I-SFB-NEXT: ret1125;1126; RV64I-SFB-LABEL: smax_i32_pos_constant_trailing_zeros:1127; RV64I-SFB: # %bb.0:1128; RV64I-SFB-NEXT: andi a1, a0, -81129; RV64I-SFB-NEXT: li a0, 161130; RV64I-SFB-NEXT: bge a0, a1, .LBB25_21131; RV64I-SFB-NEXT: # %bb.1:1132; RV64I-SFB-NEXT: mv a0, a11133; RV64I-SFB-NEXT: .LBB25_2:1134; RV64I-SFB-NEXT: ret1135 %b = and i32 %a, -81136 %c = call i32 @llvm.smax.i32(i32 %b, i32 16)1137 %d = and i32 %c, -41138 ret i32 %d1139}1140 1141define signext i32 @smin_i32_negone(i32 signext %a) {1142; NOZBB-LABEL: smin_i32_negone:1143; NOZBB: # %bb.0:1144; NOZBB-NEXT: slti a1, a0, -11145; NOZBB-NEXT: addi a1, a1, -11146; NOZBB-NEXT: or a0, a1, a01147; NOZBB-NEXT: ret1148;1149; ZBB-LABEL: smin_i32_negone:1150; ZBB: # %bb.0:1151; ZBB-NEXT: li a1, -11152; ZBB-NEXT: min a0, a0, a11153; ZBB-NEXT: ret1154;1155; XQCI-LABEL: smin_i32_negone:1156; XQCI: # %bb.0:1157; XQCI-NEXT: qc.ligei a0, a0, 0, -11158; XQCI-NEXT: ret1159;1160; RV32I-SFB-LABEL: smin_i32_negone:1161; RV32I-SFB: # %bb.0:1162; RV32I-SFB-NEXT: li a1, -11163; RV32I-SFB-NEXT: bltz a0, .LBB26_21164; RV32I-SFB-NEXT: # %bb.1:1165; RV32I-SFB-NEXT: mv a0, a11166; RV32I-SFB-NEXT: .LBB26_2:1167; RV32I-SFB-NEXT: ret1168;1169; RV64I-SFB-LABEL: smin_i32_negone:1170; RV64I-SFB: # %bb.0:1171; RV64I-SFB-NEXT: li a1, -11172; RV64I-SFB-NEXT: bltz a0, .LBB26_21173; RV64I-SFB-NEXT: # %bb.1:1174; RV64I-SFB-NEXT: mv a0, a11175; RV64I-SFB-NEXT: .LBB26_2:1176; RV64I-SFB-NEXT: ret1177 %c = call i32 @llvm.smin.i32(i32 %a, i32 -1)1178 ret i32 %c1179}1180 1181define i64 @smin_i64_negone(i64 %a) {1182; RV32I-LABEL: smin_i64_negone:1183; RV32I: # %bb.0:1184; RV32I-NEXT: srli a2, a1, 311185; RV32I-NEXT: addi a2, a2, -11186; RV32I-NEXT: or a0, a2, a01187; RV32I-NEXT: slti a2, a1, -11188; RV32I-NEXT: addi a2, a2, -11189; RV32I-NEXT: or a1, a2, a11190; RV32I-NEXT: ret1191;1192; RV64I-LABEL: smin_i64_negone:1193; RV64I: # %bb.0:1194; RV64I-NEXT: slti a1, a0, -11195; RV64I-NEXT: addi a1, a1, -11196; RV64I-NEXT: or a0, a1, a01197; RV64I-NEXT: ret1198;1199; RV32ZBB-LABEL: smin_i64_negone:1200; RV32ZBB: # %bb.0:1201; RV32ZBB-NEXT: li a2, -11202; RV32ZBB-NEXT: min a2, a1, a21203; RV32ZBB-NEXT: srli a1, a1, 311204; RV32ZBB-NEXT: addi a1, a1, -11205; RV32ZBB-NEXT: or a0, a1, a01206; RV32ZBB-NEXT: mv a1, a21207; RV32ZBB-NEXT: ret1208;1209; RV64ZBB-LABEL: smin_i64_negone:1210; RV64ZBB: # %bb.0:1211; RV64ZBB-NEXT: li a1, -11212; RV64ZBB-NEXT: min a0, a0, a11213; RV64ZBB-NEXT: ret1214;1215; XQCI-LABEL: smin_i64_negone:1216; XQCI: # %bb.0:1217; XQCI-NEXT: qc.ligei a0, a1, 0, -11218; XQCI-NEXT: qc.ligei a1, a1, 0, -11219; XQCI-NEXT: ret1220;1221; RV32I-SFB-LABEL: smin_i64_negone:1222; RV32I-SFB: # %bb.0:1223; RV32I-SFB-NEXT: li a2, -11224; RV32I-SFB-NEXT: bltz a1, .LBB27_21225; RV32I-SFB-NEXT: # %bb.1:1226; RV32I-SFB-NEXT: mv a0, a21227; RV32I-SFB-NEXT: .LBB27_2:1228; RV32I-SFB-NEXT: bltz a1, .LBB27_41229; RV32I-SFB-NEXT: # %bb.3:1230; RV32I-SFB-NEXT: mv a1, a21231; RV32I-SFB-NEXT: .LBB27_4:1232; RV32I-SFB-NEXT: ret1233;1234; RV64I-SFB-LABEL: smin_i64_negone:1235; RV64I-SFB: # %bb.0:1236; RV64I-SFB-NEXT: li a1, -11237; RV64I-SFB-NEXT: bltz a0, .LBB27_21238; RV64I-SFB-NEXT: # %bb.1:1239; RV64I-SFB-NEXT: mv a0, a11240; RV64I-SFB-NEXT: .LBB27_2:1241; RV64I-SFB-NEXT: ret1242 %c = call i64 @llvm.smin.i64(i64 %a, i64 -1)1243 ret i64 %c1244}1245 1246define i64 @umax_i64_one(i64 %a, i64 %b) {1247; RV32I-LABEL: umax_i64_one:1248; RV32I: # %bb.0:1249; RV32I-NEXT: mv a2, a01250; RV32I-NEXT: beqz a1, .LBB28_31251; RV32I-NEXT: # %bb.1:1252; RV32I-NEXT: beqz a1, .LBB28_41253; RV32I-NEXT: .LBB28_2:1254; RV32I-NEXT: ret1255; RV32I-NEXT: .LBB28_3:1256; RV32I-NEXT: li a0, 11257; RV32I-NEXT: bnez a1, .LBB28_21258; RV32I-NEXT: .LBB28_4:1259; RV32I-NEXT: seqz a0, a21260; RV32I-NEXT: add a0, a2, a01261; RV32I-NEXT: ret1262;1263; RV64I-LABEL: umax_i64_one:1264; RV64I: # %bb.0:1265; RV64I-NEXT: seqz a1, a01266; RV64I-NEXT: add a0, a0, a11267; RV64I-NEXT: ret1268;1269; RV32ZBB-LABEL: umax_i64_one:1270; RV32ZBB: # %bb.0:1271; RV32ZBB-NEXT: mv a2, a01272; RV32ZBB-NEXT: li a3, 11273; RV32ZBB-NEXT: beqz a1, .LBB28_31274; RV32ZBB-NEXT: # %bb.1:1275; RV32ZBB-NEXT: beqz a1, .LBB28_41276; RV32ZBB-NEXT: .LBB28_2:1277; RV32ZBB-NEXT: ret1278; RV32ZBB-NEXT: .LBB28_3:1279; RV32ZBB-NEXT: li a0, 11280; RV32ZBB-NEXT: bnez a1, .LBB28_21281; RV32ZBB-NEXT: .LBB28_4:1282; RV32ZBB-NEXT: maxu a0, a2, a31283; RV32ZBB-NEXT: ret1284;1285; RV64ZBB-LABEL: umax_i64_one:1286; RV64ZBB: # %bb.0:1287; RV64ZBB-NEXT: li a1, 11288; RV64ZBB-NEXT: maxu a0, a0, a11289; RV64ZBB-NEXT: ret1290;1291; XQCI-LABEL: umax_i64_one:1292; XQCI: # %bb.0:1293; XQCI-NEXT: mv a2, a11294; XQCI-NEXT: qc.selectinei a2, 0, a0, 11295; XQCI-NEXT: qc.liltui a0, a0, 2, 11296; XQCI-NEXT: qc.mvnei a0, a1, 0, a21297; XQCI-NEXT: ret1298;1299; RV32I-SFB-LABEL: umax_i64_one:1300; RV32I-SFB: # %bb.0:1301; RV32I-SFB-NEXT: li a2, 11302; RV32I-SFB-NEXT: li a3, 11303; RV32I-SFB-NEXT: beqz a1, .LBB28_21304; RV32I-SFB-NEXT: # %bb.1:1305; RV32I-SFB-NEXT: mv a3, a01306; RV32I-SFB-NEXT: .LBB28_2:1307; RV32I-SFB-NEXT: bnez a0, .LBB28_41308; RV32I-SFB-NEXT: # %bb.3:1309; RV32I-SFB-NEXT: mv a0, a21310; RV32I-SFB-NEXT: .LBB28_4:1311; RV32I-SFB-NEXT: beqz a1, .LBB28_61312; RV32I-SFB-NEXT: # %bb.5:1313; RV32I-SFB-NEXT: mv a0, a31314; RV32I-SFB-NEXT: .LBB28_6:1315; RV32I-SFB-NEXT: ret1316;1317; RV64I-SFB-LABEL: umax_i64_one:1318; RV64I-SFB: # %bb.0:1319; RV64I-SFB-NEXT: li a1, 11320; RV64I-SFB-NEXT: bnez a0, .LBB28_21321; RV64I-SFB-NEXT: # %bb.1:1322; RV64I-SFB-NEXT: mv a0, a11323; RV64I-SFB-NEXT: .LBB28_2:1324; RV64I-SFB-NEXT: ret1325 %c = call i64 @llvm.umax.i64(i64 %a, i64 1)1326 ret i64 %c1327}1328