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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32I %s4; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV32IM %s6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \7; RUN: | FileCheck -check-prefix=RV64I %s8; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \9; RUN: | FileCheck -check-prefix=RV64IM %s10 11define signext i32 @square(i32 %a) nounwind {12; RV32I-LABEL: square:13; RV32I: # %bb.0:14; RV32I-NEXT: addi sp, sp, -1615; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill16; RV32I-NEXT: mv a1, a017; RV32I-NEXT: call __mulsi318; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload19; RV32I-NEXT: addi sp, sp, 1620; RV32I-NEXT: ret21;22; RV32IM-LABEL: square:23; RV32IM: # %bb.0:24; RV32IM-NEXT: mul a0, a0, a025; RV32IM-NEXT: ret26;27; RV64I-LABEL: square:28; RV64I: # %bb.0:29; RV64I-NEXT: addi sp, sp, -1630; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill31; RV64I-NEXT: mv a1, a032; RV64I-NEXT: call __muldi333; RV64I-NEXT: sext.w a0, a034; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload35; RV64I-NEXT: addi sp, sp, 1636; RV64I-NEXT: ret37;38; RV64IM-LABEL: square:39; RV64IM: # %bb.0:40; RV64IM-NEXT: mulw a0, a0, a041; RV64IM-NEXT: ret42 %1 = mul i32 %a, %a43 ret i32 %144}45 46define signext i32 @mul(i32 %a, i32 %b) nounwind {47; RV32I-LABEL: mul:48; RV32I: # %bb.0:49; RV32I-NEXT: addi sp, sp, -1650; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill51; RV32I-NEXT: call __mulsi352; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload53; RV32I-NEXT: addi sp, sp, 1654; RV32I-NEXT: ret55;56; RV32IM-LABEL: mul:57; RV32IM: # %bb.0:58; RV32IM-NEXT: mul a0, a0, a159; RV32IM-NEXT: ret60;61; RV64I-LABEL: mul:62; RV64I: # %bb.0:63; RV64I-NEXT: addi sp, sp, -1664; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill65; RV64I-NEXT: call __muldi366; RV64I-NEXT: sext.w a0, a067; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload68; RV64I-NEXT: addi sp, sp, 1669; RV64I-NEXT: ret70;71; RV64IM-LABEL: mul:72; RV64IM: # %bb.0:73; RV64IM-NEXT: mulw a0, a0, a174; RV64IM-NEXT: ret75 %1 = mul i32 %a, %b76 ret i32 %177}78 79define signext i32 @mul_constant(i32 %a) nounwind {80; RV32I-LABEL: mul_constant:81; RV32I: # %bb.0:82; RV32I-NEXT: slli a1, a0, 283; RV32I-NEXT: add a0, a1, a084; RV32I-NEXT: ret85;86; RV32IM-LABEL: mul_constant:87; RV32IM: # %bb.0:88; RV32IM-NEXT: slli a1, a0, 289; RV32IM-NEXT: add a0, a1, a090; RV32IM-NEXT: ret91;92; RV64I-LABEL: mul_constant:93; RV64I: # %bb.0:94; RV64I-NEXT: slli a1, a0, 295; RV64I-NEXT: addw a0, a1, a096; RV64I-NEXT: ret97;98; RV64IM-LABEL: mul_constant:99; RV64IM: # %bb.0:100; RV64IM-NEXT: slli a1, a0, 2101; RV64IM-NEXT: addw a0, a1, a0102; RV64IM-NEXT: ret103 %1 = mul i32 %a, 5104 ret i32 %1105}106 107define i32 @mul_pow2(i32 %a) nounwind {108; RV32I-LABEL: mul_pow2:109; RV32I: # %bb.0:110; RV32I-NEXT: slli a0, a0, 3111; RV32I-NEXT: ret112;113; RV32IM-LABEL: mul_pow2:114; RV32IM: # %bb.0:115; RV32IM-NEXT: slli a0, a0, 3116; RV32IM-NEXT: ret117;118; RV64I-LABEL: mul_pow2:119; RV64I: # %bb.0:120; RV64I-NEXT: slliw a0, a0, 3121; RV64I-NEXT: ret122;123; RV64IM-LABEL: mul_pow2:124; RV64IM: # %bb.0:125; RV64IM-NEXT: slliw a0, a0, 3126; RV64IM-NEXT: ret127 %1 = mul i32 %a, 8128 ret i32 %1129}130 131define i64 @mul64(i64 %a, i64 %b) nounwind {132; RV32I-LABEL: mul64:133; RV32I: # %bb.0:134; RV32I-NEXT: addi sp, sp, -16135; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill136; RV32I-NEXT: call __muldi3137; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload138; RV32I-NEXT: addi sp, sp, 16139; RV32I-NEXT: ret140;141; RV32IM-LABEL: mul64:142; RV32IM: # %bb.0:143; RV32IM-NEXT: mul a3, a0, a3144; RV32IM-NEXT: mulhu a4, a0, a2145; RV32IM-NEXT: mul a1, a1, a2146; RV32IM-NEXT: add a3, a4, a3147; RV32IM-NEXT: add a1, a3, a1148; RV32IM-NEXT: mul a0, a0, a2149; RV32IM-NEXT: ret150;151; RV64I-LABEL: mul64:152; RV64I: # %bb.0:153; RV64I-NEXT: tail __muldi3154;155; RV64IM-LABEL: mul64:156; RV64IM: # %bb.0:157; RV64IM-NEXT: mul a0, a0, a1158; RV64IM-NEXT: ret159 %1 = mul i64 %a, %b160 ret i64 %1161}162 163define i64 @mul64_constant(i64 %a) nounwind {164; RV32I-LABEL: mul64_constant:165; RV32I: # %bb.0:166; RV32I-NEXT: slli a2, a0, 2167; RV32I-NEXT: srli a3, a0, 30168; RV32I-NEXT: slli a4, a1, 2169; RV32I-NEXT: add a0, a2, a0170; RV32I-NEXT: or a3, a4, a3171; RV32I-NEXT: sltu a2, a0, a2172; RV32I-NEXT: add a1, a3, a1173; RV32I-NEXT: add a1, a1, a2174; RV32I-NEXT: ret175;176; RV32IM-LABEL: mul64_constant:177; RV32IM: # %bb.0:178; RV32IM-NEXT: li a2, 5179; RV32IM-NEXT: slli a3, a1, 2180; RV32IM-NEXT: add a1, a3, a1181; RV32IM-NEXT: slli a3, a0, 2182; RV32IM-NEXT: mulhu a2, a0, a2183; RV32IM-NEXT: add a1, a2, a1184; RV32IM-NEXT: add a0, a3, a0185; RV32IM-NEXT: ret186;187; RV64I-LABEL: mul64_constant:188; RV64I: # %bb.0:189; RV64I-NEXT: slli a1, a0, 2190; RV64I-NEXT: add a0, a1, a0191; RV64I-NEXT: ret192;193; RV64IM-LABEL: mul64_constant:194; RV64IM: # %bb.0:195; RV64IM-NEXT: slli a1, a0, 2196; RV64IM-NEXT: add a0, a1, a0197; RV64IM-NEXT: ret198 %1 = mul i64 %a, 5199 ret i64 %1200}201 202define i32 @mulhs(i32 %a, i32 %b) nounwind {203; RV32I-LABEL: mulhs:204; RV32I: # %bb.0:205; RV32I-NEXT: addi sp, sp, -16206; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill207; RV32I-NEXT: mv a2, a1208; RV32I-NEXT: srai a1, a0, 31209; RV32I-NEXT: srai a3, a2, 31210; RV32I-NEXT: call __muldi3211; RV32I-NEXT: mv a0, a1212; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload213; RV32I-NEXT: addi sp, sp, 16214; RV32I-NEXT: ret215;216; RV32IM-LABEL: mulhs:217; RV32IM: # %bb.0:218; RV32IM-NEXT: mulh a0, a0, a1219; RV32IM-NEXT: ret220;221; RV64I-LABEL: mulhs:222; RV64I: # %bb.0:223; RV64I-NEXT: addi sp, sp, -16224; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill225; RV64I-NEXT: sext.w a0, a0226; RV64I-NEXT: sext.w a1, a1227; RV64I-NEXT: call __muldi3228; RV64I-NEXT: srli a0, a0, 32229; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload230; RV64I-NEXT: addi sp, sp, 16231; RV64I-NEXT: ret232;233; RV64IM-LABEL: mulhs:234; RV64IM: # %bb.0:235; RV64IM-NEXT: sext.w a0, a0236; RV64IM-NEXT: sext.w a1, a1237; RV64IM-NEXT: mul a0, a0, a1238; RV64IM-NEXT: srli a0, a0, 32239; RV64IM-NEXT: ret240 %1 = sext i32 %a to i64241 %2 = sext i32 %b to i64242 %3 = mul i64 %1, %2243 %4 = lshr i64 %3, 32244 %5 = trunc i64 %4 to i32245 ret i32 %5246}247 248define i32 @mulhs_positive_constant(i32 %a) nounwind {249; RV32I-LABEL: mulhs_positive_constant:250; RV32I: # %bb.0:251; RV32I-NEXT: srai a1, a0, 31252; RV32I-NEXT: slli a2, a0, 2253; RV32I-NEXT: srli a3, a0, 30254; RV32I-NEXT: add a0, a2, a0255; RV32I-NEXT: sltu a0, a0, a2256; RV32I-NEXT: slli a2, a1, 2257; RV32I-NEXT: or a2, a2, a3258; RV32I-NEXT: add a1, a2, a1259; RV32I-NEXT: add a0, a1, a0260; RV32I-NEXT: ret261;262; RV32IM-LABEL: mulhs_positive_constant:263; RV32IM: # %bb.0:264; RV32IM-NEXT: li a1, 5265; RV32IM-NEXT: mulh a0, a0, a1266; RV32IM-NEXT: ret267;268; RV64I-LABEL: mulhs_positive_constant:269; RV64I: # %bb.0:270; RV64I-NEXT: sext.w a0, a0271; RV64I-NEXT: slli a1, a0, 2272; RV64I-NEXT: add a0, a1, a0273; RV64I-NEXT: srli a0, a0, 32274; RV64I-NEXT: ret275;276; RV64IM-LABEL: mulhs_positive_constant:277; RV64IM: # %bb.0:278; RV64IM-NEXT: sext.w a0, a0279; RV64IM-NEXT: slli a1, a0, 2280; RV64IM-NEXT: add a0, a1, a0281; RV64IM-NEXT: srli a0, a0, 32282; RV64IM-NEXT: ret283 %1 = sext i32 %a to i64284 %2 = mul i64 %1, 5285 %3 = lshr i64 %2, 32286 %4 = trunc i64 %3 to i32287 ret i32 %4288}289 290define i32 @mulhs_negative_constant(i32 %a) nounwind {291; RV32I-LABEL: mulhs_negative_constant:292; RV32I: # %bb.0:293; RV32I-NEXT: srai a1, a0, 31294; RV32I-NEXT: slli a2, a0, 2295; RV32I-NEXT: srli a3, a0, 30296; RV32I-NEXT: add a0, a2, a0297; RV32I-NEXT: slli a4, a1, 2298; RV32I-NEXT: sltu a2, a0, a2299; RV32I-NEXT: or a3, a4, a3300; RV32I-NEXT: snez a0, a0301; RV32I-NEXT: add a1, a3, a1302; RV32I-NEXT: add a0, a2, a0303; RV32I-NEXT: add a0, a1, a0304; RV32I-NEXT: neg a0, a0305; RV32I-NEXT: ret306;307; RV32IM-LABEL: mulhs_negative_constant:308; RV32IM: # %bb.0:309; RV32IM-NEXT: li a1, -5310; RV32IM-NEXT: mulh a0, a0, a1311; RV32IM-NEXT: ret312;313; RV64I-LABEL: mulhs_negative_constant:314; RV64I: # %bb.0:315; RV64I-NEXT: sext.w a0, a0316; RV64I-NEXT: slli a1, a0, 2317; RV64I-NEXT: neg a0, a0318; RV64I-NEXT: sub a0, a0, a1319; RV64I-NEXT: srli a0, a0, 32320; RV64I-NEXT: ret321;322; RV64IM-LABEL: mulhs_negative_constant:323; RV64IM: # %bb.0:324; RV64IM-NEXT: sext.w a0, a0325; RV64IM-NEXT: slli a1, a0, 2326; RV64IM-NEXT: neg a0, a0327; RV64IM-NEXT: sub a0, a0, a1328; RV64IM-NEXT: srli a0, a0, 32329; RV64IM-NEXT: ret330 %1 = sext i32 %a to i64331 %2 = mul i64 %1, -5332 %3 = lshr i64 %2, 32333 %4 = trunc i64 %3 to i32334 ret i32 %4335}336 337define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind {338; RV32I-LABEL: mulhu:339; RV32I: # %bb.0:340; RV32I-NEXT: addi sp, sp, -16341; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill342; RV32I-NEXT: mv a2, a1343; RV32I-NEXT: li a1, 0344; RV32I-NEXT: li a3, 0345; RV32I-NEXT: call __muldi3346; RV32I-NEXT: mv a0, a1347; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload348; RV32I-NEXT: addi sp, sp, 16349; RV32I-NEXT: ret350;351; RV32IM-LABEL: mulhu:352; RV32IM: # %bb.0:353; RV32IM-NEXT: mulhu a0, a0, a1354; RV32IM-NEXT: ret355;356; RV64I-LABEL: mulhu:357; RV64I: # %bb.0:358; RV64I-NEXT: addi sp, sp, -16359; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill360; RV64I-NEXT: call __muldi3361; RV64I-NEXT: srli a0, a0, 32362; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload363; RV64I-NEXT: addi sp, sp, 16364; RV64I-NEXT: ret365;366; RV64IM-LABEL: mulhu:367; RV64IM: # %bb.0:368; RV64IM-NEXT: mul a0, a0, a1369; RV64IM-NEXT: srli a0, a0, 32370; RV64IM-NEXT: ret371 %1 = zext i32 %a to i64372 %2 = zext i32 %b to i64373 %3 = mul i64 %1, %2374 %4 = lshr i64 %3, 32375 %5 = trunc i64 %4 to i32376 ret i32 %5377}378 379define i32 @mulhsu(i32 %a, i32 %b) nounwind {380; RV32I-LABEL: mulhsu:381; RV32I: # %bb.0:382; RV32I-NEXT: addi sp, sp, -16383; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill384; RV32I-NEXT: mv a2, a1385; RV32I-NEXT: srai a3, a1, 31386; RV32I-NEXT: li a1, 0387; RV32I-NEXT: call __muldi3388; RV32I-NEXT: mv a0, a1389; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload390; RV32I-NEXT: addi sp, sp, 16391; RV32I-NEXT: ret392;393; RV32IM-LABEL: mulhsu:394; RV32IM: # %bb.0:395; RV32IM-NEXT: mulhsu a0, a1, a0396; RV32IM-NEXT: ret397;398; RV64I-LABEL: mulhsu:399; RV64I: # %bb.0:400; RV64I-NEXT: addi sp, sp, -16401; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill402; RV64I-NEXT: slli a0, a0, 32403; RV64I-NEXT: srli a0, a0, 32404; RV64I-NEXT: sext.w a1, a1405; RV64I-NEXT: call __muldi3406; RV64I-NEXT: srli a0, a0, 32407; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload408; RV64I-NEXT: addi sp, sp, 16409; RV64I-NEXT: ret410;411; RV64IM-LABEL: mulhsu:412; RV64IM: # %bb.0:413; RV64IM-NEXT: slli a0, a0, 32414; RV64IM-NEXT: srli a0, a0, 32415; RV64IM-NEXT: sext.w a1, a1416; RV64IM-NEXT: mul a0, a0, a1417; RV64IM-NEXT: srli a0, a0, 32418; RV64IM-NEXT: ret419 %1 = zext i32 %a to i64420 %2 = sext i32 %b to i64421 %3 = mul i64 %1, %2422 %4 = lshr i64 %3, 32423 %5 = trunc i64 %4 to i32424 ret i32 %5425}426 427define i32 @mulhu_constant(i32 %a) nounwind {428; RV32I-LABEL: mulhu_constant:429; RV32I: # %bb.0:430; RV32I-NEXT: slli a1, a0, 2431; RV32I-NEXT: add a2, a1, a0432; RV32I-NEXT: sltu a1, a2, a1433; RV32I-NEXT: srli a0, a0, 30434; RV32I-NEXT: add a0, a0, a1435; RV32I-NEXT: ret436;437; RV32IM-LABEL: mulhu_constant:438; RV32IM: # %bb.0:439; RV32IM-NEXT: li a1, 5440; RV32IM-NEXT: mulhu a0, a0, a1441; RV32IM-NEXT: ret442;443; RV64I-LABEL: mulhu_constant:444; RV64I: # %bb.0:445; RV64I-NEXT: slli a0, a0, 32446; RV64I-NEXT: srli a1, a0, 32447; RV64I-NEXT: srli a0, a0, 30448; RV64I-NEXT: add a0, a0, a1449; RV64I-NEXT: srli a0, a0, 32450; RV64I-NEXT: ret451;452; RV64IM-LABEL: mulhu_constant:453; RV64IM: # %bb.0:454; RV64IM-NEXT: slli a0, a0, 32455; RV64IM-NEXT: srli a1, a0, 32456; RV64IM-NEXT: srli a0, a0, 30457; RV64IM-NEXT: add a0, a0, a1458; RV64IM-NEXT: srli a0, a0, 32459; RV64IM-NEXT: ret460 %1 = zext i32 %a to i64461 %2 = mul i64 %1, 5462 %3 = lshr i64 %2, 32463 %4 = trunc i64 %3 to i32464 ret i32 %4465}466 467define i32 @muli32_p10(i32 %a) nounwind {468; RV32I-LABEL: muli32_p10:469; RV32I: # %bb.0:470; RV32I-NEXT: slli a1, a0, 1471; RV32I-NEXT: slli a0, a0, 3472; RV32I-NEXT: add a0, a0, a1473; RV32I-NEXT: ret474;475; RV32IM-LABEL: muli32_p10:476; RV32IM: # %bb.0:477; RV32IM-NEXT: slli a1, a0, 1478; RV32IM-NEXT: slli a0, a0, 3479; RV32IM-NEXT: add a0, a0, a1480; RV32IM-NEXT: ret481;482; RV64I-LABEL: muli32_p10:483; RV64I: # %bb.0:484; RV64I-NEXT: slli a1, a0, 1485; RV64I-NEXT: slli a0, a0, 3486; RV64I-NEXT: add a0, a0, a1487; RV64I-NEXT: ret488;489; RV64IM-LABEL: muli32_p10:490; RV64IM: # %bb.0:491; RV64IM-NEXT: slli a1, a0, 1492; RV64IM-NEXT: slli a0, a0, 3493; RV64IM-NEXT: addw a0, a0, a1494; RV64IM-NEXT: ret495 %1 = mul i32 %a, 10496 ret i32 %1497}498 499define i32 @muli32_p14(i32 %a) nounwind {500; RV32I-LABEL: muli32_p14:501; RV32I: # %bb.0:502; RV32I-NEXT: slli a1, a0, 1503; RV32I-NEXT: slli a0, a0, 4504; RV32I-NEXT: sub a0, a0, a1505; RV32I-NEXT: ret506;507; RV32IM-LABEL: muli32_p14:508; RV32IM: # %bb.0:509; RV32IM-NEXT: slli a1, a0, 1510; RV32IM-NEXT: slli a0, a0, 4511; RV32IM-NEXT: sub a0, a0, a1512; RV32IM-NEXT: ret513;514; RV64I-LABEL: muli32_p14:515; RV64I: # %bb.0:516; RV64I-NEXT: slli a1, a0, 1517; RV64I-NEXT: slli a0, a0, 4518; RV64I-NEXT: sub a0, a0, a1519; RV64I-NEXT: ret520;521; RV64IM-LABEL: muli32_p14:522; RV64IM: # %bb.0:523; RV64IM-NEXT: slli a1, a0, 1524; RV64IM-NEXT: slli a0, a0, 4525; RV64IM-NEXT: subw a0, a0, a1526; RV64IM-NEXT: ret527 %1 = mul i32 %a, 14528 ret i32 %1529}530 531define i32 @muli32_p18(i32 %a) nounwind {532; RV32I-LABEL: muli32_p18:533; RV32I: # %bb.0:534; RV32I-NEXT: slli a1, a0, 1535; RV32I-NEXT: slli a0, a0, 4536; RV32I-NEXT: add a0, a0, a1537; RV32I-NEXT: ret538;539; RV32IM-LABEL: muli32_p18:540; RV32IM: # %bb.0:541; RV32IM-NEXT: slli a1, a0, 1542; RV32IM-NEXT: slli a0, a0, 4543; RV32IM-NEXT: add a0, a0, a1544; RV32IM-NEXT: ret545;546; RV64I-LABEL: muli32_p18:547; RV64I: # %bb.0:548; RV64I-NEXT: slli a1, a0, 1549; RV64I-NEXT: slli a0, a0, 4550; RV64I-NEXT: add a0, a0, a1551; RV64I-NEXT: ret552;553; RV64IM-LABEL: muli32_p18:554; RV64IM: # %bb.0:555; RV64IM-NEXT: slli a1, a0, 1556; RV64IM-NEXT: slli a0, a0, 4557; RV64IM-NEXT: addw a0, a0, a1558; RV64IM-NEXT: ret559 %1 = mul i32 %a, 18560 ret i32 %1561}562 563define i32 @muli32_p28(i32 %a) nounwind {564; RV32I-LABEL: muli32_p28:565; RV32I: # %bb.0:566; RV32I-NEXT: slli a1, a0, 2567; RV32I-NEXT: slli a0, a0, 5568; RV32I-NEXT: sub a0, a0, a1569; RV32I-NEXT: ret570;571; RV32IM-LABEL: muli32_p28:572; RV32IM: # %bb.0:573; RV32IM-NEXT: slli a1, a0, 2574; RV32IM-NEXT: slli a0, a0, 5575; RV32IM-NEXT: sub a0, a0, a1576; RV32IM-NEXT: ret577;578; RV64I-LABEL: muli32_p28:579; RV64I: # %bb.0:580; RV64I-NEXT: slli a1, a0, 2581; RV64I-NEXT: slli a0, a0, 5582; RV64I-NEXT: sub a0, a0, a1583; RV64I-NEXT: ret584;585; RV64IM-LABEL: muli32_p28:586; RV64IM: # %bb.0:587; RV64IM-NEXT: slli a1, a0, 2588; RV64IM-NEXT: slli a0, a0, 5589; RV64IM-NEXT: subw a0, a0, a1590; RV64IM-NEXT: ret591 %1 = mul i32 %a, 28592 ret i32 %1593}594 595define i32 @muli32_p30(i32 %a) nounwind {596; RV32I-LABEL: muli32_p30:597; RV32I: # %bb.0:598; RV32I-NEXT: slli a1, a0, 1599; RV32I-NEXT: slli a0, a0, 5600; RV32I-NEXT: sub a0, a0, a1601; RV32I-NEXT: ret602;603; RV32IM-LABEL: muli32_p30:604; RV32IM: # %bb.0:605; RV32IM-NEXT: slli a1, a0, 1606; RV32IM-NEXT: slli a0, a0, 5607; RV32IM-NEXT: sub a0, a0, a1608; RV32IM-NEXT: ret609;610; RV64I-LABEL: muli32_p30:611; RV64I: # %bb.0:612; RV64I-NEXT: slli a1, a0, 1613; RV64I-NEXT: slli a0, a0, 5614; RV64I-NEXT: sub a0, a0, a1615; RV64I-NEXT: ret616;617; RV64IM-LABEL: muli32_p30:618; RV64IM: # %bb.0:619; RV64IM-NEXT: slli a1, a0, 1620; RV64IM-NEXT: slli a0, a0, 5621; RV64IM-NEXT: subw a0, a0, a1622; RV64IM-NEXT: ret623 %1 = mul i32 %a, 30624 ret i32 %1625}626 627define i32 @muli32_p34(i32 %a) nounwind {628; RV32I-LABEL: muli32_p34:629; RV32I: # %bb.0:630; RV32I-NEXT: slli a1, a0, 1631; RV32I-NEXT: slli a0, a0, 5632; RV32I-NEXT: add a0, a0, a1633; RV32I-NEXT: ret634;635; RV32IM-LABEL: muli32_p34:636; RV32IM: # %bb.0:637; RV32IM-NEXT: slli a1, a0, 1638; RV32IM-NEXT: slli a0, a0, 5639; RV32IM-NEXT: add a0, a0, a1640; RV32IM-NEXT: ret641;642; RV64I-LABEL: muli32_p34:643; RV64I: # %bb.0:644; RV64I-NEXT: slli a1, a0, 1645; RV64I-NEXT: slli a0, a0, 5646; RV64I-NEXT: add a0, a0, a1647; RV64I-NEXT: ret648;649; RV64IM-LABEL: muli32_p34:650; RV64IM: # %bb.0:651; RV64IM-NEXT: slli a1, a0, 1652; RV64IM-NEXT: slli a0, a0, 5653; RV64IM-NEXT: addw a0, a0, a1654; RV64IM-NEXT: ret655 %1 = mul i32 %a, 34656 ret i32 %1657}658 659define i32 @muli32_p36(i32 %a) nounwind {660; RV32I-LABEL: muli32_p36:661; RV32I: # %bb.0:662; RV32I-NEXT: slli a1, a0, 2663; RV32I-NEXT: slli a0, a0, 5664; RV32I-NEXT: add a0, a0, a1665; RV32I-NEXT: ret666;667; RV32IM-LABEL: muli32_p36:668; RV32IM: # %bb.0:669; RV32IM-NEXT: slli a1, a0, 2670; RV32IM-NEXT: slli a0, a0, 5671; RV32IM-NEXT: add a0, a0, a1672; RV32IM-NEXT: ret673;674; RV64I-LABEL: muli32_p36:675; RV64I: # %bb.0:676; RV64I-NEXT: slli a1, a0, 2677; RV64I-NEXT: slli a0, a0, 5678; RV64I-NEXT: add a0, a0, a1679; RV64I-NEXT: ret680;681; RV64IM-LABEL: muli32_p36:682; RV64IM: # %bb.0:683; RV64IM-NEXT: slli a1, a0, 2684; RV64IM-NEXT: slli a0, a0, 5685; RV64IM-NEXT: addw a0, a0, a1686; RV64IM-NEXT: ret687 %1 = mul i32 %a, 36688 ret i32 %1689}690 691define i32 @muli32_p56(i32 %a) nounwind {692; RV32I-LABEL: muli32_p56:693; RV32I: # %bb.0:694; RV32I-NEXT: slli a1, a0, 3695; RV32I-NEXT: slli a0, a0, 6696; RV32I-NEXT: sub a0, a0, a1697; RV32I-NEXT: ret698;699; RV32IM-LABEL: muli32_p56:700; RV32IM: # %bb.0:701; RV32IM-NEXT: slli a1, a0, 3702; RV32IM-NEXT: slli a0, a0, 6703; RV32IM-NEXT: sub a0, a0, a1704; RV32IM-NEXT: ret705;706; RV64I-LABEL: muli32_p56:707; RV64I: # %bb.0:708; RV64I-NEXT: slli a1, a0, 3709; RV64I-NEXT: slli a0, a0, 6710; RV64I-NEXT: sub a0, a0, a1711; RV64I-NEXT: ret712;713; RV64IM-LABEL: muli32_p56:714; RV64IM: # %bb.0:715; RV64IM-NEXT: slli a1, a0, 3716; RV64IM-NEXT: slli a0, a0, 6717; RV64IM-NEXT: subw a0, a0, a1718; RV64IM-NEXT: ret719 %1 = mul i32 %a, 56720 ret i32 %1721}722 723define i32 @muli32_p60(i32 %a) nounwind {724; RV32I-LABEL: muli32_p60:725; RV32I: # %bb.0:726; RV32I-NEXT: slli a1, a0, 2727; RV32I-NEXT: slli a0, a0, 6728; RV32I-NEXT: sub a0, a0, a1729; RV32I-NEXT: ret730;731; RV32IM-LABEL: muli32_p60:732; RV32IM: # %bb.0:733; RV32IM-NEXT: slli a1, a0, 2734; RV32IM-NEXT: slli a0, a0, 6735; RV32IM-NEXT: sub a0, a0, a1736; RV32IM-NEXT: ret737;738; RV64I-LABEL: muli32_p60:739; RV64I: # %bb.0:740; RV64I-NEXT: slli a1, a0, 2741; RV64I-NEXT: slli a0, a0, 6742; RV64I-NEXT: sub a0, a0, a1743; RV64I-NEXT: ret744;745; RV64IM-LABEL: muli32_p60:746; RV64IM: # %bb.0:747; RV64IM-NEXT: slli a1, a0, 2748; RV64IM-NEXT: slli a0, a0, 6749; RV64IM-NEXT: subw a0, a0, a1750; RV64IM-NEXT: ret751 %1 = mul i32 %a, 60752 ret i32 %1753}754 755define i32 @muli32_p62(i32 %a) nounwind {756; RV32I-LABEL: muli32_p62:757; RV32I: # %bb.0:758; RV32I-NEXT: slli a1, a0, 1759; RV32I-NEXT: slli a0, a0, 6760; RV32I-NEXT: sub a0, a0, a1761; RV32I-NEXT: ret762;763; RV32IM-LABEL: muli32_p62:764; RV32IM: # %bb.0:765; RV32IM-NEXT: slli a1, a0, 1766; RV32IM-NEXT: slli a0, a0, 6767; RV32IM-NEXT: sub a0, a0, a1768; RV32IM-NEXT: ret769;770; RV64I-LABEL: muli32_p62:771; RV64I: # %bb.0:772; RV64I-NEXT: slli a1, a0, 1773; RV64I-NEXT: slli a0, a0, 6774; RV64I-NEXT: sub a0, a0, a1775; RV64I-NEXT: ret776;777; RV64IM-LABEL: muli32_p62:778; RV64IM: # %bb.0:779; RV64IM-NEXT: slli a1, a0, 1780; RV64IM-NEXT: slli a0, a0, 6781; RV64IM-NEXT: subw a0, a0, a1782; RV64IM-NEXT: ret783 %1 = mul i32 %a, 62784 ret i32 %1785}786 787define i32 @muli32_p65(i32 %a) nounwind {788; RV32I-LABEL: muli32_p65:789; RV32I: # %bb.0:790; RV32I-NEXT: slli a1, a0, 6791; RV32I-NEXT: add a0, a1, a0792; RV32I-NEXT: ret793;794; RV32IM-LABEL: muli32_p65:795; RV32IM: # %bb.0:796; RV32IM-NEXT: slli a1, a0, 6797; RV32IM-NEXT: add a0, a1, a0798; RV32IM-NEXT: ret799;800; RV64I-LABEL: muli32_p65:801; RV64I: # %bb.0:802; RV64I-NEXT: slli a1, a0, 6803; RV64I-NEXT: addw a0, a1, a0804; RV64I-NEXT: ret805;806; RV64IM-LABEL: muli32_p65:807; RV64IM: # %bb.0:808; RV64IM-NEXT: slli a1, a0, 6809; RV64IM-NEXT: addw a0, a1, a0810; RV64IM-NEXT: ret811 %1 = mul i32 %a, 65812 ret i32 %1813}814 815define i32 @muli32_p66(i32 %a) nounwind {816; RV32I-LABEL: muli32_p66:817; RV32I: # %bb.0:818; RV32I-NEXT: slli a1, a0, 1819; RV32I-NEXT: slli a0, a0, 6820; RV32I-NEXT: add a0, a0, a1821; RV32I-NEXT: ret822;823; RV32IM-LABEL: muli32_p66:824; RV32IM: # %bb.0:825; RV32IM-NEXT: slli a1, a0, 1826; RV32IM-NEXT: slli a0, a0, 6827; RV32IM-NEXT: add a0, a0, a1828; RV32IM-NEXT: ret829;830; RV64I-LABEL: muli32_p66:831; RV64I: # %bb.0:832; RV64I-NEXT: slli a1, a0, 1833; RV64I-NEXT: slli a0, a0, 6834; RV64I-NEXT: add a0, a0, a1835; RV64I-NEXT: ret836;837; RV64IM-LABEL: muli32_p66:838; RV64IM: # %bb.0:839; RV64IM-NEXT: slli a1, a0, 1840; RV64IM-NEXT: slli a0, a0, 6841; RV64IM-NEXT: addw a0, a0, a1842; RV64IM-NEXT: ret843 %1 = mul i32 %a, 66844 ret i32 %1845}846 847define i32 @muli32_p63(i32 %a) nounwind {848; RV32I-LABEL: muli32_p63:849; RV32I: # %bb.0:850; RV32I-NEXT: slli a1, a0, 6851; RV32I-NEXT: sub a0, a1, a0852; RV32I-NEXT: ret853;854; RV32IM-LABEL: muli32_p63:855; RV32IM: # %bb.0:856; RV32IM-NEXT: slli a1, a0, 6857; RV32IM-NEXT: sub a0, a1, a0858; RV32IM-NEXT: ret859;860; RV64I-LABEL: muli32_p63:861; RV64I: # %bb.0:862; RV64I-NEXT: slli a1, a0, 6863; RV64I-NEXT: subw a0, a1, a0864; RV64I-NEXT: ret865;866; RV64IM-LABEL: muli32_p63:867; RV64IM: # %bb.0:868; RV64IM-NEXT: slli a1, a0, 6869; RV64IM-NEXT: subw a0, a1, a0870; RV64IM-NEXT: ret871 %1 = mul i32 %a, 63872 ret i32 %1873}874 875define i64 @muli64_p65(i64 %a) nounwind {876; RV32I-LABEL: muli64_p65:877; RV32I: # %bb.0:878; RV32I-NEXT: slli a2, a0, 6879; RV32I-NEXT: srli a3, a0, 26880; RV32I-NEXT: slli a4, a1, 6881; RV32I-NEXT: add a0, a2, a0882; RV32I-NEXT: or a3, a4, a3883; RV32I-NEXT: sltu a2, a0, a2884; RV32I-NEXT: add a1, a3, a1885; RV32I-NEXT: add a1, a1, a2886; RV32I-NEXT: ret887;888; RV32IM-LABEL: muli64_p65:889; RV32IM: # %bb.0:890; RV32IM-NEXT: li a2, 65891; RV32IM-NEXT: slli a3, a1, 6892; RV32IM-NEXT: add a1, a3, a1893; RV32IM-NEXT: slli a3, a0, 6894; RV32IM-NEXT: mulhu a2, a0, a2895; RV32IM-NEXT: add a1, a2, a1896; RV32IM-NEXT: add a0, a3, a0897; RV32IM-NEXT: ret898;899; RV64I-LABEL: muli64_p65:900; RV64I: # %bb.0:901; RV64I-NEXT: slli a1, a0, 6902; RV64I-NEXT: add a0, a1, a0903; RV64I-NEXT: ret904;905; RV64IM-LABEL: muli64_p65:906; RV64IM: # %bb.0:907; RV64IM-NEXT: slli a1, a0, 6908; RV64IM-NEXT: add a0, a1, a0909; RV64IM-NEXT: ret910 %1 = mul i64 %a, 65911 ret i64 %1912}913 914define i64 @muli64_p63(i64 %a) nounwind {915; RV32I-LABEL: muli64_p63:916; RV32I: # %bb.0:917; RV32I-NEXT: slli a2, a0, 6918; RV32I-NEXT: srli a3, a0, 26919; RV32I-NEXT: slli a4, a1, 6920; RV32I-NEXT: sltu a5, a2, a0921; RV32I-NEXT: or a3, a4, a3922; RV32I-NEXT: sub a1, a3, a1923; RV32I-NEXT: sub a1, a1, a5924; RV32I-NEXT: sub a0, a2, a0925; RV32I-NEXT: ret926;927; RV32IM-LABEL: muli64_p63:928; RV32IM: # %bb.0:929; RV32IM-NEXT: li a2, 63930; RV32IM-NEXT: slli a3, a1, 6931; RV32IM-NEXT: sub a1, a3, a1932; RV32IM-NEXT: slli a3, a0, 6933; RV32IM-NEXT: mulhu a2, a0, a2934; RV32IM-NEXT: add a1, a2, a1935; RV32IM-NEXT: sub a0, a3, a0936; RV32IM-NEXT: ret937;938; RV64I-LABEL: muli64_p63:939; RV64I: # %bb.0:940; RV64I-NEXT: slli a1, a0, 6941; RV64I-NEXT: sub a0, a1, a0942; RV64I-NEXT: ret943;944; RV64IM-LABEL: muli64_p63:945; RV64IM: # %bb.0:946; RV64IM-NEXT: slli a1, a0, 6947; RV64IM-NEXT: sub a0, a1, a0948; RV64IM-NEXT: ret949 %1 = mul i64 %a, 63950 ret i64 %1951}952 953define i64 @muli64_p72(i64 %a) nounwind {954; RV32I-LABEL: muli64_p72:955; RV32I: # %bb.0:956; RV32I-NEXT: addi sp, sp, -16957; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill958; RV32I-NEXT: li a2, 72959; RV32I-NEXT: li a3, 0960; RV32I-NEXT: call __muldi3961; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload962; RV32I-NEXT: addi sp, sp, 16963; RV32I-NEXT: ret964;965; RV32IM-LABEL: muli64_p72:966; RV32IM: # %bb.0:967; RV32IM-NEXT: li a2, 72968; RV32IM-NEXT: slli a3, a1, 3969; RV32IM-NEXT: slli a1, a1, 6970; RV32IM-NEXT: add a1, a1, a3971; RV32IM-NEXT: slli a3, a0, 3972; RV32IM-NEXT: mulhu a2, a0, a2973; RV32IM-NEXT: slli a0, a0, 6974; RV32IM-NEXT: add a1, a2, a1975; RV32IM-NEXT: add a0, a0, a3976; RV32IM-NEXT: ret977;978; RV64I-LABEL: muli64_p72:979; RV64I: # %bb.0:980; RV64I-NEXT: slli a1, a0, 3981; RV64I-NEXT: slli a0, a0, 6982; RV64I-NEXT: add a0, a0, a1983; RV64I-NEXT: ret984;985; RV64IM-LABEL: muli64_p72:986; RV64IM: # %bb.0:987; RV64IM-NEXT: slli a1, a0, 3988; RV64IM-NEXT: slli a0, a0, 6989; RV64IM-NEXT: add a0, a0, a1990; RV64IM-NEXT: ret991 %1 = mul i64 %a, 72992 ret i64 %1993}994 995define i64 @muli64_p68(i64 %a) nounwind {996; RV32I-LABEL: muli64_p68:997; RV32I: # %bb.0:998; RV32I-NEXT: addi sp, sp, -16999; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1000; RV32I-NEXT: li a2, 681001; RV32I-NEXT: li a3, 01002; RV32I-NEXT: call __muldi31003; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1004; RV32I-NEXT: addi sp, sp, 161005; RV32I-NEXT: ret1006;1007; RV32IM-LABEL: muli64_p68:1008; RV32IM: # %bb.0:1009; RV32IM-NEXT: li a2, 681010; RV32IM-NEXT: slli a3, a1, 21011; RV32IM-NEXT: slli a1, a1, 61012; RV32IM-NEXT: add a1, a1, a31013; RV32IM-NEXT: slli a3, a0, 21014; RV32IM-NEXT: mulhu a2, a0, a21015; RV32IM-NEXT: slli a0, a0, 61016; RV32IM-NEXT: add a1, a2, a11017; RV32IM-NEXT: add a0, a0, a31018; RV32IM-NEXT: ret1019;1020; RV64I-LABEL: muli64_p68:1021; RV64I: # %bb.0:1022; RV64I-NEXT: slli a1, a0, 21023; RV64I-NEXT: slli a0, a0, 61024; RV64I-NEXT: add a0, a0, a11025; RV64I-NEXT: ret1026;1027; RV64IM-LABEL: muli64_p68:1028; RV64IM: # %bb.0:1029; RV64IM-NEXT: slli a1, a0, 21030; RV64IM-NEXT: slli a0, a0, 61031; RV64IM-NEXT: add a0, a0, a11032; RV64IM-NEXT: ret1033 %1 = mul i64 %a, 681034 ret i64 %11035}1036 1037define i32 @muli32_m63(i32 %a) nounwind {1038; RV32I-LABEL: muli32_m63:1039; RV32I: # %bb.0:1040; RV32I-NEXT: slli a1, a0, 61041; RV32I-NEXT: sub a0, a0, a11042; RV32I-NEXT: ret1043;1044; RV32IM-LABEL: muli32_m63:1045; RV32IM: # %bb.0:1046; RV32IM-NEXT: slli a1, a0, 61047; RV32IM-NEXT: sub a0, a0, a11048; RV32IM-NEXT: ret1049;1050; RV64I-LABEL: muli32_m63:1051; RV64I: # %bb.0:1052; RV64I-NEXT: slli a1, a0, 61053; RV64I-NEXT: subw a0, a0, a11054; RV64I-NEXT: ret1055;1056; RV64IM-LABEL: muli32_m63:1057; RV64IM: # %bb.0:1058; RV64IM-NEXT: slli a1, a0, 61059; RV64IM-NEXT: subw a0, a0, a11060; RV64IM-NEXT: ret1061 %1 = mul i32 %a, -631062 ret i32 %11063}1064 1065define i32 @muli32_m65(i32 %a) nounwind {1066; RV32I-LABEL: muli32_m65:1067; RV32I: # %bb.0:1068; RV32I-NEXT: slli a1, a0, 61069; RV32I-NEXT: neg a0, a01070; RV32I-NEXT: sub a0, a0, a11071; RV32I-NEXT: ret1072;1073; RV32IM-LABEL: muli32_m65:1074; RV32IM: # %bb.0:1075; RV32IM-NEXT: slli a1, a0, 61076; RV32IM-NEXT: neg a0, a01077; RV32IM-NEXT: sub a0, a0, a11078; RV32IM-NEXT: ret1079;1080; RV64I-LABEL: muli32_m65:1081; RV64I: # %bb.0:1082; RV64I-NEXT: slli a1, a0, 61083; RV64I-NEXT: neg a0, a01084; RV64I-NEXT: subw a0, a0, a11085; RV64I-NEXT: ret1086;1087; RV64IM-LABEL: muli32_m65:1088; RV64IM: # %bb.0:1089; RV64IM-NEXT: slli a1, a0, 61090; RV64IM-NEXT: neg a0, a01091; RV64IM-NEXT: subw a0, a0, a11092; RV64IM-NEXT: ret1093 %1 = mul i32 %a, -651094 ret i32 %11095}1096 1097define i64 @muli64_m63(i64 %a) nounwind {1098; RV32I-LABEL: muli64_m63:1099; RV32I: # %bb.0:1100; RV32I-NEXT: slli a2, a0, 61101; RV32I-NEXT: srli a3, a0, 261102; RV32I-NEXT: slli a4, a1, 61103; RV32I-NEXT: sltu a5, a0, a21104; RV32I-NEXT: or a3, a4, a31105; RV32I-NEXT: sub a1, a1, a31106; RV32I-NEXT: sub a1, a1, a51107; RV32I-NEXT: sub a0, a0, a21108; RV32I-NEXT: ret1109;1110; RV32IM-LABEL: muli64_m63:1111; RV32IM: # %bb.0:1112; RV32IM-NEXT: slli a2, a1, 61113; RV32IM-NEXT: sub a1, a1, a21114; RV32IM-NEXT: li a2, -631115; RV32IM-NEXT: mulhu a2, a0, a21116; RV32IM-NEXT: sub a2, a2, a01117; RV32IM-NEXT: add a1, a2, a11118; RV32IM-NEXT: slli a2, a0, 61119; RV32IM-NEXT: sub a0, a0, a21120; RV32IM-NEXT: ret1121;1122; RV64I-LABEL: muli64_m63:1123; RV64I: # %bb.0:1124; RV64I-NEXT: slli a1, a0, 61125; RV64I-NEXT: sub a0, a0, a11126; RV64I-NEXT: ret1127;1128; RV64IM-LABEL: muli64_m63:1129; RV64IM: # %bb.0:1130; RV64IM-NEXT: slli a1, a0, 61131; RV64IM-NEXT: sub a0, a0, a11132; RV64IM-NEXT: ret1133 %1 = mul i64 %a, -631134 ret i64 %11135}1136 1137define i64 @muli64_m65(i64 %a) nounwind {1138; RV32I-LABEL: muli64_m65:1139; RV32I: # %bb.0:1140; RV32I-NEXT: slli a2, a0, 61141; RV32I-NEXT: srli a3, a0, 261142; RV32I-NEXT: slli a4, a1, 61143; RV32I-NEXT: add a0, a2, a01144; RV32I-NEXT: or a3, a4, a31145; RV32I-NEXT: sltu a2, a0, a21146; RV32I-NEXT: add a1, a3, a11147; RV32I-NEXT: snez a3, a01148; RV32I-NEXT: add a1, a1, a21149; RV32I-NEXT: neg a2, a31150; RV32I-NEXT: sub a1, a2, a11151; RV32I-NEXT: neg a0, a01152; RV32I-NEXT: ret1153;1154; RV32IM-LABEL: muli64_m65:1155; RV32IM: # %bb.0:1156; RV32IM-NEXT: slli a2, a1, 61157; RV32IM-NEXT: add a1, a2, a11158; RV32IM-NEXT: li a2, -651159; RV32IM-NEXT: mulhu a2, a0, a21160; RV32IM-NEXT: sub a2, a2, a01161; RV32IM-NEXT: sub a1, a2, a11162; RV32IM-NEXT: slli a2, a0, 61163; RV32IM-NEXT: neg a0, a01164; RV32IM-NEXT: sub a0, a0, a21165; RV32IM-NEXT: ret1166;1167; RV64I-LABEL: muli64_m65:1168; RV64I: # %bb.0:1169; RV64I-NEXT: slli a1, a0, 61170; RV64I-NEXT: neg a0, a01171; RV64I-NEXT: sub a0, a0, a11172; RV64I-NEXT: ret1173;1174; RV64IM-LABEL: muli64_m65:1175; RV64IM: # %bb.0:1176; RV64IM-NEXT: slli a1, a0, 61177; RV64IM-NEXT: neg a0, a01178; RV64IM-NEXT: sub a0, a0, a11179; RV64IM-NEXT: ret1180 %1 = mul i64 %a, -651181 ret i64 %11182}1183 1184define i32 @muli32_p384(i32 %a) nounwind {1185; RV32I-LABEL: muli32_p384:1186; RV32I: # %bb.0:1187; RV32I-NEXT: slli a1, a0, 71188; RV32I-NEXT: slli a0, a0, 81189; RV32I-NEXT: add a0, a0, a11190; RV32I-NEXT: ret1191;1192; RV32IM-LABEL: muli32_p384:1193; RV32IM: # %bb.0:1194; RV32IM-NEXT: slli a1, a0, 71195; RV32IM-NEXT: slli a0, a0, 81196; RV32IM-NEXT: add a0, a0, a11197; RV32IM-NEXT: ret1198;1199; RV64I-LABEL: muli32_p384:1200; RV64I: # %bb.0:1201; RV64I-NEXT: slli a1, a0, 71202; RV64I-NEXT: slli a0, a0, 81203; RV64I-NEXT: add a0, a0, a11204; RV64I-NEXT: ret1205;1206; RV64IM-LABEL: muli32_p384:1207; RV64IM: # %bb.0:1208; RV64IM-NEXT: slli a1, a0, 71209; RV64IM-NEXT: slli a0, a0, 81210; RV64IM-NEXT: addw a0, a0, a11211; RV64IM-NEXT: ret1212 %1 = mul i32 %a, 3841213 ret i32 %11214}1215 1216define i32 @muli32_p12288(i32 %a) nounwind {1217; RV32I-LABEL: muli32_p12288:1218; RV32I: # %bb.0:1219; RV32I-NEXT: slli a1, a0, 121220; RV32I-NEXT: slli a0, a0, 131221; RV32I-NEXT: add a0, a0, a11222; RV32I-NEXT: ret1223;1224; RV32IM-LABEL: muli32_p12288:1225; RV32IM: # %bb.0:1226; RV32IM-NEXT: slli a1, a0, 121227; RV32IM-NEXT: slli a0, a0, 131228; RV32IM-NEXT: add a0, a0, a11229; RV32IM-NEXT: ret1230;1231; RV64I-LABEL: muli32_p12288:1232; RV64I: # %bb.0:1233; RV64I-NEXT: slli a1, a0, 121234; RV64I-NEXT: slli a0, a0, 131235; RV64I-NEXT: add a0, a0, a11236; RV64I-NEXT: ret1237;1238; RV64IM-LABEL: muli32_p12288:1239; RV64IM: # %bb.0:1240; RV64IM-NEXT: slli a1, a0, 121241; RV64IM-NEXT: slli a0, a0, 131242; RV64IM-NEXT: addw a0, a0, a11243; RV64IM-NEXT: ret1244 %1 = mul i32 %a, 122881245 ret i32 %11246}1247 1248define i32 @muli32_p4352(i32 %a) nounwind {1249; RV32I-LABEL: muli32_p4352:1250; RV32I: # %bb.0:1251; RV32I-NEXT: slli a1, a0, 81252; RV32I-NEXT: slli a0, a0, 121253; RV32I-NEXT: add a0, a0, a11254; RV32I-NEXT: ret1255;1256; RV32IM-LABEL: muli32_p4352:1257; RV32IM: # %bb.0:1258; RV32IM-NEXT: slli a1, a0, 81259; RV32IM-NEXT: slli a0, a0, 121260; RV32IM-NEXT: add a0, a0, a11261; RV32IM-NEXT: ret1262;1263; RV64I-LABEL: muli32_p4352:1264; RV64I: # %bb.0:1265; RV64I-NEXT: slli a1, a0, 81266; RV64I-NEXT: slli a0, a0, 121267; RV64I-NEXT: addw a0, a0, a11268; RV64I-NEXT: ret1269;1270; RV64IM-LABEL: muli32_p4352:1271; RV64IM: # %bb.0:1272; RV64IM-NEXT: slli a1, a0, 81273; RV64IM-NEXT: slli a0, a0, 121274; RV64IM-NEXT: addw a0, a0, a11275; RV64IM-NEXT: ret1276 %1 = mul i32 %a, 43521277 ret i32 %11278}1279 1280define i32 @muli32_p3840(i32 %a) nounwind {1281; RV32I-LABEL: muli32_p3840:1282; RV32I: # %bb.0:1283; RV32I-NEXT: slli a1, a0, 81284; RV32I-NEXT: slli a0, a0, 121285; RV32I-NEXT: sub a0, a0, a11286; RV32I-NEXT: ret1287;1288; RV32IM-LABEL: muli32_p3840:1289; RV32IM: # %bb.0:1290; RV32IM-NEXT: slli a1, a0, 81291; RV32IM-NEXT: slli a0, a0, 121292; RV32IM-NEXT: sub a0, a0, a11293; RV32IM-NEXT: ret1294;1295; RV64I-LABEL: muli32_p3840:1296; RV64I: # %bb.0:1297; RV64I-NEXT: slli a1, a0, 81298; RV64I-NEXT: slli a0, a0, 121299; RV64I-NEXT: subw a0, a0, a11300; RV64I-NEXT: ret1301;1302; RV64IM-LABEL: muli32_p3840:1303; RV64IM: # %bb.0:1304; RV64IM-NEXT: slli a1, a0, 81305; RV64IM-NEXT: slli a0, a0, 121306; RV64IM-NEXT: subw a0, a0, a11307; RV64IM-NEXT: ret1308 %1 = mul i32 %a, 38401309 ret i32 %11310}1311 1312define i32 @muli32_m3840(i32 %a) nounwind {1313; RV32I-LABEL: muli32_m3840:1314; RV32I: # %bb.0:1315; RV32I-NEXT: slli a1, a0, 121316; RV32I-NEXT: slli a0, a0, 81317; RV32I-NEXT: sub a0, a0, a11318; RV32I-NEXT: ret1319;1320; RV32IM-LABEL: muli32_m3840:1321; RV32IM: # %bb.0:1322; RV32IM-NEXT: slli a1, a0, 121323; RV32IM-NEXT: slli a0, a0, 81324; RV32IM-NEXT: sub a0, a0, a11325; RV32IM-NEXT: ret1326;1327; RV64I-LABEL: muli32_m3840:1328; RV64I: # %bb.0:1329; RV64I-NEXT: slli a1, a0, 121330; RV64I-NEXT: slli a0, a0, 81331; RV64I-NEXT: subw a0, a0, a11332; RV64I-NEXT: ret1333;1334; RV64IM-LABEL: muli32_m3840:1335; RV64IM: # %bb.0:1336; RV64IM-NEXT: slli a1, a0, 121337; RV64IM-NEXT: slli a0, a0, 81338; RV64IM-NEXT: subw a0, a0, a11339; RV64IM-NEXT: ret1340 %1 = mul i32 %a, -38401341 ret i32 %11342}1343 1344define i32 @muli32_m4352(i32 %a) nounwind {1345; RV32I-LABEL: muli32_m4352:1346; RV32I: # %bb.0:1347; RV32I-NEXT: slli a1, a0, 121348; RV32I-NEXT: slli a0, a0, 81349; RV32I-NEXT: add a0, a0, a11350; RV32I-NEXT: neg a0, a01351; RV32I-NEXT: ret1352;1353; RV32IM-LABEL: muli32_m4352:1354; RV32IM: # %bb.0:1355; RV32IM-NEXT: li a1, -171356; RV32IM-NEXT: slli a1, a1, 81357; RV32IM-NEXT: mul a0, a0, a11358; RV32IM-NEXT: ret1359;1360; RV64I-LABEL: muli32_m4352:1361; RV64I: # %bb.0:1362; RV64I-NEXT: slli a1, a0, 121363; RV64I-NEXT: slli a0, a0, 81364; RV64I-NEXT: add a0, a0, a11365; RV64I-NEXT: neg a0, a01366; RV64I-NEXT: ret1367;1368; RV64IM-LABEL: muli32_m4352:1369; RV64IM: # %bb.0:1370; RV64IM-NEXT: li a1, -171371; RV64IM-NEXT: slli a1, a1, 81372; RV64IM-NEXT: mulw a0, a0, a11373; RV64IM-NEXT: ret1374 %1 = mul i32 %a, -43521375 ret i32 %11376}1377 1378define i64 @muli64_p4352(i64 %a) nounwind {1379; RV32I-LABEL: muli64_p4352:1380; RV32I: # %bb.0:1381; RV32I-NEXT: srli a2, a0, 241382; RV32I-NEXT: slli a3, a1, 81383; RV32I-NEXT: or a2, a3, a21384; RV32I-NEXT: srli a3, a0, 201385; RV32I-NEXT: slli a1, a1, 121386; RV32I-NEXT: or a1, a1, a31387; RV32I-NEXT: slli a3, a0, 81388; RV32I-NEXT: slli a4, a0, 121389; RV32I-NEXT: add a0, a4, a31390; RV32I-NEXT: add a1, a1, a21391; RV32I-NEXT: sltu a2, a0, a41392; RV32I-NEXT: add a1, a1, a21393; RV32I-NEXT: ret1394;1395; RV32IM-LABEL: muli64_p4352:1396; RV32IM: # %bb.0:1397; RV32IM-NEXT: slli a2, a1, 81398; RV32IM-NEXT: slli a1, a1, 121399; RV32IM-NEXT: add a1, a1, a21400; RV32IM-NEXT: li a2, 171401; RV32IM-NEXT: slli a2, a2, 81402; RV32IM-NEXT: mulhu a2, a0, a21403; RV32IM-NEXT: add a1, a2, a11404; RV32IM-NEXT: slli a2, a0, 81405; RV32IM-NEXT: slli a0, a0, 121406; RV32IM-NEXT: add a0, a0, a21407; RV32IM-NEXT: ret1408;1409; RV64I-LABEL: muli64_p4352:1410; RV64I: # %bb.0:1411; RV64I-NEXT: slli a1, a0, 81412; RV64I-NEXT: slli a0, a0, 121413; RV64I-NEXT: add a0, a0, a11414; RV64I-NEXT: ret1415;1416; RV64IM-LABEL: muli64_p4352:1417; RV64IM: # %bb.0:1418; RV64IM-NEXT: slli a1, a0, 81419; RV64IM-NEXT: slli a0, a0, 121420; RV64IM-NEXT: add a0, a0, a11421; RV64IM-NEXT: ret1422 %1 = mul i64 %a, 43521423 ret i64 %11424}1425 1426define i64 @muli64_p3840(i64 %a) nounwind {1427; RV32I-LABEL: muli64_p3840:1428; RV32I: # %bb.0:1429; RV32I-NEXT: srli a2, a0, 241430; RV32I-NEXT: slli a3, a1, 81431; RV32I-NEXT: or a2, a3, a21432; RV32I-NEXT: srli a3, a0, 201433; RV32I-NEXT: slli a1, a1, 121434; RV32I-NEXT: or a1, a1, a31435; RV32I-NEXT: slli a3, a0, 81436; RV32I-NEXT: slli a0, a0, 121437; RV32I-NEXT: sub a1, a1, a21438; RV32I-NEXT: sltu a2, a0, a31439; RV32I-NEXT: sub a1, a1, a21440; RV32I-NEXT: sub a0, a0, a31441; RV32I-NEXT: ret1442;1443; RV32IM-LABEL: muli64_p3840:1444; RV32IM: # %bb.0:1445; RV32IM-NEXT: slli a2, a1, 81446; RV32IM-NEXT: slli a1, a1, 121447; RV32IM-NEXT: sub a1, a1, a21448; RV32IM-NEXT: li a2, 151449; RV32IM-NEXT: slli a2, a2, 81450; RV32IM-NEXT: mulhu a2, a0, a21451; RV32IM-NEXT: add a1, a2, a11452; RV32IM-NEXT: slli a2, a0, 81453; RV32IM-NEXT: slli a0, a0, 121454; RV32IM-NEXT: sub a0, a0, a21455; RV32IM-NEXT: ret1456;1457; RV64I-LABEL: muli64_p3840:1458; RV64I: # %bb.0:1459; RV64I-NEXT: slli a1, a0, 81460; RV64I-NEXT: slli a0, a0, 121461; RV64I-NEXT: sub a0, a0, a11462; RV64I-NEXT: ret1463;1464; RV64IM-LABEL: muli64_p3840:1465; RV64IM: # %bb.0:1466; RV64IM-NEXT: slli a1, a0, 81467; RV64IM-NEXT: slli a0, a0, 121468; RV64IM-NEXT: sub a0, a0, a11469; RV64IM-NEXT: ret1470 %1 = mul i64 %a, 38401471 ret i64 %11472}1473 1474define i64 @muli64_m4352(i64 %a) nounwind {1475; RV32I-LABEL: muli64_m4352:1476; RV32I: # %bb.0:1477; RV32I-NEXT: addi sp, sp, -161478; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1479; RV32I-NEXT: li a2, -171480; RV32I-NEXT: slli a2, a2, 81481; RV32I-NEXT: li a3, -11482; RV32I-NEXT: call __muldi31483; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1484; RV32I-NEXT: addi sp, sp, 161485; RV32I-NEXT: ret1486;1487; RV32IM-LABEL: muli64_m4352:1488; RV32IM: # %bb.0:1489; RV32IM-NEXT: li a2, -171490; RV32IM-NEXT: slli a2, a2, 81491; RV32IM-NEXT: mul a1, a1, a21492; RV32IM-NEXT: mulhu a3, a0, a21493; RV32IM-NEXT: sub a3, a3, a01494; RV32IM-NEXT: add a1, a3, a11495; RV32IM-NEXT: mul a0, a0, a21496; RV32IM-NEXT: ret1497;1498; RV64I-LABEL: muli64_m4352:1499; RV64I: # %bb.0:1500; RV64I-NEXT: slli a1, a0, 121501; RV64I-NEXT: slli a0, a0, 81502; RV64I-NEXT: add a0, a0, a11503; RV64I-NEXT: neg a0, a01504; RV64I-NEXT: ret1505;1506; RV64IM-LABEL: muli64_m4352:1507; RV64IM: # %bb.0:1508; RV64IM-NEXT: li a1, -171509; RV64IM-NEXT: slli a1, a1, 81510; RV64IM-NEXT: mul a0, a0, a11511; RV64IM-NEXT: ret1512 %1 = mul i64 %a, -43521513 ret i64 %11514}1515 1516define i64 @muli64_m3840(i64 %a) nounwind {1517; RV32I-LABEL: muli64_m3840:1518; RV32I: # %bb.0:1519; RV32I-NEXT: srli a2, a0, 201520; RV32I-NEXT: slli a3, a1, 121521; RV32I-NEXT: or a2, a3, a21522; RV32I-NEXT: srli a3, a0, 241523; RV32I-NEXT: slli a1, a1, 81524; RV32I-NEXT: or a1, a1, a31525; RV32I-NEXT: slli a3, a0, 121526; RV32I-NEXT: slli a0, a0, 81527; RV32I-NEXT: sub a1, a1, a21528; RV32I-NEXT: sltu a2, a0, a31529; RV32I-NEXT: sub a1, a1, a21530; RV32I-NEXT: sub a0, a0, a31531; RV32I-NEXT: ret1532;1533; RV32IM-LABEL: muli64_m3840:1534; RV32IM: # %bb.0:1535; RV32IM-NEXT: li a2, -151536; RV32IM-NEXT: slli a2, a2, 81537; RV32IM-NEXT: mul a1, a1, a21538; RV32IM-NEXT: mulhu a3, a0, a21539; RV32IM-NEXT: sub a3, a3, a01540; RV32IM-NEXT: add a1, a3, a11541; RV32IM-NEXT: mul a0, a0, a21542; RV32IM-NEXT: ret1543;1544; RV64I-LABEL: muli64_m3840:1545; RV64I: # %bb.0:1546; RV64I-NEXT: slli a1, a0, 121547; RV64I-NEXT: slli a0, a0, 81548; RV64I-NEXT: sub a0, a0, a11549; RV64I-NEXT: ret1550;1551; RV64IM-LABEL: muli64_m3840:1552; RV64IM: # %bb.0:1553; RV64IM-NEXT: slli a1, a0, 121554; RV64IM-NEXT: slli a0, a0, 81555; RV64IM-NEXT: sub a0, a0, a11556; RV64IM-NEXT: ret1557 %1 = mul i64 %a, -38401558 ret i64 %11559}1560 1561define i128 @muli128_m3840(i128 %a) nounwind {1562; RV32I-LABEL: muli128_m3840:1563; RV32I: # %bb.0:1564; RV32I-NEXT: lw a3, 4(a1)1565; RV32I-NEXT: lw a2, 8(a1)1566; RV32I-NEXT: lw a5, 0(a1)1567; RV32I-NEXT: lw a4, 12(a1)1568; RV32I-NEXT: srli a1, a3, 201569; RV32I-NEXT: slli a6, a2, 121570; RV32I-NEXT: srli a7, a3, 241571; RV32I-NEXT: slli t0, a2, 81572; RV32I-NEXT: srli t1, a2, 201573; RV32I-NEXT: or a1, a6, a11574; RV32I-NEXT: slli a6, a4, 121575; RV32I-NEXT: srli t2, a2, 241576; RV32I-NEXT: slli a4, a4, 81577; RV32I-NEXT: or a2, t0, a71578; RV32I-NEXT: srli a7, a5, 201579; RV32I-NEXT: or a6, a6, t11580; RV32I-NEXT: slli t0, a3, 121581; RV32I-NEXT: or t1, a4, t21582; RV32I-NEXT: srli t2, a5, 241583; RV32I-NEXT: slli t3, a3, 81584; RV32I-NEXT: or a3, t0, a71585; RV32I-NEXT: slli a4, a5, 121586; RV32I-NEXT: slli a5, a5, 81587; RV32I-NEXT: or t0, t3, t21588; RV32I-NEXT: sltu t2, a2, a11589; RV32I-NEXT: sub a6, t1, a61590; RV32I-NEXT: sltu a7, a5, a41591; RV32I-NEXT: sub a6, a6, t21592; RV32I-NEXT: mv t1, a71593; RV32I-NEXT: beq t0, a3, .LBB43_21594; RV32I-NEXT: # %bb.1:1595; RV32I-NEXT: sltu t1, t0, a31596; RV32I-NEXT: .LBB43_2:1597; RV32I-NEXT: sub a2, a2, a11598; RV32I-NEXT: sub a1, t0, a31599; RV32I-NEXT: sub a5, a5, a41600; RV32I-NEXT: sltu a3, a2, t11601; RV32I-NEXT: sub a2, a2, t11602; RV32I-NEXT: sub a1, a1, a71603; RV32I-NEXT: sub a3, a6, a31604; RV32I-NEXT: sw a5, 0(a0)1605; RV32I-NEXT: sw a1, 4(a0)1606; RV32I-NEXT: sw a2, 8(a0)1607; RV32I-NEXT: sw a3, 12(a0)1608; RV32I-NEXT: ret1609;1610; RV32IM-LABEL: muli128_m3840:1611; RV32IM: # %bb.0:1612; RV32IM-NEXT: addi sp, sp, -161613; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1614; RV32IM-NEXT: lw a3, 0(a1)1615; RV32IM-NEXT: lw a2, 4(a1)1616; RV32IM-NEXT: lw a4, 8(a1)1617; RV32IM-NEXT: lw a1, 12(a1)1618; RV32IM-NEXT: li a5, -151619; RV32IM-NEXT: li a6, -11620; RV32IM-NEXT: slli a5, a5, 81621; RV32IM-NEXT: mulhu a7, a3, a51622; RV32IM-NEXT: mul t0, a2, a51623; RV32IM-NEXT: mulhu t1, a2, a51624; RV32IM-NEXT: neg t2, a31625; RV32IM-NEXT: mulhu t3, a3, a61626; RV32IM-NEXT: mul t4, a4, a51627; RV32IM-NEXT: neg t5, a21628; RV32IM-NEXT: mulhu a6, a2, a61629; RV32IM-NEXT: mul a1, a1, a51630; RV32IM-NEXT: mulhu t6, a4, a51631; RV32IM-NEXT: add s0, a3, a21632; RV32IM-NEXT: mul a5, a3, a51633; RV32IM-NEXT: add a7, t0, a71634; RV32IM-NEXT: sub t4, t4, a31635; RV32IM-NEXT: sub a4, t6, a41636; RV32IM-NEXT: sub t6, t3, s01637; RV32IM-NEXT: sltu t0, a7, t01638; RV32IM-NEXT: sub a3, a7, a31639; RV32IM-NEXT: sltu a7, t4, t21640; RV32IM-NEXT: add a1, a4, a11641; RV32IM-NEXT: add t0, t1, t01642; RV32IM-NEXT: sltu a4, a3, t21643; RV32IM-NEXT: add a1, t6, a11644; RV32IM-NEXT: add a4, t3, a41645; RV32IM-NEXT: add a1, a1, a71646; RV32IM-NEXT: add a4, t0, a41647; RV32IM-NEXT: sub a2, a4, a21648; RV32IM-NEXT: sltu a4, a4, t01649; RV32IM-NEXT: add t4, a2, t41650; RV32IM-NEXT: sltu a7, a2, t51651; RV32IM-NEXT: add a4, a6, a41652; RV32IM-NEXT: sltu a2, t4, a21653; RV32IM-NEXT: add a4, a4, a71654; RV32IM-NEXT: add a1, a4, a11655; RV32IM-NEXT: add a1, a1, a21656; RV32IM-NEXT: sw a5, 0(a0)1657; RV32IM-NEXT: sw a3, 4(a0)1658; RV32IM-NEXT: sw t4, 8(a0)1659; RV32IM-NEXT: sw a1, 12(a0)1660; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1661; RV32IM-NEXT: addi sp, sp, 161662; RV32IM-NEXT: ret1663;1664; RV64I-LABEL: muli128_m3840:1665; RV64I: # %bb.0:1666; RV64I-NEXT: srli a2, a0, 521667; RV64I-NEXT: slli a3, a1, 121668; RV64I-NEXT: or a2, a3, a21669; RV64I-NEXT: srli a3, a0, 561670; RV64I-NEXT: slli a1, a1, 81671; RV64I-NEXT: or a1, a1, a31672; RV64I-NEXT: slli a3, a0, 121673; RV64I-NEXT: slli a0, a0, 81674; RV64I-NEXT: sub a1, a1, a21675; RV64I-NEXT: sltu a2, a0, a31676; RV64I-NEXT: sub a1, a1, a21677; RV64I-NEXT: sub a0, a0, a31678; RV64I-NEXT: ret1679;1680; RV64IM-LABEL: muli128_m3840:1681; RV64IM: # %bb.0:1682; RV64IM-NEXT: li a2, -151683; RV64IM-NEXT: slli a2, a2, 81684; RV64IM-NEXT: mul a1, a1, a21685; RV64IM-NEXT: mulhu a3, a0, a21686; RV64IM-NEXT: sub a3, a3, a01687; RV64IM-NEXT: add a1, a3, a11688; RV64IM-NEXT: mul a0, a0, a21689; RV64IM-NEXT: ret1690 %1 = mul i128 %a, -38401691 ret i128 %11692}1693 1694define i128 @muli128_m63(i128 %a) nounwind {1695; RV32I-LABEL: muli128_m63:1696; RV32I: # %bb.0:1697; RV32I-NEXT: lw a3, 0(a1)1698; RV32I-NEXT: lw a4, 4(a1)1699; RV32I-NEXT: lw a2, 8(a1)1700; RV32I-NEXT: lw a1, 12(a1)1701; RV32I-NEXT: slli a6, a3, 61702; RV32I-NEXT: srli a5, a3, 261703; RV32I-NEXT: slli t0, a4, 61704; RV32I-NEXT: sltu a7, a3, a61705; RV32I-NEXT: or t0, t0, a51706; RV32I-NEXT: mv a5, a71707; RV32I-NEXT: beq a4, t0, .LBB44_21708; RV32I-NEXT: # %bb.1:1709; RV32I-NEXT: sltu a5, a4, t01710; RV32I-NEXT: .LBB44_2:1711; RV32I-NEXT: srli t1, a4, 261712; RV32I-NEXT: slli t2, a2, 61713; RV32I-NEXT: srli t3, a2, 261714; RV32I-NEXT: slli t4, a1, 61715; RV32I-NEXT: sub a4, a4, t01716; RV32I-NEXT: sub a3, a3, a61717; RV32I-NEXT: or a6, t2, t11718; RV32I-NEXT: or t0, t4, t31719; RV32I-NEXT: sub a4, a4, a71720; RV32I-NEXT: sub a7, a2, a61721; RV32I-NEXT: sltu a2, a2, a61722; RV32I-NEXT: sub a1, a1, t01723; RV32I-NEXT: sltu a6, a7, a51724; RV32I-NEXT: sub a1, a1, a21725; RV32I-NEXT: sub a2, a7, a51726; RV32I-NEXT: sub a1, a1, a61727; RV32I-NEXT: sw a3, 0(a0)1728; RV32I-NEXT: sw a4, 4(a0)1729; RV32I-NEXT: sw a2, 8(a0)1730; RV32I-NEXT: sw a1, 12(a0)1731; RV32I-NEXT: ret1732;1733; RV32IM-LABEL: muli128_m63:1734; RV32IM: # %bb.0:1735; RV32IM-NEXT: addi sp, sp, -161736; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1737; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill1738; RV32IM-NEXT: lw a3, 0(a1)1739; RV32IM-NEXT: lw a2, 4(a1)1740; RV32IM-NEXT: lw a4, 8(a1)1741; RV32IM-NEXT: lw a1, 12(a1)1742; RV32IM-NEXT: li a5, -631743; RV32IM-NEXT: li a6, -11744; RV32IM-NEXT: mulhu a7, a3, a51745; RV32IM-NEXT: slli t0, a2, 61746; RV32IM-NEXT: mulhu t1, a2, a51747; RV32IM-NEXT: neg t2, a31748; RV32IM-NEXT: mulhu t3, a3, a61749; RV32IM-NEXT: slli t4, a4, 61750; RV32IM-NEXT: sub t5, a4, a31751; RV32IM-NEXT: neg t6, a21752; RV32IM-NEXT: mulhu a6, a2, a61753; RV32IM-NEXT: slli s0, a1, 61754; RV32IM-NEXT: mulhu a5, a4, a51755; RV32IM-NEXT: add s1, a3, a21756; RV32IM-NEXT: sub t4, t5, t41757; RV32IM-NEXT: slli t5, a3, 61758; RV32IM-NEXT: sub t0, a2, t01759; RV32IM-NEXT: sub a1, a1, s01760; RV32IM-NEXT: sub a5, a5, a41761; RV32IM-NEXT: sub a4, t3, s11762; RV32IM-NEXT: sub t5, a3, t51763; RV32IM-NEXT: add a7, t0, a71764; RV32IM-NEXT: sltu s0, t4, t21765; RV32IM-NEXT: add a1, a5, a11766; RV32IM-NEXT: sltu a5, a7, t01767; RV32IM-NEXT: sub a3, a7, a31768; RV32IM-NEXT: add a1, a4, a11769; RV32IM-NEXT: add a5, t1, a51770; RV32IM-NEXT: sltu a4, a3, t21771; RV32IM-NEXT: add a1, a1, s01772; RV32IM-NEXT: add a4, t3, a41773; RV32IM-NEXT: add a4, a5, a41774; RV32IM-NEXT: sub a2, a4, a21775; RV32IM-NEXT: sltu a4, a4, a51776; RV32IM-NEXT: add t4, a2, t41777; RV32IM-NEXT: sltu a5, a2, t61778; RV32IM-NEXT: add a4, a6, a41779; RV32IM-NEXT: sltu a2, t4, a21780; RV32IM-NEXT: add a4, a4, a51781; RV32IM-NEXT: add a1, a4, a11782; RV32IM-NEXT: add a1, a1, a21783; RV32IM-NEXT: sw t5, 0(a0)1784; RV32IM-NEXT: sw a3, 4(a0)1785; RV32IM-NEXT: sw t4, 8(a0)1786; RV32IM-NEXT: sw a1, 12(a0)1787; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1788; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload1789; RV32IM-NEXT: addi sp, sp, 161790; RV32IM-NEXT: ret1791;1792; RV64I-LABEL: muli128_m63:1793; RV64I: # %bb.0:1794; RV64I-NEXT: slli a2, a0, 61795; RV64I-NEXT: srli a3, a0, 581796; RV64I-NEXT: slli a4, a1, 61797; RV64I-NEXT: sltu a5, a0, a21798; RV64I-NEXT: or a3, a4, a31799; RV64I-NEXT: sub a1, a1, a31800; RV64I-NEXT: sub a1, a1, a51801; RV64I-NEXT: sub a0, a0, a21802; RV64I-NEXT: ret1803;1804; RV64IM-LABEL: muli128_m63:1805; RV64IM: # %bb.0:1806; RV64IM-NEXT: slli a2, a1, 61807; RV64IM-NEXT: sub a1, a1, a21808; RV64IM-NEXT: li a2, -631809; RV64IM-NEXT: mulhu a2, a0, a21810; RV64IM-NEXT: sub a2, a2, a01811; RV64IM-NEXT: add a1, a2, a11812; RV64IM-NEXT: slli a2, a0, 61813; RV64IM-NEXT: sub a0, a0, a21814; RV64IM-NEXT: ret1815 %1 = mul i128 %a, -631816 ret i128 %11817}1818 1819define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {1820; RV32I-LABEL: mulhsu_i64:1821; RV32I: # %bb.0:1822; RV32I-NEXT: addi sp, sp, -481823; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill1824; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill1825; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill1826; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill1827; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill1828; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill1829; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill1830; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill1831; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill1832; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill1833; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill1834; RV32I-NEXT: mv s2, a31835; RV32I-NEXT: mv s3, a21836; RV32I-NEXT: mv s0, a11837; RV32I-NEXT: mv s1, a01838; RV32I-NEXT: srai s4, a3, 311839; RV32I-NEXT: li a1, 01840; RV32I-NEXT: li a3, 01841; RV32I-NEXT: call __muldi31842; RV32I-NEXT: mv s5, a11843; RV32I-NEXT: mv a0, s01844; RV32I-NEXT: li a1, 01845; RV32I-NEXT: mv a2, s31846; RV32I-NEXT: li a3, 01847; RV32I-NEXT: call __muldi31848; RV32I-NEXT: add s5, a0, s51849; RV32I-NEXT: sltu a0, s5, a01850; RV32I-NEXT: add s7, a1, a01851; RV32I-NEXT: mv a0, s11852; RV32I-NEXT: li a1, 01853; RV32I-NEXT: mv a2, s21854; RV32I-NEXT: li a3, 01855; RV32I-NEXT: call __muldi31856; RV32I-NEXT: add s5, a0, s51857; RV32I-NEXT: sltu a0, s5, a01858; RV32I-NEXT: add a0, a1, a01859; RV32I-NEXT: add s8, s7, a01860; RV32I-NEXT: mv a0, s01861; RV32I-NEXT: li a1, 01862; RV32I-NEXT: mv a2, s21863; RV32I-NEXT: li a3, 01864; RV32I-NEXT: call __muldi31865; RV32I-NEXT: mv s5, a01866; RV32I-NEXT: mv s6, a11867; RV32I-NEXT: add s9, a0, s81868; RV32I-NEXT: mv a0, s31869; RV32I-NEXT: mv a1, s21870; RV32I-NEXT: li a2, 01871; RV32I-NEXT: li a3, 01872; RV32I-NEXT: call __muldi31873; RV32I-NEXT: mv s2, a01874; RV32I-NEXT: mv s3, a11875; RV32I-NEXT: mv a0, s41876; RV32I-NEXT: mv a1, s41877; RV32I-NEXT: mv a2, s11878; RV32I-NEXT: mv a3, s01879; RV32I-NEXT: call __muldi31880; RV32I-NEXT: add s2, a0, s21881; RV32I-NEXT: sltu a3, s9, s51882; RV32I-NEXT: sltu a4, s8, s71883; RV32I-NEXT: add a1, a1, s31884; RV32I-NEXT: add a2, s9, s21885; RV32I-NEXT: add a4, s6, a41886; RV32I-NEXT: sltu a0, s2, a01887; RV32I-NEXT: sltu a5, a2, s91888; RV32I-NEXT: add a3, a4, a31889; RV32I-NEXT: add a0, a1, a01890; RV32I-NEXT: add a0, a3, a01891; RV32I-NEXT: add a1, a0, a51892; RV32I-NEXT: mv a0, a21893; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload1894; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload1895; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload1896; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload1897; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload1898; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload1899; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload1900; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload1901; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload1902; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload1903; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload1904; RV32I-NEXT: addi sp, sp, 481905; RV32I-NEXT: ret1906;1907; RV32IM-LABEL: mulhsu_i64:1908; RV32IM: # %bb.0:1909; RV32IM-NEXT: srai a4, a3, 311910; RV32IM-NEXT: mulhu a5, a0, a21911; RV32IM-NEXT: mul a6, a1, a21912; RV32IM-NEXT: mulhu a2, a1, a21913; RV32IM-NEXT: mul a7, a0, a31914; RV32IM-NEXT: mulhu t0, a0, a31915; RV32IM-NEXT: mul t1, a1, a31916; RV32IM-NEXT: mulhu a3, a1, a31917; RV32IM-NEXT: add a5, a6, a51918; RV32IM-NEXT: mul t2, a4, a01919; RV32IM-NEXT: mul a1, a4, a11920; RV32IM-NEXT: mulhu a0, a4, a01921; RV32IM-NEXT: sltu a4, a5, a61922; RV32IM-NEXT: add a5, a7, a51923; RV32IM-NEXT: add a1, a0, a11924; RV32IM-NEXT: add a2, a2, a41925; RV32IM-NEXT: sltu a0, a5, a71926; RV32IM-NEXT: add a0, t0, a01927; RV32IM-NEXT: add a0, a2, a01928; RV32IM-NEXT: add a4, t1, a01929; RV32IM-NEXT: sltu a2, a0, a21930; RV32IM-NEXT: add a0, a4, t21931; RV32IM-NEXT: sltu a5, a4, t11932; RV32IM-NEXT: add a2, a3, a21933; RV32IM-NEXT: sltu a3, a0, a41934; RV32IM-NEXT: add a2, a2, a51935; RV32IM-NEXT: add a1, a1, t21936; RV32IM-NEXT: add a1, a2, a11937; RV32IM-NEXT: add a1, a1, a31938; RV32IM-NEXT: ret1939;1940; RV64I-LABEL: mulhsu_i64:1941; RV64I: # %bb.0:1942; RV64I-NEXT: addi sp, sp, -161943; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1944; RV64I-NEXT: mv a2, a11945; RV64I-NEXT: srai a3, a1, 631946; RV64I-NEXT: li a1, 01947; RV64I-NEXT: call __multi31948; RV64I-NEXT: mv a0, a11949; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1950; RV64I-NEXT: addi sp, sp, 161951; RV64I-NEXT: ret1952;1953; RV64IM-LABEL: mulhsu_i64:1954; RV64IM: # %bb.0:1955; RV64IM-NEXT: mulhsu a0, a1, a01956; RV64IM-NEXT: ret1957 %1 = zext i64 %a to i1281958 %2 = sext i64 %b to i1281959 %3 = mul i128 %1, %21960 %4 = lshr i128 %3, 641961 %5 = trunc i128 %4 to i641962 ret i64 %51963}1964 1965define i8 @muladd_demand(i8 %x, i8 %y) nounwind {1966; RV32I-LABEL: muladd_demand:1967; RV32I: # %bb.0:1968; RV32I-NEXT: slli a0, a0, 11969; RV32I-NEXT: sub a0, a1, a01970; RV32I-NEXT: andi a0, a0, 151971; RV32I-NEXT: ret1972;1973; RV32IM-LABEL: muladd_demand:1974; RV32IM: # %bb.0:1975; RV32IM-NEXT: slli a0, a0, 11976; RV32IM-NEXT: sub a0, a1, a01977; RV32IM-NEXT: andi a0, a0, 151978; RV32IM-NEXT: ret1979;1980; RV64I-LABEL: muladd_demand:1981; RV64I: # %bb.0:1982; RV64I-NEXT: slli a0, a0, 11983; RV64I-NEXT: sub a0, a1, a01984; RV64I-NEXT: andi a0, a0, 151985; RV64I-NEXT: ret1986;1987; RV64IM-LABEL: muladd_demand:1988; RV64IM: # %bb.0:1989; RV64IM-NEXT: slli a0, a0, 11990; RV64IM-NEXT: sub a0, a1, a01991; RV64IM-NEXT: andi a0, a0, 151992; RV64IM-NEXT: ret1993 %m = mul i8 %x, 141994 %a = add i8 %y, %m1995 %r = and i8 %a, 151996 ret i8 %r1997}1998 1999define i8 @mulsub_demand(i8 %x, i8 %y) nounwind {2000; RV32I-LABEL: mulsub_demand:2001; RV32I: # %bb.0:2002; RV32I-NEXT: slli a0, a0, 12003; RV32I-NEXT: add a0, a1, a02004; RV32I-NEXT: andi a0, a0, 152005; RV32I-NEXT: ret2006;2007; RV32IM-LABEL: mulsub_demand:2008; RV32IM: # %bb.0:2009; RV32IM-NEXT: slli a0, a0, 12010; RV32IM-NEXT: add a0, a1, a02011; RV32IM-NEXT: andi a0, a0, 152012; RV32IM-NEXT: ret2013;2014; RV64I-LABEL: mulsub_demand:2015; RV64I: # %bb.0:2016; RV64I-NEXT: slli a0, a0, 12017; RV64I-NEXT: add a0, a1, a02018; RV64I-NEXT: andi a0, a0, 152019; RV64I-NEXT: ret2020;2021; RV64IM-LABEL: mulsub_demand:2022; RV64IM: # %bb.0:2023; RV64IM-NEXT: slli a0, a0, 12024; RV64IM-NEXT: add a0, a1, a02025; RV64IM-NEXT: andi a0, a0, 152026; RV64IM-NEXT: ret2027 %m = mul i8 %x, 142028 %a = sub i8 %y, %m2029 %r = and i8 %a, 152030 ret i8 %r2031}2032 2033define i8 @muladd_demand_2(i8 %x, i8 %y) nounwind {2034; RV32I-LABEL: muladd_demand_2:2035; RV32I: # %bb.0:2036; RV32I-NEXT: slli a0, a0, 12037; RV32I-NEXT: sub a1, a1, a02038; RV32I-NEXT: ori a0, a1, -162039; RV32I-NEXT: ret2040;2041; RV32IM-LABEL: muladd_demand_2:2042; RV32IM: # %bb.0:2043; RV32IM-NEXT: slli a0, a0, 12044; RV32IM-NEXT: sub a1, a1, a02045; RV32IM-NEXT: ori a0, a1, -162046; RV32IM-NEXT: ret2047;2048; RV64I-LABEL: muladd_demand_2:2049; RV64I: # %bb.0:2050; RV64I-NEXT: slli a0, a0, 12051; RV64I-NEXT: sub a1, a1, a02052; RV64I-NEXT: ori a0, a1, -162053; RV64I-NEXT: ret2054;2055; RV64IM-LABEL: muladd_demand_2:2056; RV64IM: # %bb.0:2057; RV64IM-NEXT: slli a0, a0, 12058; RV64IM-NEXT: sub a1, a1, a02059; RV64IM-NEXT: ori a0, a1, -162060; RV64IM-NEXT: ret2061 %m = mul i8 %x, 142062 %a = add i8 %y, %m2063 %r = or i8 %a, 2402064 ret i8 %r2065}2066 2067define i8 @mulsub_demand_2(i8 %x, i8 %y) nounwind {2068; RV32I-LABEL: mulsub_demand_2:2069; RV32I: # %bb.0:2070; RV32I-NEXT: slli a0, a0, 12071; RV32I-NEXT: add a0, a1, a02072; RV32I-NEXT: ori a0, a0, -162073; RV32I-NEXT: ret2074;2075; RV32IM-LABEL: mulsub_demand_2:2076; RV32IM: # %bb.0:2077; RV32IM-NEXT: slli a0, a0, 12078; RV32IM-NEXT: add a0, a1, a02079; RV32IM-NEXT: ori a0, a0, -162080; RV32IM-NEXT: ret2081;2082; RV64I-LABEL: mulsub_demand_2:2083; RV64I: # %bb.0:2084; RV64I-NEXT: slli a0, a0, 12085; RV64I-NEXT: add a0, a1, a02086; RV64I-NEXT: ori a0, a0, -162087; RV64I-NEXT: ret2088;2089; RV64IM-LABEL: mulsub_demand_2:2090; RV64IM: # %bb.0:2091; RV64IM-NEXT: slli a0, a0, 12092; RV64IM-NEXT: add a0, a1, a02093; RV64IM-NEXT: ori a0, a0, -162094; RV64IM-NEXT: ret2095 %m = mul i8 %x, 142096 %a = sub i8 %y, %m2097 %r = or i8 %a, 2402098 ret i8 %r2099}2100 2101define i64 @muland_demand(i64 %x) nounwind {2102; RV32I-LABEL: muland_demand:2103; RV32I: # %bb.0:2104; RV32I-NEXT: addi sp, sp, -162105; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2106; RV32I-NEXT: andi a0, a0, -82107; RV32I-NEXT: slli a1, a1, 22108; RV32I-NEXT: srli a1, a1, 22109; RV32I-NEXT: li a2, 122110; RV32I-NEXT: li a3, 02111; RV32I-NEXT: call __muldi32112; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2113; RV32I-NEXT: addi sp, sp, 162114; RV32I-NEXT: ret2115;2116; RV32IM-LABEL: muland_demand:2117; RV32IM: # %bb.0:2118; RV32IM-NEXT: andi a0, a0, -82119; RV32IM-NEXT: slli a2, a1, 22120; RV32IM-NEXT: slli a1, a1, 32121; RV32IM-NEXT: add a1, a1, a22122; RV32IM-NEXT: li a2, 122123; RV32IM-NEXT: mulhu a2, a0, a22124; RV32IM-NEXT: add a1, a2, a12125; RV32IM-NEXT: slli a2, a0, 22126; RV32IM-NEXT: slli a0, a0, 32127; RV32IM-NEXT: add a0, a0, a22128; RV32IM-NEXT: ret2129;2130; RV64I-LABEL: muland_demand:2131; RV64I: # %bb.0:2132; RV64I-NEXT: li a1, -292133; RV64I-NEXT: srli a1, a1, 22134; RV64I-NEXT: and a0, a0, a12135; RV64I-NEXT: slli a1, a0, 22136; RV64I-NEXT: slli a0, a0, 32137; RV64I-NEXT: add a0, a0, a12138; RV64I-NEXT: ret2139;2140; RV64IM-LABEL: muland_demand:2141; RV64IM: # %bb.0:2142; RV64IM-NEXT: andi a0, a0, -82143; RV64IM-NEXT: slli a1, a0, 22144; RV64IM-NEXT: slli a0, a0, 32145; RV64IM-NEXT: add a0, a0, a12146; RV64IM-NEXT: ret2147 %and = and i64 %x, 46116860184273878962148 %mul = mul i64 %and, 122149 ret i64 %mul2150}2151 2152define i64 @mulzext_demand(i32 signext %x) nounwind {2153; RV32I-LABEL: mulzext_demand:2154; RV32I: # %bb.0:2155; RV32I-NEXT: addi sp, sp, -162156; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill2157; RV32I-NEXT: li a3, 32158; RV32I-NEXT: li a2, 02159; RV32I-NEXT: call __muldi32160; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload2161; RV32I-NEXT: addi sp, sp, 162162; RV32I-NEXT: ret2163;2164; RV32IM-LABEL: mulzext_demand:2165; RV32IM: # %bb.0:2166; RV32IM-NEXT: slli a1, a0, 12167; RV32IM-NEXT: add a1, a1, a02168; RV32IM-NEXT: li a0, 02169; RV32IM-NEXT: ret2170;2171; RV64I-LABEL: mulzext_demand:2172; RV64I: # %bb.0:2173; RV64I-NEXT: slli a1, a0, 322174; RV64I-NEXT: slli a0, a0, 332175; RV64I-NEXT: add a0, a0, a12176; RV64I-NEXT: ret2177;2178; RV64IM-LABEL: mulzext_demand:2179; RV64IM: # %bb.0:2180; RV64IM-NEXT: slli a1, a0, 322181; RV64IM-NEXT: slli a0, a0, 332182; RV64IM-NEXT: add a0, a0, a12183; RV64IM-NEXT: ret2184 %ext = zext i32 %x to i642185 %mul = mul i64 %ext, 128849018882186 ret i64 %mul2187}2188 2189define i32 @mulfshl_demand(i32 signext %x) nounwind {2190; RV32I-LABEL: mulfshl_demand:2191; RV32I: # %bb.0:2192; RV32I-NEXT: srli a0, a0, 112193; RV32I-NEXT: slli a1, a0, 192194; RV32I-NEXT: slli a2, a0, 152195; RV32I-NEXT: slli a3, a0, 212196; RV32I-NEXT: slli a4, a0, 232197; RV32I-NEXT: add a1, a2, a12198; RV32I-NEXT: slli a2, a0, 252199; RV32I-NEXT: add a3, a3, a42200; RV32I-NEXT: slli a4, a0, 272201; RV32I-NEXT: add a2, a2, a42202; RV32I-NEXT: slli a0, a0, 292203; RV32I-NEXT: add a1, a1, a32204; RV32I-NEXT: sub a2, a2, a02205; RV32I-NEXT: sub a0, a1, a22206; RV32I-NEXT: ret2207;2208; RV32IM-LABEL: mulfshl_demand:2209; RV32IM: # %bb.0:2210; RV32IM-NEXT: srli a0, a0, 112211; RV32IM-NEXT: lui a1, 928082212; RV32IM-NEXT: mul a0, a0, a12213; RV32IM-NEXT: ret2214;2215; RV64I-LABEL: mulfshl_demand:2216; RV64I: # %bb.0:2217; RV64I-NEXT: srliw a0, a0, 112218; RV64I-NEXT: slli a1, a0, 192219; RV64I-NEXT: slli a2, a0, 152220; RV64I-NEXT: slli a3, a0, 212221; RV64I-NEXT: slli a4, a0, 232222; RV64I-NEXT: add a1, a2, a12223; RV64I-NEXT: slli a2, a0, 252224; RV64I-NEXT: add a3, a3, a42225; RV64I-NEXT: slli a4, a0, 272226; RV64I-NEXT: add a2, a2, a42227; RV64I-NEXT: slli a0, a0, 292228; RV64I-NEXT: add a1, a1, a32229; RV64I-NEXT: sub a2, a2, a02230; RV64I-NEXT: sub a0, a1, a22231; RV64I-NEXT: ret2232;2233; RV64IM-LABEL: mulfshl_demand:2234; RV64IM: # %bb.0:2235; RV64IM-NEXT: srliw a0, a0, 112236; RV64IM-NEXT: lui a1, 928082237; RV64IM-NEXT: mulw a0, a0, a12238; RV64IM-NEXT: ret2239 %fshl = tail call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 21)2240 %mul = mul i32 %fshl, 3801415682241 ret i32 %mul2242}2243 2244define i32 @mulor_demand(i32 signext %x, i32 signext %y) nounwind {2245; RV32I-LABEL: mulor_demand:2246; RV32I: # %bb.0:2247; RV32I-NEXT: slli a1, a0, 192248; RV32I-NEXT: slli a2, a0, 152249; RV32I-NEXT: slli a3, a0, 212250; RV32I-NEXT: slli a4, a0, 232251; RV32I-NEXT: add a1, a2, a12252; RV32I-NEXT: slli a2, a0, 252253; RV32I-NEXT: add a3, a3, a42254; RV32I-NEXT: slli a4, a0, 272255; RV32I-NEXT: add a2, a2, a42256; RV32I-NEXT: slli a0, a0, 292257; RV32I-NEXT: add a1, a1, a32258; RV32I-NEXT: sub a2, a2, a02259; RV32I-NEXT: sub a0, a1, a22260; RV32I-NEXT: ret2261;2262; RV32IM-LABEL: mulor_demand:2263; RV32IM: # %bb.0:2264; RV32IM-NEXT: lui a1, 928082265; RV32IM-NEXT: mul a0, a0, a12266; RV32IM-NEXT: ret2267;2268; RV64I-LABEL: mulor_demand:2269; RV64I: # %bb.0:2270; RV64I-NEXT: slli a1, a0, 192271; RV64I-NEXT: slli a2, a0, 152272; RV64I-NEXT: slli a3, a0, 212273; RV64I-NEXT: slli a4, a0, 232274; RV64I-NEXT: add a1, a2, a12275; RV64I-NEXT: slli a2, a0, 252276; RV64I-NEXT: add a3, a3, a42277; RV64I-NEXT: slli a4, a0, 272278; RV64I-NEXT: add a2, a2, a42279; RV64I-NEXT: slli a0, a0, 292280; RV64I-NEXT: add a1, a1, a32281; RV64I-NEXT: sub a2, a2, a02282; RV64I-NEXT: sub a0, a1, a22283; RV64I-NEXT: ret2284;2285; RV64IM-LABEL: mulor_demand:2286; RV64IM: # %bb.0:2287; RV64IM-NEXT: lui a1, 928082288; RV64IM-NEXT: mulw a0, a0, a12289; RV64IM-NEXT: ret2290 %mul1 = mul i32 %y, 104857602291 %or = or disjoint i32 %mul1, %x2292 %mul2 = mul i32 %or, 3801415682293 ret i32 %mul22294}2295