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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=RV323; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV644 5define signext i32 @test1(i32 signext %x) nounwind {6; RV32-LABEL: test1:7; RV32: # %bb.0:8; RV32-NEXT: ori a0, a0, 319; RV32-NEXT: slli a0, a0, 1010; RV32-NEXT: ret11;12; RV64-LABEL: test1:13; RV64: # %bb.0:14; RV64-NEXT: ori a0, a0, 3115; RV64-NEXT: slliw a0, a0, 1016; RV64-NEXT: ret17 %or = shl i32 %x, 1018 %shl = or i32 %or, 3174419 ret i32 %shl20}21 22define signext i32 @test2(i32 signext %x) nounwind {23; RV32-LABEL: test2:24; RV32: # %bb.0:25; RV32-NEXT: xori a0, a0, 3126; RV32-NEXT: slli a0, a0, 1027; RV32-NEXT: ret28;29; RV64-LABEL: test2:30; RV64: # %bb.0:31; RV64-NEXT: xori a0, a0, 3132; RV64-NEXT: slliw a0, a0, 1033; RV64-NEXT: ret34 %xor = shl i32 %x, 1035 %shl = xor i32 %xor, 3174436 ret i32 %shl37}38 39define i64 @test3(i64 %x) nounwind {40; RV32-LABEL: test3:41; RV32: # %bb.0:42; RV32-NEXT: andi a1, a0, 24143; RV32-NEXT: slli a1, a1, 844; RV32-NEXT: li a0, 045; RV32-NEXT: ret46;47; RV64-LABEL: test3:48; RV64: # %bb.0:49; RV64-NEXT: andi a0, a0, 24150; RV64-NEXT: slli a0, a0, 4051; RV64-NEXT: ret52 %and = shl i64 %x, 4053 %shl = and i64 %and, 26498230229401654 ret i64 %shl55}56 57define i64 @test4(i64 %x) nounwind {58; RV32-LABEL: test4:59; RV32: # %bb.0:60; RV32-NEXT: ori a1, a0, 24161; RV32-NEXT: slli a1, a1, 862; RV32-NEXT: li a0, 063; RV32-NEXT: ret64;65; RV64-LABEL: test4:66; RV64: # %bb.0:67; RV64-NEXT: ori a0, a0, 24168; RV64-NEXT: slli a0, a0, 4069; RV64-NEXT: ret70 %or = shl i64 %x, 4071 %shl = or i64 %or, 26498230229401672 ret i64 %shl73}74 75define i64 @test5(i64 %x) nounwind {76; RV32-LABEL: test5:77; RV32: # %bb.0:78; RV32-NEXT: ori a1, a0, 3179; RV32-NEXT: slli a1, a1, 880; RV32-NEXT: li a0, 081; RV32-NEXT: ret82;83; RV64-LABEL: test5:84; RV64: # %bb.0:85; RV64-NEXT: ori a0, a0, 3186; RV64-NEXT: slli a0, a0, 4087; RV64-NEXT: ret88 %or = shl i64 %x, 4089 %shl = or i64 %or, 3408486046105690 ret i64 %shl91}92 93define i64 @test6(i64 %x) nounwind {94; RV32-LABEL: test6:95; RV32: # %bb.0:96; RV32-NEXT: xori a1, a0, 24197; RV32-NEXT: slli a1, a1, 898; RV32-NEXT: li a0, 099; RV32-NEXT: ret100;101; RV64-LABEL: test6:102; RV64: # %bb.0:103; RV64-NEXT: xori a0, a0, 241104; RV64-NEXT: slli a0, a0, 40105; RV64-NEXT: ret106 %xor = shl i64 %x, 40107 %shl = xor i64 %xor, 264982302294016108 ret i64 %shl109}110 111define i64 @test7(i64 %x) nounwind {112; RV32-LABEL: test7:113; RV32: # %bb.0:114; RV32-NEXT: xori a1, a0, 31115; RV32-NEXT: slli a1, a1, 8116; RV32-NEXT: li a0, 0117; RV32-NEXT: ret118;119; RV64-LABEL: test7:120; RV64: # %bb.0:121; RV64-NEXT: xori a0, a0, 31122; RV64-NEXT: slli a0, a0, 40123; RV64-NEXT: ret124 %xor = shl i64 %x, 40125 %shl = xor i64 %xor, 34084860461056126 ret i64 %shl127}128 129define i64 @test8(i64 %x) nounwind {130; RV32-LABEL: test8:131; RV32: # %bb.0:132; RV32-NEXT: slli a0, a0, 1133; RV32-NEXT: andi a1, a0, -482134; RV32-NEXT: li a0, 0135; RV32-NEXT: ret136;137; RV64-LABEL: test8:138; RV64: # %bb.0:139; RV64-NEXT: andi a0, a0, -241140; RV64-NEXT: slli a0, a0, 33141; RV64-NEXT: ret142 %xor = shl i64 %x, 33143 %shl = and i64 %xor, -2070174236672144 ret i64 %shl145}146 147define i64 @test9(i64 %x) nounwind {148; RV32-LABEL: test9:149; RV32: # %bb.0:150; RV32-NEXT: slli a0, a0, 1151; RV32-NEXT: ori a1, a0, -482152; RV32-NEXT: li a0, 0153; RV32-NEXT: ret154;155; RV64-LABEL: test9:156; RV64: # %bb.0:157; RV64-NEXT: ori a0, a0, -241158; RV64-NEXT: slli a0, a0, 33159; RV64-NEXT: ret160 %xor = shl i64 %x, 33161 %shl = or i64 %xor, -2070174236672162 ret i64 %shl163}164 165define i64 @test10(i64 %x) nounwind {166; RV32-LABEL: test10:167; RV32: # %bb.0:168; RV32-NEXT: slli a0, a0, 1169; RV32-NEXT: xori a1, a0, -482170; RV32-NEXT: li a0, 0171; RV32-NEXT: ret172;173; RV64-LABEL: test10:174; RV64: # %bb.0:175; RV64-NEXT: xori a0, a0, -241176; RV64-NEXT: slli a0, a0, 33177; RV64-NEXT: ret178 %xor = shl i64 %x, 33179 %shl = xor i64 %xor, -2070174236672180 ret i64 %shl181}182 183define signext i32 @test11(i32 signext %x) nounwind {184; RV32-LABEL: test11:185; RV32: # %bb.0:186; RV32-NEXT: andi a0, a0, -241187; RV32-NEXT: slli a0, a0, 17188; RV32-NEXT: ret189;190; RV64-LABEL: test11:191; RV64: # %bb.0:192; RV64-NEXT: andi a0, a0, -241193; RV64-NEXT: slliw a0, a0, 17194; RV64-NEXT: ret195 %or = shl i32 %x, 17196 %shl = and i32 %or, -31588352197 ret i32 %shl198}199 200define signext i32 @test12(i32 signext %x) nounwind {201; RV32-LABEL: test12:202; RV32: # %bb.0:203; RV32-NEXT: ori a0, a0, -241204; RV32-NEXT: slli a0, a0, 17205; RV32-NEXT: ret206;207; RV64-LABEL: test12:208; RV64: # %bb.0:209; RV64-NEXT: ori a0, a0, -241210; RV64-NEXT: slli a0, a0, 17211; RV64-NEXT: ret212 %or = shl i32 %x, 17213 %shl = or i32 %or, -31588352214 ret i32 %shl215}216 217define signext i32 @test13(i32 signext %x) nounwind {218; RV32-LABEL: test13:219; RV32: # %bb.0:220; RV32-NEXT: xori a0, a0, -241221; RV32-NEXT: slli a0, a0, 17222; RV32-NEXT: ret223;224; RV64-LABEL: test13:225; RV64: # %bb.0:226; RV64-NEXT: xori a0, a0, -241227; RV64-NEXT: slliw a0, a0, 17228; RV64-NEXT: ret229 %or = shl i32 %x, 17230 %shl = xor i32 %or, -31588352231 ret i32 %shl232}233 234; Negative test. Can't transform because the constant has a 1 in the bits235; cleared by the shl.236define signext i32 @test14(i32 signext %x) nounwind {237; RV32-LABEL: test14:238; RV32: # %bb.0:239; RV32-NEXT: slli a0, a0, 10240; RV32-NEXT: lui a1, 8241; RV32-NEXT: addi a1, a1, -1027242; RV32-NEXT: or a0, a0, a1243; RV32-NEXT: ret244;245; RV64-LABEL: test14:246; RV64: # %bb.0:247; RV64-NEXT: slliw a0, a0, 10248; RV64-NEXT: lui a1, 8249; RV64-NEXT: addi a1, a1, -1027250; RV64-NEXT: or a0, a0, a1251; RV64-NEXT: ret252 %or = shl i32 %x, 10253 %shl = or i32 %or, 31741254 ret i32 %shl255}256 257; Negative test. Can't transform because the constant has a 1 in the bits258; cleared by the shl.259define signext i32 @test15(i32 signext %x) nounwind {260; RV32-LABEL: test15:261; RV32: # %bb.0:262; RV32-NEXT: slli a0, a0, 10263; RV32-NEXT: lui a1, 8264; RV32-NEXT: addi a1, a1, -515265; RV32-NEXT: xor a0, a0, a1266; RV32-NEXT: ret267;268; RV64-LABEL: test15:269; RV64: # %bb.0:270; RV64-NEXT: slliw a0, a0, 10271; RV64-NEXT: lui a1, 8272; RV64-NEXT: addi a1, a1, -515273; RV64-NEXT: xor a0, a0, a1274; RV64-NEXT: ret275 %xor = shl i32 %x, 10276 %shl = xor i32 %xor, 32253277 ret i32 %shl278}279