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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefix=RV32I4; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefix=RV32ZBB6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefix=RV64I8; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \9; RUN: | FileCheck %s --check-prefix=RV64ZBB10 11define i32 @neg_abs32(i32 %x) {12; RV32I-LABEL: neg_abs32:13; RV32I: # %bb.0:14; RV32I-NEXT: srai a1, a0, 3115; RV32I-NEXT: xor a0, a0, a116; RV32I-NEXT: sub a0, a1, a017; RV32I-NEXT: ret18;19; RV32ZBB-LABEL: neg_abs32:20; RV32ZBB: # %bb.0:21; RV32ZBB-NEXT: neg a1, a022; RV32ZBB-NEXT: min a0, a0, a123; RV32ZBB-NEXT: ret24;25; RV64I-LABEL: neg_abs32:26; RV64I: # %bb.0:27; RV64I-NEXT: sraiw a1, a0, 3128; RV64I-NEXT: xor a0, a0, a129; RV64I-NEXT: subw a0, a1, a030; RV64I-NEXT: ret31;32; RV64ZBB-LABEL: neg_abs32:33; RV64ZBB: # %bb.0:34; RV64ZBB-NEXT: sraiw a1, a0, 3135; RV64ZBB-NEXT: xor a0, a0, a136; RV64ZBB-NEXT: subw a0, a1, a037; RV64ZBB-NEXT: ret38 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)39 %neg = sub nsw i32 0, %abs40 ret i32 %neg41}42 43define i32 @select_neg_abs32(i32 %x) {44; RV32I-LABEL: select_neg_abs32:45; RV32I: # %bb.0:46; RV32I-NEXT: srai a1, a0, 3147; RV32I-NEXT: xor a0, a0, a148; RV32I-NEXT: sub a0, a1, a049; RV32I-NEXT: ret50;51; RV32ZBB-LABEL: select_neg_abs32:52; RV32ZBB: # %bb.0:53; RV32ZBB-NEXT: neg a1, a054; RV32ZBB-NEXT: min a0, a0, a155; RV32ZBB-NEXT: ret56;57; RV64I-LABEL: select_neg_abs32:58; RV64I: # %bb.0:59; RV64I-NEXT: sraiw a1, a0, 3160; RV64I-NEXT: xor a0, a0, a161; RV64I-NEXT: subw a0, a1, a062; RV64I-NEXT: ret63;64; RV64ZBB-LABEL: select_neg_abs32:65; RV64ZBB: # %bb.0:66; RV64ZBB-NEXT: sraiw a1, a0, 3167; RV64ZBB-NEXT: xor a0, a0, a168; RV64ZBB-NEXT: subw a0, a1, a069; RV64ZBB-NEXT: ret70 %1 = icmp slt i32 %x, 071 %2 = sub nsw i32 0, %x72 %3 = select i1 %1, i32 %x, i32 %273 ret i32 %374}75 76define i64 @neg_abs64(i64 %x) {77; RV32I-LABEL: neg_abs64:78; RV32I: # %bb.0:79; RV32I-NEXT: srai a2, a1, 3180; RV32I-NEXT: xor a0, a0, a281; RV32I-NEXT: xor a1, a1, a282; RV32I-NEXT: sltu a3, a2, a083; RV32I-NEXT: sub a1, a2, a184; RV32I-NEXT: sub a1, a1, a385; RV32I-NEXT: sub a0, a2, a086; RV32I-NEXT: ret87;88; RV32ZBB-LABEL: neg_abs64:89; RV32ZBB: # %bb.0:90; RV32ZBB-NEXT: srai a2, a1, 3191; RV32ZBB-NEXT: xor a0, a0, a292; RV32ZBB-NEXT: xor a1, a1, a293; RV32ZBB-NEXT: sltu a3, a2, a094; RV32ZBB-NEXT: sub a1, a2, a195; RV32ZBB-NEXT: sub a1, a1, a396; RV32ZBB-NEXT: sub a0, a2, a097; RV32ZBB-NEXT: ret98;99; RV64I-LABEL: neg_abs64:100; RV64I: # %bb.0:101; RV64I-NEXT: srai a1, a0, 63102; RV64I-NEXT: xor a0, a0, a1103; RV64I-NEXT: sub a0, a1, a0104; RV64I-NEXT: ret105;106; RV64ZBB-LABEL: neg_abs64:107; RV64ZBB: # %bb.0:108; RV64ZBB-NEXT: neg a1, a0109; RV64ZBB-NEXT: min a0, a0, a1110; RV64ZBB-NEXT: ret111 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)112 %neg = sub nsw i64 0, %abs113 ret i64 %neg114}115 116define i64 @select_neg_abs64(i64 %x) {117; RV32I-LABEL: select_neg_abs64:118; RV32I: # %bb.0:119; RV32I-NEXT: srai a2, a1, 31120; RV32I-NEXT: xor a0, a0, a2121; RV32I-NEXT: xor a1, a1, a2122; RV32I-NEXT: sltu a3, a2, a0123; RV32I-NEXT: sub a1, a2, a1124; RV32I-NEXT: sub a1, a1, a3125; RV32I-NEXT: sub a0, a2, a0126; RV32I-NEXT: ret127;128; RV32ZBB-LABEL: select_neg_abs64:129; RV32ZBB: # %bb.0:130; RV32ZBB-NEXT: srai a2, a1, 31131; RV32ZBB-NEXT: xor a0, a0, a2132; RV32ZBB-NEXT: xor a1, a1, a2133; RV32ZBB-NEXT: sltu a3, a2, a0134; RV32ZBB-NEXT: sub a1, a2, a1135; RV32ZBB-NEXT: sub a1, a1, a3136; RV32ZBB-NEXT: sub a0, a2, a0137; RV32ZBB-NEXT: ret138;139; RV64I-LABEL: select_neg_abs64:140; RV64I: # %bb.0:141; RV64I-NEXT: srai a1, a0, 63142; RV64I-NEXT: xor a0, a0, a1143; RV64I-NEXT: sub a0, a1, a0144; RV64I-NEXT: ret145;146; RV64ZBB-LABEL: select_neg_abs64:147; RV64ZBB: # %bb.0:148; RV64ZBB-NEXT: neg a1, a0149; RV64ZBB-NEXT: min a0, a0, a1150; RV64ZBB-NEXT: ret151 %1 = icmp slt i64 %x, 0152 %2 = sub nsw i64 0, %x153 %3 = select i1 %1, i64 %x, i64 %2154 ret i64 %3155}156 157define i32 @neg_abs32_multiuse(i32 %x, ptr %y) {158; RV32I-LABEL: neg_abs32_multiuse:159; RV32I: # %bb.0:160; RV32I-NEXT: srai a2, a0, 31161; RV32I-NEXT: xor a0, a0, a2162; RV32I-NEXT: sub a2, a0, a2163; RV32I-NEXT: neg a0, a2164; RV32I-NEXT: sw a2, 0(a1)165; RV32I-NEXT: ret166;167; RV32ZBB-LABEL: neg_abs32_multiuse:168; RV32ZBB: # %bb.0:169; RV32ZBB-NEXT: neg a2, a0170; RV32ZBB-NEXT: max a2, a0, a2171; RV32ZBB-NEXT: neg a0, a2172; RV32ZBB-NEXT: sw a2, 0(a1)173; RV32ZBB-NEXT: ret174;175; RV64I-LABEL: neg_abs32_multiuse:176; RV64I: # %bb.0:177; RV64I-NEXT: sraiw a2, a0, 31178; RV64I-NEXT: xor a0, a0, a2179; RV64I-NEXT: sub a2, a0, a2180; RV64I-NEXT: negw a0, a2181; RV64I-NEXT: sw a2, 0(a1)182; RV64I-NEXT: ret183;184; RV64ZBB-LABEL: neg_abs32_multiuse:185; RV64ZBB: # %bb.0:186; RV64ZBB-NEXT: sext.w a0, a0187; RV64ZBB-NEXT: negw a2, a0188; RV64ZBB-NEXT: max a2, a0, a2189; RV64ZBB-NEXT: negw a0, a2190; RV64ZBB-NEXT: sw a2, 0(a1)191; RV64ZBB-NEXT: ret192 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)193 store i32 %abs, ptr %y194 %neg = sub nsw i32 0, %abs195 ret i32 %neg196}197 198define i64 @neg_abs64_multiuse(i64 %x, ptr %y) {199; RV32I-LABEL: neg_abs64_multiuse:200; RV32I: # %bb.0:201; RV32I-NEXT: bgez a1, .LBB5_2202; RV32I-NEXT: # %bb.1:203; RV32I-NEXT: snez a3, a0204; RV32I-NEXT: neg a1, a1205; RV32I-NEXT: sub a1, a1, a3206; RV32I-NEXT: neg a0, a0207; RV32I-NEXT: .LBB5_2:208; RV32I-NEXT: snez a4, a0209; RV32I-NEXT: neg a3, a0210; RV32I-NEXT: add a4, a1, a4211; RV32I-NEXT: neg a4, a4212; RV32I-NEXT: sw a0, 0(a2)213; RV32I-NEXT: sw a1, 4(a2)214; RV32I-NEXT: mv a0, a3215; RV32I-NEXT: mv a1, a4216; RV32I-NEXT: ret217;218; RV32ZBB-LABEL: neg_abs64_multiuse:219; RV32ZBB: # %bb.0:220; RV32ZBB-NEXT: bgez a1, .LBB5_2221; RV32ZBB-NEXT: # %bb.1:222; RV32ZBB-NEXT: snez a3, a0223; RV32ZBB-NEXT: neg a1, a1224; RV32ZBB-NEXT: sub a1, a1, a3225; RV32ZBB-NEXT: neg a0, a0226; RV32ZBB-NEXT: .LBB5_2:227; RV32ZBB-NEXT: snez a4, a0228; RV32ZBB-NEXT: neg a3, a0229; RV32ZBB-NEXT: add a4, a1, a4230; RV32ZBB-NEXT: neg a4, a4231; RV32ZBB-NEXT: sw a0, 0(a2)232; RV32ZBB-NEXT: sw a1, 4(a2)233; RV32ZBB-NEXT: mv a0, a3234; RV32ZBB-NEXT: mv a1, a4235; RV32ZBB-NEXT: ret236;237; RV64I-LABEL: neg_abs64_multiuse:238; RV64I: # %bb.0:239; RV64I-NEXT: srai a2, a0, 63240; RV64I-NEXT: xor a0, a0, a2241; RV64I-NEXT: sub a2, a0, a2242; RV64I-NEXT: neg a0, a2243; RV64I-NEXT: sd a2, 0(a1)244; RV64I-NEXT: ret245;246; RV64ZBB-LABEL: neg_abs64_multiuse:247; RV64ZBB: # %bb.0:248; RV64ZBB-NEXT: neg a2, a0249; RV64ZBB-NEXT: max a2, a0, a2250; RV64ZBB-NEXT: neg a0, a2251; RV64ZBB-NEXT: sd a2, 0(a1)252; RV64ZBB-NEXT: ret253 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)254 store i64 %abs, ptr %y255 %neg = sub nsw i64 0, %abs256 ret i64 %neg257}258 259define i32 @expanded_neg_abs32(i32 %x) {260; RV32I-LABEL: expanded_neg_abs32:261; RV32I: # %bb.0:262; RV32I-NEXT: neg a1, a0263; RV32I-NEXT: blt a0, a1, .LBB6_2264; RV32I-NEXT: # %bb.1:265; RV32I-NEXT: mv a1, a0266; RV32I-NEXT: .LBB6_2:267; RV32I-NEXT: neg a0, a1268; RV32I-NEXT: ret269;270; RV32ZBB-LABEL: expanded_neg_abs32:271; RV32ZBB: # %bb.0:272; RV32ZBB-NEXT: neg a1, a0273; RV32ZBB-NEXT: min a0, a0, a1274; RV32ZBB-NEXT: ret275;276; RV64I-LABEL: expanded_neg_abs32:277; RV64I: # %bb.0:278; RV64I-NEXT: sext.w a1, a0279; RV64I-NEXT: negw a0, a0280; RV64I-NEXT: blt a1, a0, .LBB6_2281; RV64I-NEXT: # %bb.1:282; RV64I-NEXT: mv a0, a1283; RV64I-NEXT: .LBB6_2:284; RV64I-NEXT: negw a0, a0285; RV64I-NEXT: ret286;287; RV64ZBB-LABEL: expanded_neg_abs32:288; RV64ZBB: # %bb.0:289; RV64ZBB-NEXT: sext.w a1, a0290; RV64ZBB-NEXT: negw a0, a0291; RV64ZBB-NEXT: max a0, a0, a1292; RV64ZBB-NEXT: negw a0, a0293; RV64ZBB-NEXT: ret294 %n = sub i32 0, %x295 %t = call i32 @llvm.smax.i32(i32 %n, i32 %x)296 %r = sub i32 0, %t297 ret i32 %r298}299 300define i32 @expanded_neg_abs32_unsigned(i32 %x) {301; RV32I-LABEL: expanded_neg_abs32_unsigned:302; RV32I: # %bb.0:303; RV32I-NEXT: neg a1, a0304; RV32I-NEXT: bltu a0, a1, .LBB7_2305; RV32I-NEXT: # %bb.1:306; RV32I-NEXT: mv a1, a0307; RV32I-NEXT: .LBB7_2:308; RV32I-NEXT: neg a0, a1309; RV32I-NEXT: ret310;311; RV32ZBB-LABEL: expanded_neg_abs32_unsigned:312; RV32ZBB: # %bb.0:313; RV32ZBB-NEXT: neg a1, a0314; RV32ZBB-NEXT: minu a0, a0, a1315; RV32ZBB-NEXT: ret316;317; RV64I-LABEL: expanded_neg_abs32_unsigned:318; RV64I: # %bb.0:319; RV64I-NEXT: sext.w a1, a0320; RV64I-NEXT: negw a0, a0321; RV64I-NEXT: bltu a1, a0, .LBB7_2322; RV64I-NEXT: # %bb.1:323; RV64I-NEXT: mv a0, a1324; RV64I-NEXT: .LBB7_2:325; RV64I-NEXT: negw a0, a0326; RV64I-NEXT: ret327;328; RV64ZBB-LABEL: expanded_neg_abs32_unsigned:329; RV64ZBB: # %bb.0:330; RV64ZBB-NEXT: sext.w a1, a0331; RV64ZBB-NEXT: negw a0, a0332; RV64ZBB-NEXT: maxu a0, a0, a1333; RV64ZBB-NEXT: negw a0, a0334; RV64ZBB-NEXT: ret335 %n = sub i32 0, %x336 %t = call i32 @llvm.umax.i32(i32 %n, i32 %x)337 %r = sub i32 0, %t338 ret i32 %r339}340 341define i64 @expanded_neg_abs64(i64 %x) {342; RV32I-LABEL: expanded_neg_abs64:343; RV32I: # %bb.0:344; RV32I-NEXT: snez a2, a0345; RV32I-NEXT: neg a3, a1346; RV32I-NEXT: sub a2, a3, a2347; RV32I-NEXT: neg a3, a0348; RV32I-NEXT: beq a2, a1, .LBB8_2349; RV32I-NEXT: # %bb.1:350; RV32I-NEXT: slt a4, a1, a2351; RV32I-NEXT: beqz a4, .LBB8_3352; RV32I-NEXT: j .LBB8_4353; RV32I-NEXT: .LBB8_2:354; RV32I-NEXT: sltu a4, a0, a3355; RV32I-NEXT: bnez a4, .LBB8_4356; RV32I-NEXT: .LBB8_3:357; RV32I-NEXT: mv a2, a1358; RV32I-NEXT: mv a3, a0359; RV32I-NEXT: .LBB8_4:360; RV32I-NEXT: snez a0, a3361; RV32I-NEXT: add a0, a2, a0362; RV32I-NEXT: neg a1, a0363; RV32I-NEXT: neg a0, a3364; RV32I-NEXT: ret365;366; RV32ZBB-LABEL: expanded_neg_abs64:367; RV32ZBB: # %bb.0:368; RV32ZBB-NEXT: snez a2, a0369; RV32ZBB-NEXT: neg a3, a1370; RV32ZBB-NEXT: sub a2, a3, a2371; RV32ZBB-NEXT: neg a3, a0372; RV32ZBB-NEXT: beq a2, a1, .LBB8_2373; RV32ZBB-NEXT: # %bb.1:374; RV32ZBB-NEXT: slt a4, a1, a2375; RV32ZBB-NEXT: beqz a4, .LBB8_3376; RV32ZBB-NEXT: j .LBB8_4377; RV32ZBB-NEXT: .LBB8_2:378; RV32ZBB-NEXT: sltu a4, a0, a3379; RV32ZBB-NEXT: bnez a4, .LBB8_4380; RV32ZBB-NEXT: .LBB8_3:381; RV32ZBB-NEXT: mv a2, a1382; RV32ZBB-NEXT: mv a3, a0383; RV32ZBB-NEXT: .LBB8_4:384; RV32ZBB-NEXT: snez a0, a3385; RV32ZBB-NEXT: add a0, a2, a0386; RV32ZBB-NEXT: neg a1, a0387; RV32ZBB-NEXT: neg a0, a3388; RV32ZBB-NEXT: ret389;390; RV64I-LABEL: expanded_neg_abs64:391; RV64I: # %bb.0:392; RV64I-NEXT: neg a1, a0393; RV64I-NEXT: blt a0, a1, .LBB8_2394; RV64I-NEXT: # %bb.1:395; RV64I-NEXT: mv a1, a0396; RV64I-NEXT: .LBB8_2:397; RV64I-NEXT: neg a0, a1398; RV64I-NEXT: ret399;400; RV64ZBB-LABEL: expanded_neg_abs64:401; RV64ZBB: # %bb.0:402; RV64ZBB-NEXT: neg a1, a0403; RV64ZBB-NEXT: min a0, a0, a1404; RV64ZBB-NEXT: ret405 %n = sub i64 0, %x406 %t = call i64 @llvm.smax.i64(i64 %n, i64 %x)407 %r = sub i64 0, %t408 ret i64 %r409}410 411define i64 @expanded_neg_abs64_unsigned(i64 %x) {412; RV32I-LABEL: expanded_neg_abs64_unsigned:413; RV32I: # %bb.0:414; RV32I-NEXT: snez a2, a0415; RV32I-NEXT: neg a3, a1416; RV32I-NEXT: sub a2, a3, a2417; RV32I-NEXT: neg a3, a0418; RV32I-NEXT: beq a2, a1, .LBB9_2419; RV32I-NEXT: # %bb.1:420; RV32I-NEXT: sltu a4, a1, a2421; RV32I-NEXT: beqz a4, .LBB9_3422; RV32I-NEXT: j .LBB9_4423; RV32I-NEXT: .LBB9_2:424; RV32I-NEXT: sltu a4, a0, a3425; RV32I-NEXT: bnez a4, .LBB9_4426; RV32I-NEXT: .LBB9_3:427; RV32I-NEXT: mv a2, a1428; RV32I-NEXT: mv a3, a0429; RV32I-NEXT: .LBB9_4:430; RV32I-NEXT: snez a0, a3431; RV32I-NEXT: add a0, a2, a0432; RV32I-NEXT: neg a1, a0433; RV32I-NEXT: neg a0, a3434; RV32I-NEXT: ret435;436; RV32ZBB-LABEL: expanded_neg_abs64_unsigned:437; RV32ZBB: # %bb.0:438; RV32ZBB-NEXT: snez a2, a0439; RV32ZBB-NEXT: neg a3, a1440; RV32ZBB-NEXT: sub a2, a3, a2441; RV32ZBB-NEXT: neg a3, a0442; RV32ZBB-NEXT: beq a2, a1, .LBB9_2443; RV32ZBB-NEXT: # %bb.1:444; RV32ZBB-NEXT: sltu a4, a1, a2445; RV32ZBB-NEXT: beqz a4, .LBB9_3446; RV32ZBB-NEXT: j .LBB9_4447; RV32ZBB-NEXT: .LBB9_2:448; RV32ZBB-NEXT: sltu a4, a0, a3449; RV32ZBB-NEXT: bnez a4, .LBB9_4450; RV32ZBB-NEXT: .LBB9_3:451; RV32ZBB-NEXT: mv a2, a1452; RV32ZBB-NEXT: mv a3, a0453; RV32ZBB-NEXT: .LBB9_4:454; RV32ZBB-NEXT: snez a0, a3455; RV32ZBB-NEXT: add a0, a2, a0456; RV32ZBB-NEXT: neg a1, a0457; RV32ZBB-NEXT: neg a0, a3458; RV32ZBB-NEXT: ret459;460; RV64I-LABEL: expanded_neg_abs64_unsigned:461; RV64I: # %bb.0:462; RV64I-NEXT: neg a1, a0463; RV64I-NEXT: bltu a0, a1, .LBB9_2464; RV64I-NEXT: # %bb.1:465; RV64I-NEXT: mv a1, a0466; RV64I-NEXT: .LBB9_2:467; RV64I-NEXT: neg a0, a1468; RV64I-NEXT: ret469;470; RV64ZBB-LABEL: expanded_neg_abs64_unsigned:471; RV64ZBB: # %bb.0:472; RV64ZBB-NEXT: neg a1, a0473; RV64ZBB-NEXT: minu a0, a0, a1474; RV64ZBB-NEXT: ret475 %n = sub i64 0, %x476 %t = call i64 @llvm.umax.i64(i64 %n, i64 %x)477 %r = sub i64 0, %t478 ret i64 %r479}480 481define i32 @expanded_neg_inv_abs32(i32 %x) {482; RV32I-LABEL: expanded_neg_inv_abs32:483; RV32I: # %bb.0:484; RV32I-NEXT: neg a1, a0485; RV32I-NEXT: blt a1, a0, .LBB10_2486; RV32I-NEXT: # %bb.1:487; RV32I-NEXT: mv a1, a0488; RV32I-NEXT: .LBB10_2:489; RV32I-NEXT: neg a0, a1490; RV32I-NEXT: ret491;492; RV32ZBB-LABEL: expanded_neg_inv_abs32:493; RV32ZBB: # %bb.0:494; RV32ZBB-NEXT: neg a1, a0495; RV32ZBB-NEXT: max a0, a0, a1496; RV32ZBB-NEXT: ret497;498; RV64I-LABEL: expanded_neg_inv_abs32:499; RV64I: # %bb.0:500; RV64I-NEXT: sext.w a1, a0501; RV64I-NEXT: negw a0, a0502; RV64I-NEXT: blt a0, a1, .LBB10_2503; RV64I-NEXT: # %bb.1:504; RV64I-NEXT: mv a0, a1505; RV64I-NEXT: .LBB10_2:506; RV64I-NEXT: negw a0, a0507; RV64I-NEXT: ret508;509; RV64ZBB-LABEL: expanded_neg_inv_abs32:510; RV64ZBB: # %bb.0:511; RV64ZBB-NEXT: sext.w a1, a0512; RV64ZBB-NEXT: negw a0, a0513; RV64ZBB-NEXT: min a0, a0, a1514; RV64ZBB-NEXT: negw a0, a0515; RV64ZBB-NEXT: ret516 %n = sub i32 0, %x517 %t = call i32 @llvm.smin.i32(i32 %n, i32 %x)518 %r = sub i32 0, %t519 ret i32 %r520}521 522define i32 @expanded_neg_inv_abs32_unsigned(i32 %x) {523; RV32I-LABEL: expanded_neg_inv_abs32_unsigned:524; RV32I: # %bb.0:525; RV32I-NEXT: neg a1, a0526; RV32I-NEXT: bltu a1, a0, .LBB11_2527; RV32I-NEXT: # %bb.1:528; RV32I-NEXT: mv a1, a0529; RV32I-NEXT: .LBB11_2:530; RV32I-NEXT: neg a0, a1531; RV32I-NEXT: ret532;533; RV32ZBB-LABEL: expanded_neg_inv_abs32_unsigned:534; RV32ZBB: # %bb.0:535; RV32ZBB-NEXT: neg a1, a0536; RV32ZBB-NEXT: maxu a0, a0, a1537; RV32ZBB-NEXT: ret538;539; RV64I-LABEL: expanded_neg_inv_abs32_unsigned:540; RV64I: # %bb.0:541; RV64I-NEXT: sext.w a1, a0542; RV64I-NEXT: negw a0, a0543; RV64I-NEXT: bltu a0, a1, .LBB11_2544; RV64I-NEXT: # %bb.1:545; RV64I-NEXT: mv a0, a1546; RV64I-NEXT: .LBB11_2:547; RV64I-NEXT: negw a0, a0548; RV64I-NEXT: ret549;550; RV64ZBB-LABEL: expanded_neg_inv_abs32_unsigned:551; RV64ZBB: # %bb.0:552; RV64ZBB-NEXT: sext.w a1, a0553; RV64ZBB-NEXT: negw a0, a0554; RV64ZBB-NEXT: minu a0, a0, a1555; RV64ZBB-NEXT: negw a0, a0556; RV64ZBB-NEXT: ret557 %n = sub i32 0, %x558 %t = call i32 @llvm.umin.i32(i32 %n, i32 %x)559 %r = sub i32 0, %t560 ret i32 %r561}562 563define i64 @expanded_neg_inv_abs64(i64 %x) {564; RV32I-LABEL: expanded_neg_inv_abs64:565; RV32I: # %bb.0:566; RV32I-NEXT: snez a2, a0567; RV32I-NEXT: neg a3, a1568; RV32I-NEXT: sub a2, a3, a2569; RV32I-NEXT: neg a3, a0570; RV32I-NEXT: beq a2, a1, .LBB12_2571; RV32I-NEXT: # %bb.1:572; RV32I-NEXT: slt a4, a2, a1573; RV32I-NEXT: beqz a4, .LBB12_3574; RV32I-NEXT: j .LBB12_4575; RV32I-NEXT: .LBB12_2:576; RV32I-NEXT: sltu a4, a3, a0577; RV32I-NEXT: bnez a4, .LBB12_4578; RV32I-NEXT: .LBB12_3:579; RV32I-NEXT: mv a2, a1580; RV32I-NEXT: mv a3, a0581; RV32I-NEXT: .LBB12_4:582; RV32I-NEXT: snez a0, a3583; RV32I-NEXT: add a0, a2, a0584; RV32I-NEXT: neg a1, a0585; RV32I-NEXT: neg a0, a3586; RV32I-NEXT: ret587;588; RV32ZBB-LABEL: expanded_neg_inv_abs64:589; RV32ZBB: # %bb.0:590; RV32ZBB-NEXT: snez a2, a0591; RV32ZBB-NEXT: neg a3, a1592; RV32ZBB-NEXT: sub a2, a3, a2593; RV32ZBB-NEXT: neg a3, a0594; RV32ZBB-NEXT: beq a2, a1, .LBB12_2595; RV32ZBB-NEXT: # %bb.1:596; RV32ZBB-NEXT: slt a4, a2, a1597; RV32ZBB-NEXT: beqz a4, .LBB12_3598; RV32ZBB-NEXT: j .LBB12_4599; RV32ZBB-NEXT: .LBB12_2:600; RV32ZBB-NEXT: sltu a4, a3, a0601; RV32ZBB-NEXT: bnez a4, .LBB12_4602; RV32ZBB-NEXT: .LBB12_3:603; RV32ZBB-NEXT: mv a2, a1604; RV32ZBB-NEXT: mv a3, a0605; RV32ZBB-NEXT: .LBB12_4:606; RV32ZBB-NEXT: snez a0, a3607; RV32ZBB-NEXT: add a0, a2, a0608; RV32ZBB-NEXT: neg a1, a0609; RV32ZBB-NEXT: neg a0, a3610; RV32ZBB-NEXT: ret611;612; RV64I-LABEL: expanded_neg_inv_abs64:613; RV64I: # %bb.0:614; RV64I-NEXT: neg a1, a0615; RV64I-NEXT: blt a1, a0, .LBB12_2616; RV64I-NEXT: # %bb.1:617; RV64I-NEXT: mv a1, a0618; RV64I-NEXT: .LBB12_2:619; RV64I-NEXT: neg a0, a1620; RV64I-NEXT: ret621;622; RV64ZBB-LABEL: expanded_neg_inv_abs64:623; RV64ZBB: # %bb.0:624; RV64ZBB-NEXT: neg a1, a0625; RV64ZBB-NEXT: max a0, a0, a1626; RV64ZBB-NEXT: ret627 %n = sub i64 0, %x628 %t = call i64 @llvm.smin.i64(i64 %n, i64 %x)629 %r = sub i64 0, %t630 ret i64 %r631}632 633define i64 @expanded_neg_inv_abs64_unsigned(i64 %x) {634; RV32I-LABEL: expanded_neg_inv_abs64_unsigned:635; RV32I: # %bb.0:636; RV32I-NEXT: snez a2, a0637; RV32I-NEXT: neg a3, a1638; RV32I-NEXT: sub a2, a3, a2639; RV32I-NEXT: neg a3, a0640; RV32I-NEXT: beq a2, a1, .LBB13_2641; RV32I-NEXT: # %bb.1:642; RV32I-NEXT: sltu a4, a2, a1643; RV32I-NEXT: beqz a4, .LBB13_3644; RV32I-NEXT: j .LBB13_4645; RV32I-NEXT: .LBB13_2:646; RV32I-NEXT: sltu a4, a3, a0647; RV32I-NEXT: bnez a4, .LBB13_4648; RV32I-NEXT: .LBB13_3:649; RV32I-NEXT: mv a2, a1650; RV32I-NEXT: mv a3, a0651; RV32I-NEXT: .LBB13_4:652; RV32I-NEXT: snez a0, a3653; RV32I-NEXT: add a0, a2, a0654; RV32I-NEXT: neg a1, a0655; RV32I-NEXT: neg a0, a3656; RV32I-NEXT: ret657;658; RV32ZBB-LABEL: expanded_neg_inv_abs64_unsigned:659; RV32ZBB: # %bb.0:660; RV32ZBB-NEXT: snez a2, a0661; RV32ZBB-NEXT: neg a3, a1662; RV32ZBB-NEXT: sub a2, a3, a2663; RV32ZBB-NEXT: neg a3, a0664; RV32ZBB-NEXT: beq a2, a1, .LBB13_2665; RV32ZBB-NEXT: # %bb.1:666; RV32ZBB-NEXT: sltu a4, a2, a1667; RV32ZBB-NEXT: beqz a4, .LBB13_3668; RV32ZBB-NEXT: j .LBB13_4669; RV32ZBB-NEXT: .LBB13_2:670; RV32ZBB-NEXT: sltu a4, a3, a0671; RV32ZBB-NEXT: bnez a4, .LBB13_4672; RV32ZBB-NEXT: .LBB13_3:673; RV32ZBB-NEXT: mv a2, a1674; RV32ZBB-NEXT: mv a3, a0675; RV32ZBB-NEXT: .LBB13_4:676; RV32ZBB-NEXT: snez a0, a3677; RV32ZBB-NEXT: add a0, a2, a0678; RV32ZBB-NEXT: neg a1, a0679; RV32ZBB-NEXT: neg a0, a3680; RV32ZBB-NEXT: ret681;682; RV64I-LABEL: expanded_neg_inv_abs64_unsigned:683; RV64I: # %bb.0:684; RV64I-NEXT: neg a1, a0685; RV64I-NEXT: bltu a1, a0, .LBB13_2686; RV64I-NEXT: # %bb.1:687; RV64I-NEXT: mv a1, a0688; RV64I-NEXT: .LBB13_2:689; RV64I-NEXT: neg a0, a1690; RV64I-NEXT: ret691;692; RV64ZBB-LABEL: expanded_neg_inv_abs64_unsigned:693; RV64ZBB: # %bb.0:694; RV64ZBB-NEXT: neg a1, a0695; RV64ZBB-NEXT: maxu a0, a0, a1696; RV64ZBB-NEXT: ret697 %n = sub i64 0, %x698 %t = call i64 @llvm.umin.i64(i64 %n, i64 %x)699 %r = sub i64 0, %t700 ret i64 %r701}702