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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=RV323; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV644 5define signext i32 @test1(i32 signext %x) {6; RV32-LABEL: test1:7; RV32: # %bb.0:8; RV32-NEXT: slli a0, a0, 19; RV32-NEXT: addi a0, a0, 110; RV32-NEXT: ret11;12; RV64-LABEL: test1:13; RV64: # %bb.0:14; RV64-NEXT: slli a0, a0, 115; RV64-NEXT: addiw a0, a0, 116; RV64-NEXT: ret17 %a = shl i32 %x, 118 %b = or i32 %a, 119 ret i32 %b20}21 22define i64 @test2(i64 %x) {23; RV32-LABEL: test2:24; RV32: # %bb.0:25; RV32-NEXT: andi a0, a0, -426; RV32-NEXT: addi a0, a0, 227; RV32-NEXT: ret28;29; RV64-LABEL: test2:30; RV64: # %bb.0:31; RV64-NEXT: andi a0, a0, -432; RV64-NEXT: addi a0, a0, 233; RV64-NEXT: ret34 %a = and i64 %x, -435 %b = or i64 %a, 236 ret i64 %b37}38 39define signext i32 @test3(i32 signext %x) {40; RV32-LABEL: test3:41; RV32: # %bb.0:42; RV32-NEXT: slli a0, a0, 343; RV32-NEXT: addi a0, a0, 644; RV32-NEXT: ret45;46; RV64-LABEL: test3:47; RV64: # %bb.0:48; RV64-NEXT: slli a0, a0, 349; RV64-NEXT: addiw a0, a0, 650; RV64-NEXT: ret51 %a = shl i32 %x, 352 %b = add i32 %a, 653 ret i32 %b54}55 56define i64 @test4(i64 %x) {57; RV32-LABEL: test4:58; RV32: # %bb.0:59; RV32-NEXT: srli a2, a0, 2860; RV32-NEXT: slli a1, a1, 461; RV32-NEXT: slli a0, a0, 462; RV32-NEXT: or a1, a1, a263; RV32-NEXT: addi a0, a0, 1364; RV32-NEXT: ret65;66; RV64-LABEL: test4:67; RV64: # %bb.0:68; RV64-NEXT: slli a0, a0, 469; RV64-NEXT: addi a0, a0, 1370; RV64-NEXT: ret71 %a = shl i64 %x, 472 %b = add i64 %a, 1373 ret i64 %b74}75 76define signext i32 @test5(i32 signext %x) {77; RV32-LABEL: test5:78; RV32: # %bb.0:79; RV32-NEXT: srli a0, a0, 2480; RV32-NEXT: addi a0, a0, 25681; RV32-NEXT: ret82;83; RV64-LABEL: test5:84; RV64: # %bb.0:85; RV64-NEXT: srliw a0, a0, 2486; RV64-NEXT: addiw a0, a0, 25687; RV64-NEXT: ret88 %a = lshr i32 %x, 2489 %b = xor i32 %a, 25690 ret i32 %b91}92 93define i64 @test6(i64 %x) {94; RV32-LABEL: test6:95; RV32: # %bb.0:96; RV32-NEXT: srli a1, a1, 2297; RV32-NEXT: addi a0, a1, 102498; RV32-NEXT: li a1, 099; RV32-NEXT: ret100;101; RV64-LABEL: test6:102; RV64: # %bb.0:103; RV64-NEXT: srli a0, a0, 54104; RV64-NEXT: addiw a0, a0, 1024105; RV64-NEXT: ret106 %a = lshr i64 %x, 54107 %b = xor i64 %a, 1024108 ret i64 %b109}110 111define signext i32 @test7(i32 signext %x) {112; RV32-LABEL: test7:113; RV32: # %bb.0:114; RV32-NEXT: addi a0, a0, 1115; RV32-NEXT: ret116;117; RV64-LABEL: test7:118; RV64: # %bb.0:119; RV64-NEXT: ori a0, a0, 1120; RV64-NEXT: ret121 %a = or disjoint i32 %x, 1122 ret i32 %a123}124 125define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {126; RV32-LABEL: pr128468:127; RV32: # %bb.0:128; RV32-NEXT: slli a3, a1, 3129; RV32-NEXT: add a3, a0, a3130; RV32-NEXT: lw a2, 4(a3)131; RV32-NEXT: bgez a2, .LBB7_6132; RV32-NEXT: # %bb.1:133; RV32-NEXT: slli a2, a1, 1134; RV32-NEXT: addi a2, a2, 1135; RV32-NEXT: beq a2, a1, .LBB7_6136; RV32-NEXT: # %bb.2: # %.preheader137; RV32-NEXT: addi a3, a3, 4138; RV32-NEXT: j .LBB7_4139; RV32-NEXT: .LBB7_3: # in Loop: Header=BB7_4 Depth=1140; RV32-NEXT: mv a2, a1141; RV32-NEXT: addi a3, a3, 4142; RV32-NEXT: beq a1, a1, .LBB7_6143; RV32-NEXT: .LBB7_4: # =>This Inner Loop Header: Depth=1144; RV32-NEXT: slli a1, a1, 2145; RV32-NEXT: add a1, a0, a1146; RV32-NEXT: lw a4, 0(a1)147; RV32-NEXT: mv a1, a2148; RV32-NEXT: sw a4, 0(a3)149; RV32-NEXT: slli a3, a2, 3150; RV32-NEXT: add a3, a0, a3151; RV32-NEXT: lw a2, 4(a3)152; RV32-NEXT: bgez a2, .LBB7_3153; RV32-NEXT: # %bb.5: # in Loop: Header=BB7_4 Depth=1154; RV32-NEXT: slli a2, a1, 1155; RV32-NEXT: addi a2, a2, 1156; RV32-NEXT: addi a3, a3, 4157; RV32-NEXT: bne a2, a1, .LBB7_4158; RV32-NEXT: .LBB7_6:159; RV32-NEXT: ret160;161; RV64-LABEL: pr128468:162; RV64: # %bb.0:163; RV64-NEXT: slliw a2, a1, 1164; RV64-NEXT: slli a3, a2, 2165; RV64-NEXT: add a3, a0, a3166; RV64-NEXT: lw a4, 4(a3)167; RV64-NEXT: bgez a4, .LBB7_6168; RV64-NEXT: # %bb.1:169; RV64-NEXT: addiw a2, a2, 1170; RV64-NEXT: beq a2, a1, .LBB7_6171; RV64-NEXT: # %bb.2: # %.preheader172; RV64-NEXT: addi a3, a3, 4173; RV64-NEXT: j .LBB7_4174; RV64-NEXT: .LBB7_3: # in Loop: Header=BB7_4 Depth=1175; RV64-NEXT: mv a2, a1176; RV64-NEXT: addi a3, a3, 4177; RV64-NEXT: beq a1, a1, .LBB7_6178; RV64-NEXT: .LBB7_4: # =>This Inner Loop Header: Depth=1179; RV64-NEXT: slli a1, a1, 2180; RV64-NEXT: add a1, a0, a1181; RV64-NEXT: lw a4, 0(a1)182; RV64-NEXT: mv a1, a2183; RV64-NEXT: slliw a2, a2, 1184; RV64-NEXT: sw a4, 0(a3)185; RV64-NEXT: slli a3, a2, 2186; RV64-NEXT: add a3, a0, a3187; RV64-NEXT: lw a4, 4(a3)188; RV64-NEXT: bgez a4, .LBB7_3189; RV64-NEXT: # %bb.5: # in Loop: Header=BB7_4 Depth=1190; RV64-NEXT: addiw a2, a2, 1191; RV64-NEXT: addi a3, a3, 4192; RV64-NEXT: bne a2, a1, .LBB7_4193; RV64-NEXT: .LBB7_6:194; RV64-NEXT: ret195 %4 = shl nsw i32 %1, 1196 %5 = or disjoint i32 %4, 1197 %6 = sext i32 %5 to i64198 %7 = getelementptr inbounds i32, ptr %0, i64 %6199 %8 = load i32, ptr %7, align 4200 %9 = icmp sgt i32 %8, -1201 %10 = icmp eq i32 %5, %1202 %11 = or i1 %9, %10203 br i1 %11, label %27, label %12204 20512: ; preds = %3, %12206 %13 = phi i32 [ %25, %12 ], [ %5, %3 ]207 %14 = phi ptr [ %22, %12 ], [ %7, %3 ]208 %15 = phi i32 [ %13, %12 ], [ %1, %3 ]209 %16 = sext i32 %15 to i64210 %17 = getelementptr inbounds i32, ptr %0, i64 %16211 %18 = load i32, ptr %17, align 4212 store i32 %18, ptr %14, align 4213 %19 = shl nsw i32 %13, 1214 %20 = or disjoint i32 %19, 1215 %21 = sext i32 %20 to i64216 %22 = getelementptr inbounds i32, ptr %0, i64 %21217 %23 = load i32, ptr %22, align 4218 %24 = icmp slt i32 %23, 0219 %25 = select i1 %24, i32 %20, i32 %13220 %26 = icmp eq i32 %25, %13221 br i1 %26, label %27, label %12222 22327: ; preds = %12, %3224 ret void225}226