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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I4; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB6 7define i32 @orc_b_i32_mul255(i32 %x) nounwind {8; RV32I-LABEL: orc_b_i32_mul255:9; RV32I: # %bb.0: # %entry10; RV32I-NEXT: lui a1, 411211; RV32I-NEXT: addi a1, a1, 25712; RV32I-NEXT: and a0, a0, a113; RV32I-NEXT: slli a1, a0, 814; RV32I-NEXT: sub a0, a1, a015; RV32I-NEXT: ret16;17; RV32ZBB-LABEL: orc_b_i32_mul255:18; RV32ZBB: # %bb.0: # %entry19; RV32ZBB-NEXT: lui a1, 411220; RV32ZBB-NEXT: addi a1, a1, 25721; RV32ZBB-NEXT: and a0, a0, a122; RV32ZBB-NEXT: orc.b a0, a023; RV32ZBB-NEXT: ret24entry:25 %and = and i32 %x, 1684300926 %mul = mul nuw nsw i32 %and, 25527 ret i32 %mul28}29 30 31define i32 @orc_b_i32_sub_shl8x_x_lsb(i32 %x) {32; RV32I-LABEL: orc_b_i32_sub_shl8x_x_lsb:33; RV32I: # %bb.0: # %entry34; RV32I-NEXT: lui a1, 411235; RV32I-NEXT: addi a1, a1, 25736; RV32I-NEXT: and a0, a0, a137; RV32I-NEXT: slli a1, a0, 838; RV32I-NEXT: sub a0, a1, a039; RV32I-NEXT: ret40;41; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb:42; RV32ZBB: # %bb.0: # %entry43; RV32ZBB-NEXT: lui a1, 411244; RV32ZBB-NEXT: addi a1, a1, 25745; RV32ZBB-NEXT: and a0, a0, a146; RV32ZBB-NEXT: orc.b a0, a047; RV32ZBB-NEXT: ret48entry:49 %and = and i32 %x, 1684300950 %sub = mul nuw i32 %and, 25551 ret i32 %sub52}53 54define i32 @orc_b_i32_sub_shl8x_x_lsb_preshifted(i32 %x){55; RV32I-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted:56; RV32I: # %bb.0: # %entry57; RV32I-NEXT: srli a0, a0, 1158; RV32I-NEXT: lui a1, 1659; RV32I-NEXT: addi a1, a1, 25760; RV32I-NEXT: and a0, a0, a161; RV32I-NEXT: slli a1, a0, 862; RV32I-NEXT: sub a0, a1, a063; RV32I-NEXT: ret64;65; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted:66; RV32ZBB: # %bb.0: # %entry67; RV32ZBB-NEXT: srli a0, a0, 1168; RV32ZBB-NEXT: lui a1, 1669; RV32ZBB-NEXT: addi a1, a1, 25770; RV32ZBB-NEXT: and a0, a0, a171; RV32ZBB-NEXT: orc.b a0, a072; RV32ZBB-NEXT: ret73entry:74 %shr = lshr i32 %x, 1175 %and = and i32 %shr, 1684300976 %sub = mul nuw i32 %and, 25577 ret i32 %sub78}79 80 81define i32 @orc_b_i32_sub_shl8x_x_b1(i32 %x) {82; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1:83; RV32I: # %bb.0: # %entry84; RV32I-NEXT: lui a1, 822485; RV32I-NEXT: addi a1, a1, 51486; RV32I-NEXT: and a0, a0, a187; RV32I-NEXT: slli a1, a0, 788; RV32I-NEXT: srli a0, a0, 189; RV32I-NEXT: sub a0, a1, a090; RV32I-NEXT: ret91;92; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1:93; RV32ZBB: # %bb.0: # %entry94; RV32ZBB-NEXT: lui a1, 822495; RV32ZBB-NEXT: addi a1, a1, 51496; RV32ZBB-NEXT: and a0, a0, a197; RV32ZBB-NEXT: orc.b a0, a098; RV32ZBB-NEXT: ret99entry:100 %and = and i32 %x, 33686018101 %shl = shl i32 %and, 7102 %shr = lshr exact i32 %and, 1103 %sub = sub nsw i32 %shl, %shr104 ret i32 %sub105}106 107 108define i32 @orc_b_i32_sub_shl8x_x_b2(i32 %x) {109; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b2:110; RV32I: # %bb.0: # %entry111; RV32I-NEXT: lui a1, 16448112; RV32I-NEXT: addi a1, a1, 1028113; RV32I-NEXT: and a0, a0, a1114; RV32I-NEXT: slli a1, a0, 6115; RV32I-NEXT: srli a0, a0, 2116; RV32I-NEXT: sub a0, a1, a0117; RV32I-NEXT: ret118;119; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b2:120; RV32ZBB: # %bb.0: # %entry121; RV32ZBB-NEXT: lui a1, 16448122; RV32ZBB-NEXT: addi a1, a1, 1028123; RV32ZBB-NEXT: and a0, a0, a1124; RV32ZBB-NEXT: orc.b a0, a0125; RV32ZBB-NEXT: ret126entry:127 %and = and i32 %x, 67372036128 %shl = shl i32 %and, 6129 %shr = lshr exact i32 %and, 2130 %sub = sub nsw i32 %shl, %shr131 ret i32 %sub132}133 134 135define i32 @orc_b_i32_sub_shl8x_x_b3(i32 %x) {136; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b3:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: lui a1, 24672139; CHECK-NEXT: addi a1, a1, 1542140; CHECK-NEXT: and a0, a0, a1141; CHECK-NEXT: slli a1, a0, 5142; CHECK-NEXT: srli a0, a0, 3143; CHECK-NEXT: sub a0, a1, a0144; CHECK-NEXT: ret145entry:146 %and = and i32 %x, 101058054147 %shl = shl nuw i32 %and, 5148 %shr = lshr i32 %and, 3149 %sub = sub nsw i32 %shl, %shr150 ret i32 %sub151}152 153 154define i32 @orc_b_i32_sub_shl8x_x_b4(i32 %x) {155; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b4:156; CHECK: # %bb.0: # %entry157; CHECK-NEXT: lui a1, 32897158; CHECK-NEXT: addi a1, a1, -2040159; CHECK-NEXT: and a0, a0, a1160; CHECK-NEXT: slli a1, a0, 4161; CHECK-NEXT: srli a0, a0, 4162; CHECK-NEXT: sub a0, a1, a0163; CHECK-NEXT: ret164entry:165 %and = and i32 %x, 134744072166 %shl = shl nuw i32 %and, 4167 %shr = lshr i32 %and, 4168 %sub = sub nsw i32 %shl, %shr169 ret i32 %sub170}171 172 173define i32 @orc_b_i32_sub_shl8x_x_b5(i32 %x) {174; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b5:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: lui a1, 65793177; CHECK-NEXT: addi a1, a1, 16178; CHECK-NEXT: and a0, a0, a1179; CHECK-NEXT: slli a1, a0, 3180; CHECK-NEXT: srli a0, a0, 5181; CHECK-NEXT: sub a0, a1, a0182; CHECK-NEXT: ret183entry:184 %and = and i32 %x, 269488144185 %shl = shl nuw i32 %and, 3186 %shr = lshr i32 %and, 5187 %sub = sub nsw i32 %shl, %shr188 ret i32 %sub189}190 191 192define i32 @orc_b_i32_sub_shl8x_x_b6(i32 %x) {193; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b6:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: lui a1, 131586196; CHECK-NEXT: addi a1, a1, 32197; CHECK-NEXT: and a0, a0, a1198; CHECK-NEXT: slli a1, a0, 2199; CHECK-NEXT: srli a0, a0, 6200; CHECK-NEXT: sub a0, a1, a0201; CHECK-NEXT: ret202entry:203 %and = and i32 %x, 538976288204 %shl = shl nuw i32 %and, 2205 %shr = lshr i32 %and, 6206 %sub = sub nsw i32 %shl, %shr207 ret i32 %sub208}209 210 211define i32 @orc_b_i32_sub_shl8x_x_b7(i32 %x) {212; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b7:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: lui a1, 263172215; CHECK-NEXT: addi a1, a1, 64216; CHECK-NEXT: and a0, a0, a1217; CHECK-NEXT: slli a1, a0, 1218; CHECK-NEXT: srli a0, a0, 7219; CHECK-NEXT: sub a0, a1, a0220; CHECK-NEXT: ret221entry:222 %and = and i32 %x, 1077952576223 %shl = shl nuw i32 %and, 1224 %shr = lshr i32 %and, 7225 %sub = sub nsw i32 %shl, %shr226 ret i32 %sub227}228 229define i32 @orc_b_i32_sub_shl8x_x_b1_shl_used(i32 %x, ptr %arr) {230; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used:231; RV32I: # %bb.0: # %entry232; RV32I-NEXT: lui a2, 8224233; RV32I-NEXT: addi a2, a2, 514234; RV32I-NEXT: and a0, a0, a2235; RV32I-NEXT: slli a2, a0, 7236; RV32I-NEXT: srli a3, a0, 1237; RV32I-NEXT: sub a0, a2, a3238; RV32I-NEXT: sw a3, 0(a1)239; RV32I-NEXT: ret240;241; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used:242; RV32ZBB: # %bb.0: # %entry243; RV32ZBB-NEXT: lui a2, 8224244; RV32ZBB-NEXT: addi a2, a2, 514245; RV32ZBB-NEXT: and a0, a0, a2246; RV32ZBB-NEXT: srli a2, a0, 1247; RV32ZBB-NEXT: orc.b a0, a0248; RV32ZBB-NEXT: sw a2, 0(a1)249; RV32ZBB-NEXT: ret250entry:251 %and = and i32 %x, 33686018252 %shl = shl i32 %and, 7253 %shr = lshr exact i32 %and, 1254 store i32 %shr, ptr %arr, align 4255 %sub = sub nsw i32 %shl, %shr256 ret i32 %sub257}258 259define i32 @orc_b_i32_sub_shl8x_x_b1_srl_used(i32 %x, ptr %arr) {260; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used:261; RV32I: # %bb.0: # %entry262; RV32I-NEXT: lui a2, 8224263; RV32I-NEXT: addi a2, a2, 514264; RV32I-NEXT: and a0, a0, a2265; RV32I-NEXT: slli a2, a0, 7266; RV32I-NEXT: srli a0, a0, 1267; RV32I-NEXT: sub a0, a2, a0268; RV32I-NEXT: sw a2, 0(a1)269; RV32I-NEXT: ret270;271; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used:272; RV32ZBB: # %bb.0: # %entry273; RV32ZBB-NEXT: lui a2, 8224274; RV32ZBB-NEXT: addi a2, a2, 514275; RV32ZBB-NEXT: and a0, a0, a2276; RV32ZBB-NEXT: slli a2, a0, 7277; RV32ZBB-NEXT: orc.b a0, a0278; RV32ZBB-NEXT: sw a2, 0(a1)279; RV32ZBB-NEXT: ret280entry:281 %and = and i32 %x, 33686018282 %shl = shl i32 %and, 7283 %shr = lshr exact i32 %and, 1284 store i32 %shl, ptr %arr, align 4285 %sub = sub nsw i32 %shl, %shr286 ret i32 %sub287}288 289 290define i32 @orc_b_i32_sub_shl8x_x_b1_not_used(i32 %x, ptr %arr) {291; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used:292; RV32I: # %bb.0: # %entry293; RV32I-NEXT: lui a1, 8224294; RV32I-NEXT: addi a1, a1, 514295; RV32I-NEXT: and a0, a0, a1296; RV32I-NEXT: slli a1, a0, 7297; RV32I-NEXT: srli a0, a0, 1298; RV32I-NEXT: sub a0, a1, a0299; RV32I-NEXT: ret300;301; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used:302; RV32ZBB: # %bb.0: # %entry303; RV32ZBB-NEXT: lui a1, 8224304; RV32ZBB-NEXT: addi a1, a1, 514305; RV32ZBB-NEXT: and a0, a0, a1306; RV32ZBB-NEXT: orc.b a0, a0307; RV32ZBB-NEXT: ret308entry:309 %and = and i32 %x, 33686018310 %shl = shl i32 %and, 7311 %shr = lshr exact i32 %and, 1312 %sub = sub nsw i32 %shl, %shr313 ret i32 %sub314}315 316define i32 @orc_b_i32_sub_shl8x_x_shl_used(i32 %x, ptr %arr){317; CHECK-LABEL: orc_b_i32_sub_shl8x_x_shl_used:318; CHECK: # %bb.0: # %entry319; CHECK-NEXT: lui a2, 4112320; CHECK-NEXT: addi a2, a2, 257321; CHECK-NEXT: and a0, a0, a2322; CHECK-NEXT: slli a2, a0, 8323; CHECK-NEXT: sub a0, a2, a0324; CHECK-NEXT: sw a2, 0(a1)325; CHECK-NEXT: ret326entry:327 %and = and i32 %x, 16843009328 %shl = shl i32 %and, 8329 store i32 %shl, ptr %arr, align 4330 %sub = mul nuw i32 %and, 255331 ret i32 %sub332}333 334define i32 @orc_b_i32_sub_shl8x_x_b1_both_used(i32 %x, ptr %arr) {335; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used:336; CHECK: # %bb.0: # %entry337; CHECK-NEXT: lui a2, 8224338; CHECK-NEXT: addi a2, a2, 514339; CHECK-NEXT: and a0, a0, a2340; CHECK-NEXT: slli a2, a0, 7341; CHECK-NEXT: srli a3, a0, 1342; CHECK-NEXT: sub a0, a2, a3343; CHECK-NEXT: sw a2, 0(a1)344; CHECK-NEXT: sw a3, 4(a1)345; CHECK-NEXT: ret346entry:347 %and = and i32 %x, 33686018348 %shl = shl i32 %and, 7349 %shr = lshr exact i32 %and, 1350 store i32 %shl, ptr %arr, align 4351 %arrayidx1 = getelementptr inbounds i8, ptr %arr, i32 4352 store i32 %shr, ptr %arrayidx1, align 4353 %sub = sub nsw i32 %shl, %shr354 ret i32 %sub355}356 357 358define i32 @orc_b_i32_sub_x_shr8x(i32 %x) {359; CHECK-LABEL: orc_b_i32_sub_x_shr8x:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: lui a1, 4112362; CHECK-NEXT: addi a1, a1, 257363; CHECK-NEXT: and a0, a0, a1364; CHECK-NEXT: srli a1, a0, 8365; CHECK-NEXT: sub a0, a0, a1366; CHECK-NEXT: ret367entry:368 %and = and i32 %x, 16843009369 %shr = lshr i32 %and, 8370 %sub = sub nsw i32 %and, %shr371 ret i32 %sub372}373