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1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2# REQUIRES: asserts3# RUN: llc -mtriple riscv64 -start-before=prologepilog -o - \4# RUN: -verify-machineinstrs %s | FileCheck %s5#6# RUN: llc -mtriple riscv64 -start-before=prologepilog -o /dev/null \7# RUN: -debug-only=prologepilog -verify-machineinstrs %s 2>&1 \8# RUN: | FileCheck --check-prefix=DEBUG %s9#10# DEBUG: Adjusting emergency spill slots!11# DEBUG: Adjusting offset of emergency spill slot #4 from -4112 to -819212 13# FIXME: The code generated here is incorrect. It stores a0 to 0(sp) before14# sub sp, sp, a0 but restores it after sub sp, sp, a0. We may need to implement15# the target hook saveScavengerRegister to solve it.16 17--- |18 ; ModuleID = 'reduced.ll'19 source_filename = "frame_layout-1253b1.cpp"20 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"21 target triple = "riscv64"22 23 ; Function Attrs: nounwind24 define weak_odr dso_local void @foo(ptr %ay) nounwind {25 ; CHECK-LABEL: foo:26 ; CHECK: # %bb.0: # %entry27 ; CHECK-NEXT: addi sp, sp, -203228 ; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill29 ; CHECK-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill30 ; CHECK-NEXT: addi s0, sp, 203231 ; CHECK-NEXT: sd a0, 0(sp) # 8-byte Folded Spill32 ; CHECK-NEXT: lui a0, 233 ; CHECK-NEXT: addi a0, a0, -203234 ; CHECK-NEXT: sub sp, sp, a035 ; CHECK-NEXT: srli a0, sp, 1236 ; CHECK-NEXT: slli sp, a0, 1237 ; CHECK-NEXT: ld a0, 0(sp) # 8-byte Folded Reload38 ; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill39 ; CHECK-NEXT: lui a1, 140 ; CHECK-NEXT: add a1, sp, a141 ; CHECK-NEXT: sd a0, -8(a1)42 ; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload43 ; CHECK-NEXT: call foo44 ; CHECK-NEXT: addi sp, s0, -203245 ; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload46 ; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload47 ; CHECK-NEXT: addi sp, sp, 203248 ; CHECK-NEXT: ret49 entry:50 ret void51 }52 53 54...55---56name: foo57alignment: 258tracksRegLiveness: false59frameInfo:60 maxAlignment: 409661stack:62 - { id: 0, size: 8, alignment: 4096 }63 - { id: 1, type: spill-slot, size: 8, alignment: 8 }64machineFunctionInfo: {}65body: |66 bb.0.entry:67 liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x3168 69 ; This is to store something to the (non-emergency) spill slot %stack.1.70 SD $x10, %stack.1, 071 ; This is here just to make all the eligible registers live at this point.72 ; This way when we replace the frame index %stack.1 with its actual address73 ; we have to allocate a virtual register to compute it.74 ; A later run of the the register scavenger won't find an available register75 ; either so it will have to spill one to the emergency spill slot.76 PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x3177 PseudoRET78 79...80## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:81# DEBUG: {{.*}}82