83 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s3 4define i32 @signed(i32 %0, ptr %1) {5; CHECK-LABEL: signed:6; CHECK: # %bb.0:7; CHECK-NEXT: sraiw a2, a0, 318; CHECK-NEXT: srliw a2, a2, 249; CHECK-NEXT: add a2, a0, a210; CHECK-NEXT: andi a2, a2, -25611; CHECK-NEXT: sub a2, a0, a212; CHECK-NEXT: sraiw a0, a0, 813; CHECK-NEXT: sw a2, 0(a1)14; CHECK-NEXT: ret15 %rem = srem i32 %0, 25616 store i32 %rem, ptr %1, align 417 %div = sdiv exact i32 %0, 25618 ret i32 %div19}20 21define i32 @unsigned(i32 %0, ptr %1) {22; CHECK-LABEL: unsigned:23; CHECK: # %bb.0:24; CHECK-NEXT: slli a2, a0, 3225; CHECK-NEXT: lui a3, 69905126; CHECK-NEXT: addi a3, a3, -136527; CHECK-NEXT: slli a4, a3, 3228; CHECK-NEXT: mulhu a2, a2, a429; CHECK-NEXT: srli a2, a2, 3630; CHECK-NEXT: slli a4, a2, 331; CHECK-NEXT: slli a2, a2, 432; CHECK-NEXT: add a2, a2, a433; CHECK-NEXT: srliw a4, a0, 334; CHECK-NEXT: sub a2, a0, a235; CHECK-NEXT: mulw a0, a4, a336; CHECK-NEXT: sw a2, 0(a1)37; CHECK-NEXT: ret38 %rem = urem i32 %0, 2439 store i32 %rem, ptr %1, align 440 %div = udiv exact i32 %0, 2441 ret i32 %div42}43 44define i32 @signed_div_first(i32 %0, ptr %1) {45; CHECK-LABEL: signed_div_first:46; CHECK: # %bb.0:47; CHECK-NEXT: sraiw a2, a0, 3148; CHECK-NEXT: srliw a2, a2, 2449; CHECK-NEXT: add a3, a0, a250; CHECK-NEXT: sraiw a2, a3, 851; CHECK-NEXT: andi a3, a3, -25652; CHECK-NEXT: sub a0, a0, a353; CHECK-NEXT: sw a0, 0(a1)54; CHECK-NEXT: mv a0, a255; CHECK-NEXT: ret56 %div = sdiv exact i32 %0, 25657 %rem = srem i32 %0, 25658 store i32 %rem, ptr %1, align 459 ret i32 %div60}61 62define i32 @unsigned_div_first(i32 %0, ptr %1) {63; CHECK-LABEL: unsigned_div_first:64; CHECK: # %bb.0:65; CHECK-NEXT: slli a2, a0, 3266; CHECK-NEXT: lui a3, 69905167; CHECK-NEXT: addi a3, a3, -136568; CHECK-NEXT: slli a3, a3, 3269; CHECK-NEXT: mulhu a2, a2, a370; CHECK-NEXT: srli a2, a2, 3671; CHECK-NEXT: slli a3, a2, 372; CHECK-NEXT: slli a4, a2, 473; CHECK-NEXT: add a3, a4, a374; CHECK-NEXT: sub a0, a0, a375; CHECK-NEXT: sw a0, 0(a1)76; CHECK-NEXT: mv a0, a277; CHECK-NEXT: ret78 %div = udiv exact i32 %0, 2479 %rem = urem i32 %0, 2480 store i32 %rem, ptr %1, align 481 ret i32 %div82}83