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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 | FileCheck %s3 4; These two loads will CSE, we need to conservatively combine the range5; metadata. The final assembly should not contain an OR.6define i32 @f(ptr %p) {7; CHECK-LABEL: f:8; CHECK: # %bb.0:9; CHECK-NEXT: lw a0, 0(a0)10; CHECK-NEXT: lui a1, 29447111; CHECK-NEXT: addi a1, a1, 106412; CHECK-NEXT: addw a0, a0, a113; CHECK-NEXT: ret14 %load = load i32, ptr %p, align 4, !range !015 %load2 = load i32, ptr %p, align 416 %add = add i32 1206154280, %load217 ret i32 %add18}19 20; The mul and getelementptr will get removed in DAGCombine causing the loads21; to CSE after they are created.22define i32 @test(ptr %p, i32 %x, ptr %q) {23; CHECK-LABEL: test:24; CHECK: # %bb.0:25; CHECK-NEXT: lw a1, 0(a0)26; CHECK-NEXT: lui a0, 29447127; CHECK-NEXT: addi a0, a0, 106428; CHECK-NEXT: addw a0, a1, a029; CHECK-NEXT: sw a1, 0(a2)30; CHECK-NEXT: ret31 %load = load i32, ptr %p, align 4, !range !032 %mul = mul i32 0, %x33 %a = getelementptr i32, ptr %p, i32 %mul34 %load2 = load i32, ptr %a, align 435 %add = add i32 1206154280, %load236 store i32 %load, ptr %q37 ret i32 %add38}39 40!0 = !{i32 1, i32 2, i32 3, i32 4}41