117 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc %s -mtriple=riscv64 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - | FileCheck %s3 4---5name: foo6alignment: 47tracksRegLiveness: true8frameInfo:9 maxAlignment: 410 localFrameSize: 411stack:12 - { id: 0, size: 1, alignment: 4, local-offset: -4 }13machineFunctionInfo:14 varArgsFrameIndex: 015 varArgsSaveSize: 016body: |17 bb.0.entry:18 ; To trick stack-slot-colouring to run its dead-store-elimination phase,19 ; which is at fault, we need the register allocator to run, and spill in two20 ; places that can have their slots merged. Achieve this by volatile-loading21 ; data into all allocatable GPRs except $x31. Then, volatile storing them22 ; later, leaving regalloc only $x31 to play with in the middle.23 $x1 = LW %stack.0, 0 :: (volatile load (s32))24 $x5 = LW %stack.0, 0 :: (volatile load (s32))25 $x6 = LW %stack.0, 0 :: (volatile load (s32))26 $x7 = LW %stack.0, 0 :: (volatile load (s32))27 $x8 = LW %stack.0, 0 :: (volatile load (s32))28 $x9 = LW %stack.0, 0 :: (volatile load (s32))29 $x10 = LW %stack.0, 0 :: (volatile load (s32))30 $x11 = LW %stack.0, 0 :: (volatile load (s32))31 $x12 = LW %stack.0, 0 :: (volatile load (s32))32 $x13 = LW %stack.0, 0 :: (volatile load (s32))33 $x14 = LW %stack.0, 0 :: (volatile load (s32))34 $x15 = LW %stack.0, 0 :: (volatile load (s32))35 $x16 = LW %stack.0, 0 :: (volatile load (s32))36 $x17 = LW %stack.0, 0 :: (volatile load (s32))37 $x18 = LW %stack.0, 0 :: (volatile load (s32))38 $x19 = LW %stack.0, 0 :: (volatile load (s32))39 $x20 = LW %stack.0, 0 :: (volatile load (s32))40 $x21 = LW %stack.0, 0 :: (volatile load (s32))41 $x22 = LW %stack.0, 0 :: (volatile load (s32))42 $x23 = LW %stack.0, 0 :: (volatile load (s32))43 $x24 = LW %stack.0, 0 :: (volatile load (s32))44 $x25 = LW %stack.0, 0 :: (volatile load (s32))45 $x26 = LW %stack.0, 0 :: (volatile load (s32))46 $x27 = LW %stack.0, 0 :: (volatile load (s32))47 $x28 = LW %stack.0, 0 :: (volatile load (s32))48 $x29 = LW %stack.0, 0 :: (volatile load (s32))49 $x30 = LW %stack.0, 0 :: (volatile load (s32))50 51 ; Force the first spill.52 %0:gpr = LW %stack.0, 0 :: (volatile load (s32))53 %1:gpr = LW %stack.0, 0 :: (volatile load (s32))54 SW %1, %stack.0, 0 :: (volatile store (s32))55 SW %0, %stack.0, 0 :: (volatile store (s32))56 57 ; CHECK: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))58 ; CHECK-NEXT: SD killed renamable $x31, %stack.1, 0 :: (store (s64) into %stack.1)59 ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))60 ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))61 ; CHECK-NEXT: renamable $x31 = LD %stack.1, 0 :: (load (s64) from %stack.1)62 ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))63 64 ; stack-slot-coloring doesn't know that a write to $x0 is discarded.65 dead $x0 = LW %stack.0, 0 :: (volatile load (s32))66 ; This stores 0 rather than the result of the preceding load since $x067 ; is special.68 ; We don't want this store to be deleted.69 SW $x0, %stack.0, 0 :: (volatile store (s32))70 71 ; CHECK-NEXT: dead $x0 = LW %stack.0, 0 :: (volatile load (s32))72 ; CHECK-NEXT: SW $x0, %stack.0, 0 :: (volatile store (s32))73 74 ; Force a second spill75 %2:gpr = LW %stack.0, 0 :: (volatile load (s32))76 %3:gpr = LW %stack.0, 0 :: (volatile load (s32))77 SW %3, %stack.0, 0 :: (volatile store (s32))78 SW %2, %stack.0, 0 :: (volatile store (s32))79 80 ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))81 ; CHECK-NEXT: SD killed renamable $x31, %stack.1, 0 :: (store (s64) into %stack.1)82 ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))83 ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))84 ; CHECK-NEXT: renamable $x31 = LD %stack.1, 0 :: (load (s64) from %stack.1)85 ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))86 87 SW $x1, %stack.0, 0 :: (volatile store (s32))88 SW $x5, %stack.0, 0 :: (volatile store (s32))89 SW $x6, %stack.0, 0 :: (volatile store (s32))90 SW $x7, %stack.0, 0 :: (volatile store (s32))91 SW $x8, %stack.0, 0 :: (volatile store (s32))92 SW $x9, %stack.0, 0 :: (volatile store (s32))93 SW $x10, %stack.0, 0 :: (volatile store (s32))94 SW $x11, %stack.0, 0 :: (volatile store (s32))95 SW $x12, %stack.0, 0 :: (volatile store (s32))96 SW $x13, %stack.0, 0 :: (volatile store (s32))97 SW $x14, %stack.0, 0 :: (volatile store (s32))98 SW $x15, %stack.0, 0 :: (volatile store (s32))99 SW $x16, %stack.0, 0 :: (volatile store (s32))100 SW $x17, %stack.0, 0 :: (volatile store (s32))101 SW $x18, %stack.0, 0 :: (volatile store (s32))102 SW $x19, %stack.0, 0 :: (volatile store (s32))103 SW $x20, %stack.0, 0 :: (volatile store (s32))104 SW $x21, %stack.0, 0 :: (volatile store (s32))105 SW $x22, %stack.0, 0 :: (volatile store (s32))106 SW $x23, %stack.0, 0 :: (volatile store (s32))107 SW $x24, %stack.0, 0 :: (volatile store (s32))108 SW $x25, %stack.0, 0 :: (volatile store (s32))109 SW $x26, %stack.0, 0 :: (volatile store (s32))110 SW $x27, %stack.0, 0 :: (volatile store (s32))111 SW $x28, %stack.0, 0 :: (volatile store (s32))112 SW $x29, %stack.0, 0 :: (volatile store (s32))113 SW $x30, %stack.0, 0 :: (volatile store (s32))114 PseudoRET115 116...117