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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv64-unknown-linux-gnu < %s | FileCheck %s3; RUN: llc -mtriple=riscv32-unknown-linux-gnu < %s | FileCheck %s4 5; Dag-combine used to improperly combine a vector vselect of 0 and 2 into6; 2 + condition(0/1) because one of the two args was transformed from an i32->i64.7 8define i16 @foo() {9; CHECK-LABEL: foo:10; CHECK: # %bb.0: # %entry11; CHECK-NEXT: li a0, 012; CHECK-NEXT: ret13entry:14 %insert.0 = insertelement <4 x i16> zeroinitializer, i16 2, i64 015 %all.two = shufflevector <4 x i16> %insert.0, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer16 %sel.0 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> zeroinitializer, <4 x i16> %all.two17 %mul.0 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> %sel.0)18 ret i16 %mul.019}20 21