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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s4 5define i32 @PR95271(ptr %p) {6; RV32I-LABEL: PR95271:7; RV32I: # %bb.0:8; RV32I-NEXT: lw a0, 0(a0)9; RV32I-NEXT: lui a1, 34952510; RV32I-NEXT: addi a1, a1, 136511; RV32I-NEXT: addi a0, a0, 112; RV32I-NEXT: srli a2, a0, 113; RV32I-NEXT: and a1, a2, a114; RV32I-NEXT: lui a2, 20971515; RV32I-NEXT: addi a2, a2, 81916; RV32I-NEXT: sub a0, a0, a117; RV32I-NEXT: and a1, a0, a218; RV32I-NEXT: srli a0, a0, 219; RV32I-NEXT: and a0, a0, a220; RV32I-NEXT: lui a2, 6168121; RV32I-NEXT: add a0, a1, a022; RV32I-NEXT: srli a1, a0, 423; RV32I-NEXT: add a0, a0, a124; RV32I-NEXT: addi a1, a2, -24125; RV32I-NEXT: and a0, a0, a126; RV32I-NEXT: slli a1, a0, 827; RV32I-NEXT: add a0, a0, a128; RV32I-NEXT: slli a1, a0, 1629; RV32I-NEXT: add a0, a0, a130; RV32I-NEXT: srli a0, a0, 2431; RV32I-NEXT: ret32;33; RV64I-LABEL: PR95271:34; RV64I: # %bb.0:35; RV64I-NEXT: lw a0, 0(a0)36; RV64I-NEXT: lui a1, 34952537; RV64I-NEXT: addi a1, a1, 136538; RV64I-NEXT: addi a2, a0, 139; RV64I-NEXT: srli a2, a2, 140; RV64I-NEXT: and a1, a2, a141; RV64I-NEXT: lui a2, 20971542; RV64I-NEXT: addi a2, a2, 81943; RV64I-NEXT: addiw a0, a0, 144; RV64I-NEXT: sub a0, a0, a145; RV64I-NEXT: and a1, a0, a246; RV64I-NEXT: srli a0, a0, 247; RV64I-NEXT: and a0, a0, a248; RV64I-NEXT: lui a2, 6168149; RV64I-NEXT: add a0, a1, a050; RV64I-NEXT: srli a1, a0, 451; RV64I-NEXT: add a0, a0, a152; RV64I-NEXT: addi a1, a2, -24153; RV64I-NEXT: and a0, a0, a154; RV64I-NEXT: slli a1, a0, 855; RV64I-NEXT: add a0, a0, a156; RV64I-NEXT: slli a1, a0, 1657; RV64I-NEXT: add a0, a0, a158; RV64I-NEXT: srliw a0, a0, 2459; RV64I-NEXT: ret60 %load = load i32, ptr %p, align 461 %inc = add i32 %load, 162 %pop = tail call i32 @llvm.ctpop.i32(i32 %inc)63 ret i32 %pop64}65