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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s4 5; regression due to creation of temporary i32 avgfloors node6define signext i64 @PR95284(i32 signext %0) {7; RV32I-LABEL: PR95284:8; RV32I: # %bb.0: # %entry9; RV32I-NEXT: addi a1, a0, -110; RV32I-NEXT: seqz a0, a011; RV32I-NEXT: slli a2, a0, 3112; RV32I-NEXT: srli a1, a1, 113; RV32I-NEXT: or a1, a1, a214; RV32I-NEXT: addi a1, a1, 115; RV32I-NEXT: seqz a2, a116; RV32I-NEXT: sub a2, a2, a017; RV32I-NEXT: andi a0, a1, -218; RV32I-NEXT: slli a1, a2, 119; RV32I-NEXT: srli a1, a1, 120; RV32I-NEXT: ret21;22; RV64I-LABEL: PR95284:23; RV64I: # %bb.0: # %entry24; RV64I-NEXT: addi a0, a0, -125; RV64I-NEXT: srli a0, a0, 126; RV64I-NEXT: addi a0, a0, 127; RV64I-NEXT: andi a0, a0, -228; RV64I-NEXT: ret29entry:30 %1 = zext nneg i32 %0 to i6431 %2 = add nsw i64 %1, -132 %3 = lshr i64 %2, 133 %4 = add nuw nsw i64 %3, 134 %5 = and i64 %4, 922337203685477580635 ret i64 %536}37