120 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV64I %s4 5@PL_reg_match_utf8 = external global i8, align 16 7declare signext i32 @test1(i8 signext)8 9declare signext i32 @test2(i8 signext)10 11declare signext i32 @test3(i8 signext)12 13define signext i32 @test() nounwind {14; RV64I-LABEL: test:15; RV64I: # %bb.0:16; RV64I-NEXT: addi sp, sp, -1617; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill18; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill19; RV64I-NEXT: lui a0, %hi(PL_reg_match_utf8)20; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(a0)21; RV64I-NEXT: beqz s0, .LBB0_222; RV64I-NEXT: # %bb.1:23; RV64I-NEXT: mv a0, s024; RV64I-NEXT: call test125; RV64I-NEXT: mv a0, s026; RV64I-NEXT: call test227; RV64I-NEXT: mv a0, s028; RV64I-NEXT: call test329; RV64I-NEXT: j .LBB0_330; RV64I-NEXT: .LBB0_2:31; RV64I-NEXT: li a0, 032; RV64I-NEXT: call test233; RV64I-NEXT: .LBB0_3:34; RV64I-NEXT: li a0, 035; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload36; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload37; RV64I-NEXT: addi sp, sp, 1638; RV64I-NEXT: ret39 %1 = load i8, ptr @PL_reg_match_utf8, align 140 %2 = icmp eq i8 %1, 041 br i1 %2, label %7, label %342 433:44 %4 = tail call signext i32 @test1(i8 signext %1)45 %5 = tail call signext i32 @test2(i8 signext %1)46 %6 = tail call signext i32 @test3(i8 signext %1)47 br label %948 497:50 %8 = tail call signext i32 @test2(i8 signext 0)51 br label %952 539:54 ret i32 055}56 57 58define signext i32 @test_loop() nounwind {59; RV64I-LABEL: test_loop:60; RV64I: # %bb.0:61; RV64I-NEXT: addi sp, sp, -3262; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill63; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill64; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill65; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill66; RV64I-NEXT: li s1, -1667; RV64I-NEXT: lui s2, %hi(PL_reg_match_utf8)68; RV64I-NEXT: j .LBB1_269; RV64I-NEXT: .LBB1_1: # in Loop: Header=BB1_2 Depth=170; RV64I-NEXT: mv a0, s071; RV64I-NEXT: call test272; RV64I-NEXT: addiw s1, s1, 173; RV64I-NEXT: beqz s1, .LBB1_474; RV64I-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=175; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(s2)76; RV64I-NEXT: beqz s0, .LBB1_177; RV64I-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=178; RV64I-NEXT: mv a0, s079; RV64I-NEXT: call test180; RV64I-NEXT: mv a0, s081; RV64I-NEXT: call test282; RV64I-NEXT: mv a0, s083; RV64I-NEXT: call test384; RV64I-NEXT: addiw s1, s1, 185; RV64I-NEXT: bnez s1, .LBB1_286; RV64I-NEXT: .LBB1_4:87; RV64I-NEXT: li a0, 088; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload89; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload90; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload91; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload92; RV64I-NEXT: addi sp, sp, 3293; RV64I-NEXT: ret94 br label %195 961:97 %2 = phi i32 [ 16, %0 ], [ %12, %11 ]98 %3 = load i8, ptr @PL_reg_match_utf8, align 199 %4 = icmp eq i8 %3, 0100 br i1 %4, label %9, label %5101 1025:103 %6 = tail call signext i32 @test1(i8 signext %3)104 %7 = tail call signext i32 @test2(i8 signext %3)105 %8 = tail call signext i32 @test3(i8 signext %3)106 br label %11107 1089:109 %10 = tail call signext i32 @test2(i8 signext %3)110 br label %11111 11211:113 %12 = add nsw i32 %2, -1114 %13 = icmp eq i32 %12, 0115 br i1 %13, label %14, label %1116 11714:118 ret i32 0119}120