103 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV323; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV644 5; Negative test to ensure we don't try to generate a vector reduce when6; vector instructions are not available.7 8define i32 @reduce_sum_4xi32(<4 x i32> %v) {9; RV32-LABEL: reduce_sum_4xi32:10; RV32: # %bb.0:11; RV32-NEXT: lw a1, 0(a0)12; RV32-NEXT: lw a2, 4(a0)13; RV32-NEXT: lw a3, 8(a0)14; RV32-NEXT: lw a0, 12(a0)15; RV32-NEXT: add a1, a1, a216; RV32-NEXT: add a0, a3, a017; RV32-NEXT: add a0, a1, a018; RV32-NEXT: ret19;20; RV64-LABEL: reduce_sum_4xi32:21; RV64: # %bb.0:22; RV64-NEXT: lw a1, 0(a0)23; RV64-NEXT: lw a2, 8(a0)24; RV64-NEXT: lw a3, 16(a0)25; RV64-NEXT: lw a0, 24(a0)26; RV64-NEXT: add a1, a1, a227; RV64-NEXT: add a0, a3, a028; RV64-NEXT: addw a0, a1, a029; RV64-NEXT: ret30 %e0 = extractelement <4 x i32> %v, i32 031 %e1 = extractelement <4 x i32> %v, i32 132 %e2 = extractelement <4 x i32> %v, i32 233 %e3 = extractelement <4 x i32> %v, i32 334 %add0 = add i32 %e0, %e135 %add1 = add i32 %add0, %e236 %add2 = add i32 %add1, %e337 ret i32 %add238}39 40define i32 @reduce_xor_4xi32(<4 x i32> %v) {41; RV32-LABEL: reduce_xor_4xi32:42; RV32: # %bb.0:43; RV32-NEXT: lw a1, 0(a0)44; RV32-NEXT: lw a2, 4(a0)45; RV32-NEXT: lw a3, 8(a0)46; RV32-NEXT: lw a0, 12(a0)47; RV32-NEXT: xor a1, a1, a248; RV32-NEXT: xor a0, a3, a049; RV32-NEXT: xor a0, a1, a050; RV32-NEXT: ret51;52; RV64-LABEL: reduce_xor_4xi32:53; RV64: # %bb.0:54; RV64-NEXT: ld a1, 0(a0)55; RV64-NEXT: ld a2, 8(a0)56; RV64-NEXT: ld a3, 16(a0)57; RV64-NEXT: ld a0, 24(a0)58; RV64-NEXT: xor a1, a1, a259; RV64-NEXT: xor a0, a3, a060; RV64-NEXT: xor a0, a1, a061; RV64-NEXT: ret62 %e0 = extractelement <4 x i32> %v, i32 063 %e1 = extractelement <4 x i32> %v, i32 164 %e2 = extractelement <4 x i32> %v, i32 265 %e3 = extractelement <4 x i32> %v, i32 366 %xor0 = xor i32 %e0, %e167 %xor1 = xor i32 %xor0, %e268 %xor2 = xor i32 %xor1, %e369 ret i32 %xor270}71 72define i32 @reduce_or_4xi32(<4 x i32> %v) {73; RV32-LABEL: reduce_or_4xi32:74; RV32: # %bb.0:75; RV32-NEXT: lw a1, 0(a0)76; RV32-NEXT: lw a2, 4(a0)77; RV32-NEXT: lw a3, 8(a0)78; RV32-NEXT: lw a0, 12(a0)79; RV32-NEXT: or a1, a1, a280; RV32-NEXT: or a0, a3, a081; RV32-NEXT: or a0, a1, a082; RV32-NEXT: ret83;84; RV64-LABEL: reduce_or_4xi32:85; RV64: # %bb.0:86; RV64-NEXT: ld a1, 0(a0)87; RV64-NEXT: ld a2, 8(a0)88; RV64-NEXT: ld a3, 16(a0)89; RV64-NEXT: ld a0, 24(a0)90; RV64-NEXT: or a1, a1, a291; RV64-NEXT: or a0, a3, a092; RV64-NEXT: or a0, a1, a093; RV64-NEXT: ret94 %e0 = extractelement <4 x i32> %v, i32 095 %e1 = extractelement <4 x i32> %v, i32 196 %e2 = extractelement <4 x i32> %v, i32 297 %e3 = extractelement <4 x i32> %v, i32 398 %or0 = or i32 %e0, %e199 %or1 = or i32 %or0, %e2100 %or2 = or i32 %or1, %e3101 ret i32 %or2102}103