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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh \3; RUN: -enable-subreg-liveness=false < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh < %s \5; RUN: -enable-subreg-liveness=true| FileCheck %s --check-prefix=SUBREGLIVENESS6 7; This testcase failed to compile after8; c46aab01c002b7a04135b8b7f1f52d8c9ae23a58, which was reverted.9 10; FIXME: The failure does not reproduce with -stop-before=greedy11; output MIR with -start-before=greedy12 13define void @last_chance_recoloring_failure() {14; CHECK-LABEL: last_chance_recoloring_failure:15; CHECK: # %bb.0: # %entry16; CHECK-NEXT: addi sp, sp, -3217; CHECK-NEXT: .cfi_def_cfa_offset 3218; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill19; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill20; CHECK-NEXT: .cfi_offset ra, -821; CHECK-NEXT: .cfi_offset s0, -1622; CHECK-NEXT: csrr a0, vlenb23; CHECK-NEXT: slli a0, a0, 424; CHECK-NEXT: sub sp, sp, a025; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb26; CHECK-NEXT: li a0, 5527; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma28; CHECK-NEXT: vmclr.m v029; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma30; CHECK-NEXT: vloxseg2ei32.v v16, (a1), v831; CHECK-NEXT: csrr a0, vlenb32; CHECK-NEXT: slli a0, a0, 333; CHECK-NEXT: add a0, sp, a034; CHECK-NEXT: addi a0, a0, 1635; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill36; CHECK-NEXT: li s0, 3637; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma38; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t39; CHECK-NEXT: addi a0, sp, 1640; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill41; CHECK-NEXT: call func42; CHECK-NEXT: csrr a0, vlenb43; CHECK-NEXT: slli a0, a0, 344; CHECK-NEXT: add a0, sp, a045; CHECK-NEXT: addi a0, a0, 1646; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload47; CHECK-NEXT: addi a0, sp, 1648; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload49; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma50; CHECK-NEXT: vfwsub.wv v8, v24, v1651; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, mu52; CHECK-NEXT: vfdiv.vv v8, v24, v8, v0.t53; CHECK-NEXT: vse32.v v8, (a0)54; CHECK-NEXT: csrr a0, vlenb55; CHECK-NEXT: slli a0, a0, 456; CHECK-NEXT: add sp, sp, a057; CHECK-NEXT: .cfi_def_cfa sp, 3258; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload59; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload60; CHECK-NEXT: .cfi_restore ra61; CHECK-NEXT: .cfi_restore s062; CHECK-NEXT: addi sp, sp, 3263; CHECK-NEXT: .cfi_def_cfa_offset 064; CHECK-NEXT: ret65;66; SUBREGLIVENESS-LABEL: last_chance_recoloring_failure:67; SUBREGLIVENESS: # %bb.0: # %entry68; SUBREGLIVENESS-NEXT: addi sp, sp, -3269; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 3270; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill71; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill72; SUBREGLIVENESS-NEXT: .cfi_offset ra, -873; SUBREGLIVENESS-NEXT: .cfi_offset s0, -1674; SUBREGLIVENESS-NEXT: csrr a0, vlenb75; SUBREGLIVENESS-NEXT: slli a0, a0, 476; SUBREGLIVENESS-NEXT: sub sp, sp, a077; SUBREGLIVENESS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb78; SUBREGLIVENESS-NEXT: li a0, 5579; SUBREGLIVENESS-NEXT: vsetvli a2, zero, e8, m2, ta, ma80; SUBREGLIVENESS-NEXT: vmclr.m v081; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma82; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v16, (a1), v883; SUBREGLIVENESS-NEXT: csrr a0, vlenb84; SUBREGLIVENESS-NEXT: slli a0, a0, 385; SUBREGLIVENESS-NEXT: add a0, sp, a086; SUBREGLIVENESS-NEXT: addi a0, a0, 1687; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill88; SUBREGLIVENESS-NEXT: li s0, 3689; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma90; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t91; SUBREGLIVENESS-NEXT: addi a0, sp, 1692; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill93; SUBREGLIVENESS-NEXT: call func94; SUBREGLIVENESS-NEXT: csrr a0, vlenb95; SUBREGLIVENESS-NEXT: slli a0, a0, 396; SUBREGLIVENESS-NEXT: add a0, sp, a097; SUBREGLIVENESS-NEXT: addi a0, a0, 1698; SUBREGLIVENESS-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload99; SUBREGLIVENESS-NEXT: addi a0, sp, 16100; SUBREGLIVENESS-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload101; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma102; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v24, v16103; SUBREGLIVENESS-NEXT: vsetvli zero, zero, e32, m8, tu, mu104; SUBREGLIVENESS-NEXT: vfdiv.vv v8, v24, v8, v0.t105; SUBREGLIVENESS-NEXT: vse32.v v8, (a0)106; SUBREGLIVENESS-NEXT: csrr a0, vlenb107; SUBREGLIVENESS-NEXT: slli a0, a0, 4108; SUBREGLIVENESS-NEXT: add sp, sp, a0109; SUBREGLIVENESS-NEXT: .cfi_def_cfa sp, 32110; SUBREGLIVENESS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload111; SUBREGLIVENESS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload112; SUBREGLIVENESS-NEXT: .cfi_restore ra113; SUBREGLIVENESS-NEXT: .cfi_restore s0114; SUBREGLIVENESS-NEXT: addi sp, sp, 32115; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 0116; SUBREGLIVENESS-NEXT: ret117entry:118 %i = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr nonnull poison, <vscale x 16 x i32> poison, i64 55, i64 4)119 %i1 = tail call <vscale x 16 x half> @llvm.riscv.tuple.extract.v16f16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %i, i32 0)120 %i2 = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> poison, <vscale x 16 x half> poison, <vscale x 16 x i1> zeroinitializer, i64 7, i64 36, i64 0)121 call void @func()122 %i3 = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison, i64 32, i64 0)123 %i4 = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %i2, <vscale x 16 x half> %i1, i64 7, i64 36)124 %i5 = call <vscale x 16 x i16> @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> %i3, <vscale x 16 x i16> %i3, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison, i64 32, i64 0)125 %i6 = call <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> %i4, <vscale x 16 x float> %i2, <vscale x 16 x float> poison, <vscale x 16 x i1> poison, i64 7, i64 36, i64 0)126 call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> %i6, ptr nonnull poison, i64 36)127 ret void128}129 130declare void @func()131