2608 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -enable-legalize-types-checking < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefix=RV32ZBB8; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \9; RUN: | FileCheck %s -check-prefix=RV64ZBB10; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb -verify-machineinstrs < %s \11; RUN: | FileCheck %s -check-prefix=RV32XTHEADBB12; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb -verify-machineinstrs < %s \13; RUN: | FileCheck %s -check-prefix=RV64XTHEADBB14 15; NOTE: -enable-legalize-types-checking is on one command line due to a previous16; assertion failure on an expensive checks build for @rotr_32_mask_multiple.17 18; These IR sequences are idioms for rotates. If rotate instructions are19; supported, they will be turned into ISD::ROTL or ISD::ROTR.20 21define i32 @rotl_32(i32 %x, i32 %y) nounwind {22; RV32I-LABEL: rotl_32:23; RV32I: # %bb.0:24; RV32I-NEXT: neg a2, a125; RV32I-NEXT: sll a1, a0, a126; RV32I-NEXT: srl a0, a0, a227; RV32I-NEXT: or a0, a1, a028; RV32I-NEXT: ret29;30; RV64I-LABEL: rotl_32:31; RV64I: # %bb.0:32; RV64I-NEXT: neg a2, a133; RV64I-NEXT: sllw a1, a0, a134; RV64I-NEXT: srlw a0, a0, a235; RV64I-NEXT: or a0, a1, a036; RV64I-NEXT: ret37;38; RV32ZBB-LABEL: rotl_32:39; RV32ZBB: # %bb.0:40; RV32ZBB-NEXT: rol a0, a0, a141; RV32ZBB-NEXT: ret42;43; RV64ZBB-LABEL: rotl_32:44; RV64ZBB: # %bb.0:45; RV64ZBB-NEXT: rolw a0, a0, a146; RV64ZBB-NEXT: ret47;48; RV32XTHEADBB-LABEL: rotl_32:49; RV32XTHEADBB: # %bb.0:50; RV32XTHEADBB-NEXT: sll a2, a0, a151; RV32XTHEADBB-NEXT: neg a1, a152; RV32XTHEADBB-NEXT: srl a0, a0, a153; RV32XTHEADBB-NEXT: or a0, a2, a054; RV32XTHEADBB-NEXT: ret55;56; RV64XTHEADBB-LABEL: rotl_32:57; RV64XTHEADBB: # %bb.0:58; RV64XTHEADBB-NEXT: sllw a2, a0, a159; RV64XTHEADBB-NEXT: neg a1, a160; RV64XTHEADBB-NEXT: srlw a0, a0, a161; RV64XTHEADBB-NEXT: or a0, a2, a062; RV64XTHEADBB-NEXT: ret63 %z = sub i32 32, %y64 %b = shl i32 %x, %y65 %c = lshr i32 %x, %z66 %d = or i32 %b, %c67 ret i32 %d68}69 70define i32 @rotr_32(i32 %x, i32 %y) nounwind {71; RV32I-LABEL: rotr_32:72; RV32I: # %bb.0:73; RV32I-NEXT: neg a2, a174; RV32I-NEXT: srl a1, a0, a175; RV32I-NEXT: sll a0, a0, a276; RV32I-NEXT: or a0, a1, a077; RV32I-NEXT: ret78;79; RV64I-LABEL: rotr_32:80; RV64I: # %bb.0:81; RV64I-NEXT: neg a2, a182; RV64I-NEXT: srlw a1, a0, a183; RV64I-NEXT: sllw a0, a0, a284; RV64I-NEXT: or a0, a1, a085; RV64I-NEXT: ret86;87; RV32ZBB-LABEL: rotr_32:88; RV32ZBB: # %bb.0:89; RV32ZBB-NEXT: ror a0, a0, a190; RV32ZBB-NEXT: ret91;92; RV64ZBB-LABEL: rotr_32:93; RV64ZBB: # %bb.0:94; RV64ZBB-NEXT: rorw a0, a0, a195; RV64ZBB-NEXT: ret96;97; RV32XTHEADBB-LABEL: rotr_32:98; RV32XTHEADBB: # %bb.0:99; RV32XTHEADBB-NEXT: srl a2, a0, a1100; RV32XTHEADBB-NEXT: neg a1, a1101; RV32XTHEADBB-NEXT: sll a0, a0, a1102; RV32XTHEADBB-NEXT: or a0, a2, a0103; RV32XTHEADBB-NEXT: ret104;105; RV64XTHEADBB-LABEL: rotr_32:106; RV64XTHEADBB: # %bb.0:107; RV64XTHEADBB-NEXT: srlw a2, a0, a1108; RV64XTHEADBB-NEXT: neg a1, a1109; RV64XTHEADBB-NEXT: sllw a0, a0, a1110; RV64XTHEADBB-NEXT: or a0, a2, a0111; RV64XTHEADBB-NEXT: ret112 %z = sub i32 32, %y113 %b = lshr i32 %x, %y114 %c = shl i32 %x, %z115 %d = or i32 %b, %c116 ret i32 %d117}118 119define i64 @rotl_64(i64 %x, i64 %y) nounwind {120; RV32I-LABEL: rotl_64:121; RV32I: # %bb.0:122; RV32I-NEXT: addi a5, a2, -32123; RV32I-NEXT: sll a4, a0, a2124; RV32I-NEXT: bltz a5, .LBB2_2125; RV32I-NEXT: # %bb.1:126; RV32I-NEXT: mv a3, a4127; RV32I-NEXT: j .LBB2_3128; RV32I-NEXT: .LBB2_2:129; RV32I-NEXT: sll a3, a1, a2130; RV32I-NEXT: not a6, a2131; RV32I-NEXT: srli a7, a0, 1132; RV32I-NEXT: srl a6, a7, a6133; RV32I-NEXT: or a3, a3, a6134; RV32I-NEXT: .LBB2_3:135; RV32I-NEXT: srai a5, a5, 31136; RV32I-NEXT: neg a7, a2137; RV32I-NEXT: li a6, 32138; RV32I-NEXT: and a4, a5, a4139; RV32I-NEXT: sub a5, a6, a2140; RV32I-NEXT: srl a6, a1, a7141; RV32I-NEXT: bltz a5, .LBB2_5142; RV32I-NEXT: # %bb.4:143; RV32I-NEXT: mv a0, a6144; RV32I-NEXT: j .LBB2_6145; RV32I-NEXT: .LBB2_5:146; RV32I-NEXT: srl a0, a0, a7147; RV32I-NEXT: li a7, 64148; RV32I-NEXT: sub a2, a7, a2149; RV32I-NEXT: not a2, a2150; RV32I-NEXT: slli a1, a1, 1151; RV32I-NEXT: sll a1, a1, a2152; RV32I-NEXT: or a0, a0, a1153; RV32I-NEXT: .LBB2_6:154; RV32I-NEXT: srai a5, a5, 31155; RV32I-NEXT: and a1, a5, a6156; RV32I-NEXT: or a1, a3, a1157; RV32I-NEXT: or a0, a4, a0158; RV32I-NEXT: ret159;160; RV64I-LABEL: rotl_64:161; RV64I: # %bb.0:162; RV64I-NEXT: neg a2, a1163; RV64I-NEXT: sll a1, a0, a1164; RV64I-NEXT: srl a0, a0, a2165; RV64I-NEXT: or a0, a1, a0166; RV64I-NEXT: ret167;168; RV32ZBB-LABEL: rotl_64:169; RV32ZBB: # %bb.0:170; RV32ZBB-NEXT: addi a5, a2, -32171; RV32ZBB-NEXT: sll a4, a0, a2172; RV32ZBB-NEXT: bltz a5, .LBB2_2173; RV32ZBB-NEXT: # %bb.1:174; RV32ZBB-NEXT: mv a3, a4175; RV32ZBB-NEXT: j .LBB2_3176; RV32ZBB-NEXT: .LBB2_2:177; RV32ZBB-NEXT: sll a3, a1, a2178; RV32ZBB-NEXT: not a6, a2179; RV32ZBB-NEXT: srli a7, a0, 1180; RV32ZBB-NEXT: srl a6, a7, a6181; RV32ZBB-NEXT: or a3, a3, a6182; RV32ZBB-NEXT: .LBB2_3:183; RV32ZBB-NEXT: srai a5, a5, 31184; RV32ZBB-NEXT: neg a7, a2185; RV32ZBB-NEXT: li a6, 32186; RV32ZBB-NEXT: and a4, a5, a4187; RV32ZBB-NEXT: sub a5, a6, a2188; RV32ZBB-NEXT: srl a6, a1, a7189; RV32ZBB-NEXT: bltz a5, .LBB2_5190; RV32ZBB-NEXT: # %bb.4:191; RV32ZBB-NEXT: mv a0, a6192; RV32ZBB-NEXT: j .LBB2_6193; RV32ZBB-NEXT: .LBB2_5:194; RV32ZBB-NEXT: srl a0, a0, a7195; RV32ZBB-NEXT: li a7, 64196; RV32ZBB-NEXT: sub a2, a7, a2197; RV32ZBB-NEXT: not a2, a2198; RV32ZBB-NEXT: slli a1, a1, 1199; RV32ZBB-NEXT: sll a1, a1, a2200; RV32ZBB-NEXT: or a0, a0, a1201; RV32ZBB-NEXT: .LBB2_6:202; RV32ZBB-NEXT: srai a5, a5, 31203; RV32ZBB-NEXT: and a1, a5, a6204; RV32ZBB-NEXT: or a1, a3, a1205; RV32ZBB-NEXT: or a0, a4, a0206; RV32ZBB-NEXT: ret207;208; RV64ZBB-LABEL: rotl_64:209; RV64ZBB: # %bb.0:210; RV64ZBB-NEXT: rol a0, a0, a1211; RV64ZBB-NEXT: ret212;213; RV32XTHEADBB-LABEL: rotl_64:214; RV32XTHEADBB: # %bb.0:215; RV32XTHEADBB-NEXT: addi a5, a2, -32216; RV32XTHEADBB-NEXT: sll a4, a0, a2217; RV32XTHEADBB-NEXT: bltz a5, .LBB2_2218; RV32XTHEADBB-NEXT: # %bb.1:219; RV32XTHEADBB-NEXT: mv a3, a4220; RV32XTHEADBB-NEXT: j .LBB2_3221; RV32XTHEADBB-NEXT: .LBB2_2:222; RV32XTHEADBB-NEXT: sll a3, a1, a2223; RV32XTHEADBB-NEXT: not a6, a2224; RV32XTHEADBB-NEXT: srli a7, a0, 1225; RV32XTHEADBB-NEXT: srl a6, a7, a6226; RV32XTHEADBB-NEXT: or a3, a3, a6227; RV32XTHEADBB-NEXT: .LBB2_3:228; RV32XTHEADBB-NEXT: srai a5, a5, 31229; RV32XTHEADBB-NEXT: neg a7, a2230; RV32XTHEADBB-NEXT: li a6, 32231; RV32XTHEADBB-NEXT: and a4, a5, a4232; RV32XTHEADBB-NEXT: sub a5, a6, a2233; RV32XTHEADBB-NEXT: srl a6, a1, a7234; RV32XTHEADBB-NEXT: bltz a5, .LBB2_5235; RV32XTHEADBB-NEXT: # %bb.4:236; RV32XTHEADBB-NEXT: mv a0, a6237; RV32XTHEADBB-NEXT: j .LBB2_6238; RV32XTHEADBB-NEXT: .LBB2_5:239; RV32XTHEADBB-NEXT: srl a0, a0, a7240; RV32XTHEADBB-NEXT: li a7, 64241; RV32XTHEADBB-NEXT: sub a2, a7, a2242; RV32XTHEADBB-NEXT: not a2, a2243; RV32XTHEADBB-NEXT: slli a1, a1, 1244; RV32XTHEADBB-NEXT: sll a1, a1, a2245; RV32XTHEADBB-NEXT: or a0, a0, a1246; RV32XTHEADBB-NEXT: .LBB2_6:247; RV32XTHEADBB-NEXT: srai a5, a5, 31248; RV32XTHEADBB-NEXT: and a1, a5, a6249; RV32XTHEADBB-NEXT: or a1, a3, a1250; RV32XTHEADBB-NEXT: or a0, a4, a0251; RV32XTHEADBB-NEXT: ret252;253; RV64XTHEADBB-LABEL: rotl_64:254; RV64XTHEADBB: # %bb.0:255; RV64XTHEADBB-NEXT: sll a2, a0, a1256; RV64XTHEADBB-NEXT: neg a1, a1257; RV64XTHEADBB-NEXT: srl a0, a0, a1258; RV64XTHEADBB-NEXT: or a0, a2, a0259; RV64XTHEADBB-NEXT: ret260 %z = sub i64 64, %y261 %b = shl i64 %x, %y262 %c = lshr i64 %x, %z263 %d = or i64 %b, %c264 ret i64 %d265}266 267define i64 @rotr_64(i64 %x, i64 %y) nounwind {268; RV32I-LABEL: rotr_64:269; RV32I: # %bb.0:270; RV32I-NEXT: addi a5, a2, -32271; RV32I-NEXT: srl a4, a1, a2272; RV32I-NEXT: bltz a5, .LBB3_2273; RV32I-NEXT: # %bb.1:274; RV32I-NEXT: mv a3, a4275; RV32I-NEXT: j .LBB3_3276; RV32I-NEXT: .LBB3_2:277; RV32I-NEXT: srl a3, a0, a2278; RV32I-NEXT: not a6, a2279; RV32I-NEXT: slli a7, a1, 1280; RV32I-NEXT: sll a6, a7, a6281; RV32I-NEXT: or a3, a3, a6282; RV32I-NEXT: .LBB3_3:283; RV32I-NEXT: srai a5, a5, 31284; RV32I-NEXT: neg a7, a2285; RV32I-NEXT: li a6, 32286; RV32I-NEXT: and a4, a5, a4287; RV32I-NEXT: sub a5, a6, a2288; RV32I-NEXT: sll a6, a0, a7289; RV32I-NEXT: bltz a5, .LBB3_5290; RV32I-NEXT: # %bb.4:291; RV32I-NEXT: mv a1, a6292; RV32I-NEXT: j .LBB3_6293; RV32I-NEXT: .LBB3_5:294; RV32I-NEXT: sll a1, a1, a7295; RV32I-NEXT: li a7, 64296; RV32I-NEXT: sub a2, a7, a2297; RV32I-NEXT: not a2, a2298; RV32I-NEXT: srli a0, a0, 1299; RV32I-NEXT: srl a0, a0, a2300; RV32I-NEXT: or a1, a1, a0301; RV32I-NEXT: .LBB3_6:302; RV32I-NEXT: srai a5, a5, 31303; RV32I-NEXT: and a0, a5, a6304; RV32I-NEXT: or a0, a3, a0305; RV32I-NEXT: or a1, a4, a1306; RV32I-NEXT: ret307;308; RV64I-LABEL: rotr_64:309; RV64I: # %bb.0:310; RV64I-NEXT: neg a2, a1311; RV64I-NEXT: srl a1, a0, a1312; RV64I-NEXT: sll a0, a0, a2313; RV64I-NEXT: or a0, a1, a0314; RV64I-NEXT: ret315;316; RV32ZBB-LABEL: rotr_64:317; RV32ZBB: # %bb.0:318; RV32ZBB-NEXT: addi a5, a2, -32319; RV32ZBB-NEXT: srl a4, a1, a2320; RV32ZBB-NEXT: bltz a5, .LBB3_2321; RV32ZBB-NEXT: # %bb.1:322; RV32ZBB-NEXT: mv a3, a4323; RV32ZBB-NEXT: j .LBB3_3324; RV32ZBB-NEXT: .LBB3_2:325; RV32ZBB-NEXT: srl a3, a0, a2326; RV32ZBB-NEXT: not a6, a2327; RV32ZBB-NEXT: slli a7, a1, 1328; RV32ZBB-NEXT: sll a6, a7, a6329; RV32ZBB-NEXT: or a3, a3, a6330; RV32ZBB-NEXT: .LBB3_3:331; RV32ZBB-NEXT: srai a5, a5, 31332; RV32ZBB-NEXT: neg a7, a2333; RV32ZBB-NEXT: li a6, 32334; RV32ZBB-NEXT: and a4, a5, a4335; RV32ZBB-NEXT: sub a5, a6, a2336; RV32ZBB-NEXT: sll a6, a0, a7337; RV32ZBB-NEXT: bltz a5, .LBB3_5338; RV32ZBB-NEXT: # %bb.4:339; RV32ZBB-NEXT: mv a1, a6340; RV32ZBB-NEXT: j .LBB3_6341; RV32ZBB-NEXT: .LBB3_5:342; RV32ZBB-NEXT: sll a1, a1, a7343; RV32ZBB-NEXT: li a7, 64344; RV32ZBB-NEXT: sub a2, a7, a2345; RV32ZBB-NEXT: not a2, a2346; RV32ZBB-NEXT: srli a0, a0, 1347; RV32ZBB-NEXT: srl a0, a0, a2348; RV32ZBB-NEXT: or a1, a1, a0349; RV32ZBB-NEXT: .LBB3_6:350; RV32ZBB-NEXT: srai a5, a5, 31351; RV32ZBB-NEXT: and a0, a5, a6352; RV32ZBB-NEXT: or a0, a3, a0353; RV32ZBB-NEXT: or a1, a4, a1354; RV32ZBB-NEXT: ret355;356; RV64ZBB-LABEL: rotr_64:357; RV64ZBB: # %bb.0:358; RV64ZBB-NEXT: ror a0, a0, a1359; RV64ZBB-NEXT: ret360;361; RV32XTHEADBB-LABEL: rotr_64:362; RV32XTHEADBB: # %bb.0:363; RV32XTHEADBB-NEXT: addi a5, a2, -32364; RV32XTHEADBB-NEXT: srl a4, a1, a2365; RV32XTHEADBB-NEXT: bltz a5, .LBB3_2366; RV32XTHEADBB-NEXT: # %bb.1:367; RV32XTHEADBB-NEXT: mv a3, a4368; RV32XTHEADBB-NEXT: j .LBB3_3369; RV32XTHEADBB-NEXT: .LBB3_2:370; RV32XTHEADBB-NEXT: srl a3, a0, a2371; RV32XTHEADBB-NEXT: not a6, a2372; RV32XTHEADBB-NEXT: slli a7, a1, 1373; RV32XTHEADBB-NEXT: sll a6, a7, a6374; RV32XTHEADBB-NEXT: or a3, a3, a6375; RV32XTHEADBB-NEXT: .LBB3_3:376; RV32XTHEADBB-NEXT: srai a5, a5, 31377; RV32XTHEADBB-NEXT: neg a7, a2378; RV32XTHEADBB-NEXT: li a6, 32379; RV32XTHEADBB-NEXT: and a4, a5, a4380; RV32XTHEADBB-NEXT: sub a5, a6, a2381; RV32XTHEADBB-NEXT: sll a6, a0, a7382; RV32XTHEADBB-NEXT: bltz a5, .LBB3_5383; RV32XTHEADBB-NEXT: # %bb.4:384; RV32XTHEADBB-NEXT: mv a1, a6385; RV32XTHEADBB-NEXT: j .LBB3_6386; RV32XTHEADBB-NEXT: .LBB3_5:387; RV32XTHEADBB-NEXT: sll a1, a1, a7388; RV32XTHEADBB-NEXT: li a7, 64389; RV32XTHEADBB-NEXT: sub a2, a7, a2390; RV32XTHEADBB-NEXT: not a2, a2391; RV32XTHEADBB-NEXT: srli a0, a0, 1392; RV32XTHEADBB-NEXT: srl a0, a0, a2393; RV32XTHEADBB-NEXT: or a1, a1, a0394; RV32XTHEADBB-NEXT: .LBB3_6:395; RV32XTHEADBB-NEXT: srai a5, a5, 31396; RV32XTHEADBB-NEXT: and a0, a5, a6397; RV32XTHEADBB-NEXT: or a0, a3, a0398; RV32XTHEADBB-NEXT: or a1, a4, a1399; RV32XTHEADBB-NEXT: ret400;401; RV64XTHEADBB-LABEL: rotr_64:402; RV64XTHEADBB: # %bb.0:403; RV64XTHEADBB-NEXT: srl a2, a0, a1404; RV64XTHEADBB-NEXT: neg a1, a1405; RV64XTHEADBB-NEXT: sll a0, a0, a1406; RV64XTHEADBB-NEXT: or a0, a2, a0407; RV64XTHEADBB-NEXT: ret408 %z = sub i64 64, %y409 %b = lshr i64 %x, %y410 %c = shl i64 %x, %z411 %d = or i64 %b, %c412 ret i64 %d413}414 415define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {416; RV32I-LABEL: rotl_32_mask:417; RV32I: # %bb.0:418; RV32I-NEXT: neg a2, a1419; RV32I-NEXT: sll a1, a0, a1420; RV32I-NEXT: srl a0, a0, a2421; RV32I-NEXT: or a0, a1, a0422; RV32I-NEXT: ret423;424; RV64I-LABEL: rotl_32_mask:425; RV64I: # %bb.0:426; RV64I-NEXT: neg a2, a1427; RV64I-NEXT: sllw a1, a0, a1428; RV64I-NEXT: srlw a0, a0, a2429; RV64I-NEXT: or a0, a1, a0430; RV64I-NEXT: ret431;432; RV32ZBB-LABEL: rotl_32_mask:433; RV32ZBB: # %bb.0:434; RV32ZBB-NEXT: rol a0, a0, a1435; RV32ZBB-NEXT: ret436;437; RV64ZBB-LABEL: rotl_32_mask:438; RV64ZBB: # %bb.0:439; RV64ZBB-NEXT: rolw a0, a0, a1440; RV64ZBB-NEXT: ret441;442; RV32XTHEADBB-LABEL: rotl_32_mask:443; RV32XTHEADBB: # %bb.0:444; RV32XTHEADBB-NEXT: sll a2, a0, a1445; RV32XTHEADBB-NEXT: neg a1, a1446; RV32XTHEADBB-NEXT: srl a0, a0, a1447; RV32XTHEADBB-NEXT: or a0, a2, a0448; RV32XTHEADBB-NEXT: ret449;450; RV64XTHEADBB-LABEL: rotl_32_mask:451; RV64XTHEADBB: # %bb.0:452; RV64XTHEADBB-NEXT: sllw a2, a0, a1453; RV64XTHEADBB-NEXT: neg a1, a1454; RV64XTHEADBB-NEXT: srlw a0, a0, a1455; RV64XTHEADBB-NEXT: or a0, a2, a0456; RV64XTHEADBB-NEXT: ret457 %z = sub i32 0, %y458 %and = and i32 %z, 31459 %b = shl i32 %x, %y460 %c = lshr i32 %x, %and461 %d = or i32 %b, %c462 ret i32 %d463}464 465define i32 @rotl_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {466; RV32I-LABEL: rotl_32_mask_and_63_and_31:467; RV32I: # %bb.0:468; RV32I-NEXT: sll a2, a0, a1469; RV32I-NEXT: neg a1, a1470; RV32I-NEXT: srl a0, a0, a1471; RV32I-NEXT: or a0, a2, a0472; RV32I-NEXT: ret473;474; RV64I-LABEL: rotl_32_mask_and_63_and_31:475; RV64I: # %bb.0:476; RV64I-NEXT: sllw a2, a0, a1477; RV64I-NEXT: neg a1, a1478; RV64I-NEXT: srlw a0, a0, a1479; RV64I-NEXT: or a0, a2, a0480; RV64I-NEXT: ret481;482; RV32ZBB-LABEL: rotl_32_mask_and_63_and_31:483; RV32ZBB: # %bb.0:484; RV32ZBB-NEXT: rol a0, a0, a1485; RV32ZBB-NEXT: ret486;487; RV64ZBB-LABEL: rotl_32_mask_and_63_and_31:488; RV64ZBB: # %bb.0:489; RV64ZBB-NEXT: rolw a0, a0, a1490; RV64ZBB-NEXT: ret491;492; RV32XTHEADBB-LABEL: rotl_32_mask_and_63_and_31:493; RV32XTHEADBB: # %bb.0:494; RV32XTHEADBB-NEXT: sll a2, a0, a1495; RV32XTHEADBB-NEXT: neg a1, a1496; RV32XTHEADBB-NEXT: srl a0, a0, a1497; RV32XTHEADBB-NEXT: or a0, a2, a0498; RV32XTHEADBB-NEXT: ret499;500; RV64XTHEADBB-LABEL: rotl_32_mask_and_63_and_31:501; RV64XTHEADBB: # %bb.0:502; RV64XTHEADBB-NEXT: sllw a2, a0, a1503; RV64XTHEADBB-NEXT: neg a1, a1504; RV64XTHEADBB-NEXT: srlw a0, a0, a1505; RV64XTHEADBB-NEXT: or a0, a2, a0506; RV64XTHEADBB-NEXT: ret507 %a = and i32 %y, 63508 %b = shl i32 %x, %a509 %c = sub i32 0, %y510 %d = and i32 %c, 31511 %e = lshr i32 %x, %d512 %f = or i32 %b, %e513 ret i32 %f514}515 516define i32 @rotl_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {517; RV32I-LABEL: rotl_32_mask_or_64_or_32:518; RV32I: # %bb.0:519; RV32I-NEXT: li a0, 0520; RV32I-NEXT: ret521;522; RV64I-LABEL: rotl_32_mask_or_64_or_32:523; RV64I: # %bb.0:524; RV64I-NEXT: li a0, 0525; RV64I-NEXT: ret526;527; RV32ZBB-LABEL: rotl_32_mask_or_64_or_32:528; RV32ZBB: # %bb.0:529; RV32ZBB-NEXT: rol a0, a0, a1530; RV32ZBB-NEXT: ret531;532; RV64ZBB-LABEL: rotl_32_mask_or_64_or_32:533; RV64ZBB: # %bb.0:534; RV64ZBB-NEXT: rolw a0, a0, a1535; RV64ZBB-NEXT: ret536;537; RV32XTHEADBB-LABEL: rotl_32_mask_or_64_or_32:538; RV32XTHEADBB: # %bb.0:539; RV32XTHEADBB-NEXT: sll a2, a0, a1540; RV32XTHEADBB-NEXT: neg a1, a1541; RV32XTHEADBB-NEXT: srl a0, a0, a1542; RV32XTHEADBB-NEXT: or a0, a2, a0543; RV32XTHEADBB-NEXT: ret544;545; RV64XTHEADBB-LABEL: rotl_32_mask_or_64_or_32:546; RV64XTHEADBB: # %bb.0:547; RV64XTHEADBB-NEXT: sllw a2, a0, a1548; RV64XTHEADBB-NEXT: neg a1, a1549; RV64XTHEADBB-NEXT: srlw a0, a0, a1550; RV64XTHEADBB-NEXT: or a0, a2, a0551; RV64XTHEADBB-NEXT: ret552 %a = or i32 %y, 64553 %b = shl i32 %x, %a554 %c = sub i32 0, %y555 %d = or i32 %c, 32556 %e = lshr i32 %x, %d557 %f = or i32 %b, %e558 ret i32 %f559}560 561define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {562; RV32I-LABEL: rotr_32_mask:563; RV32I: # %bb.0:564; RV32I-NEXT: neg a2, a1565; RV32I-NEXT: srl a1, a0, a1566; RV32I-NEXT: sll a0, a0, a2567; RV32I-NEXT: or a0, a1, a0568; RV32I-NEXT: ret569;570; RV64I-LABEL: rotr_32_mask:571; RV64I: # %bb.0:572; RV64I-NEXT: neg a2, a1573; RV64I-NEXT: srlw a1, a0, a1574; RV64I-NEXT: sllw a0, a0, a2575; RV64I-NEXT: or a0, a1, a0576; RV64I-NEXT: ret577;578; RV32ZBB-LABEL: rotr_32_mask:579; RV32ZBB: # %bb.0:580; RV32ZBB-NEXT: ror a0, a0, a1581; RV32ZBB-NEXT: ret582;583; RV64ZBB-LABEL: rotr_32_mask:584; RV64ZBB: # %bb.0:585; RV64ZBB-NEXT: rorw a0, a0, a1586; RV64ZBB-NEXT: ret587;588; RV32XTHEADBB-LABEL: rotr_32_mask:589; RV32XTHEADBB: # %bb.0:590; RV32XTHEADBB-NEXT: srl a2, a0, a1591; RV32XTHEADBB-NEXT: neg a1, a1592; RV32XTHEADBB-NEXT: sll a0, a0, a1593; RV32XTHEADBB-NEXT: or a0, a2, a0594; RV32XTHEADBB-NEXT: ret595;596; RV64XTHEADBB-LABEL: rotr_32_mask:597; RV64XTHEADBB: # %bb.0:598; RV64XTHEADBB-NEXT: srlw a2, a0, a1599; RV64XTHEADBB-NEXT: neg a1, a1600; RV64XTHEADBB-NEXT: sllw a0, a0, a1601; RV64XTHEADBB-NEXT: or a0, a2, a0602; RV64XTHEADBB-NEXT: ret603 %z = sub i32 0, %y604 %and = and i32 %z, 31605 %b = lshr i32 %x, %y606 %c = shl i32 %x, %and607 %d = or i32 %b, %c608 ret i32 %d609}610 611define i32 @rotr_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {612; RV32I-LABEL: rotr_32_mask_and_63_and_31:613; RV32I: # %bb.0:614; RV32I-NEXT: srl a2, a0, a1615; RV32I-NEXT: neg a1, a1616; RV32I-NEXT: sll a0, a0, a1617; RV32I-NEXT: or a0, a2, a0618; RV32I-NEXT: ret619;620; RV64I-LABEL: rotr_32_mask_and_63_and_31:621; RV64I: # %bb.0:622; RV64I-NEXT: srlw a2, a0, a1623; RV64I-NEXT: neg a1, a1624; RV64I-NEXT: sllw a0, a0, a1625; RV64I-NEXT: or a0, a2, a0626; RV64I-NEXT: ret627;628; RV32ZBB-LABEL: rotr_32_mask_and_63_and_31:629; RV32ZBB: # %bb.0:630; RV32ZBB-NEXT: ror a0, a0, a1631; RV32ZBB-NEXT: ret632;633; RV64ZBB-LABEL: rotr_32_mask_and_63_and_31:634; RV64ZBB: # %bb.0:635; RV64ZBB-NEXT: rorw a0, a0, a1636; RV64ZBB-NEXT: ret637;638; RV32XTHEADBB-LABEL: rotr_32_mask_and_63_and_31:639; RV32XTHEADBB: # %bb.0:640; RV32XTHEADBB-NEXT: srl a2, a0, a1641; RV32XTHEADBB-NEXT: neg a1, a1642; RV32XTHEADBB-NEXT: sll a0, a0, a1643; RV32XTHEADBB-NEXT: or a0, a2, a0644; RV32XTHEADBB-NEXT: ret645;646; RV64XTHEADBB-LABEL: rotr_32_mask_and_63_and_31:647; RV64XTHEADBB: # %bb.0:648; RV64XTHEADBB-NEXT: srlw a2, a0, a1649; RV64XTHEADBB-NEXT: neg a1, a1650; RV64XTHEADBB-NEXT: sllw a0, a0, a1651; RV64XTHEADBB-NEXT: or a0, a2, a0652; RV64XTHEADBB-NEXT: ret653 %a = and i32 %y, 63654 %b = lshr i32 %x, %a655 %c = sub i32 0, %y656 %d = and i32 %c, 31657 %e = shl i32 %x, %d658 %f = or i32 %b, %e659 ret i32 %f660}661 662define i32 @rotr_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {663; RV32I-LABEL: rotr_32_mask_or_64_or_32:664; RV32I: # %bb.0:665; RV32I-NEXT: li a0, 0666; RV32I-NEXT: ret667;668; RV64I-LABEL: rotr_32_mask_or_64_or_32:669; RV64I: # %bb.0:670; RV64I-NEXT: li a0, 0671; RV64I-NEXT: ret672;673; RV32ZBB-LABEL: rotr_32_mask_or_64_or_32:674; RV32ZBB: # %bb.0:675; RV32ZBB-NEXT: ror a0, a0, a1676; RV32ZBB-NEXT: ret677;678; RV64ZBB-LABEL: rotr_32_mask_or_64_or_32:679; RV64ZBB: # %bb.0:680; RV64ZBB-NEXT: rorw a0, a0, a1681; RV64ZBB-NEXT: ret682;683; RV32XTHEADBB-LABEL: rotr_32_mask_or_64_or_32:684; RV32XTHEADBB: # %bb.0:685; RV32XTHEADBB-NEXT: srl a2, a0, a1686; RV32XTHEADBB-NEXT: neg a1, a1687; RV32XTHEADBB-NEXT: sll a0, a0, a1688; RV32XTHEADBB-NEXT: or a0, a2, a0689; RV32XTHEADBB-NEXT: ret690;691; RV64XTHEADBB-LABEL: rotr_32_mask_or_64_or_32:692; RV64XTHEADBB: # %bb.0:693; RV64XTHEADBB-NEXT: srlw a2, a0, a1694; RV64XTHEADBB-NEXT: neg a1, a1695; RV64XTHEADBB-NEXT: sllw a0, a0, a1696; RV64XTHEADBB-NEXT: or a0, a2, a0697; RV64XTHEADBB-NEXT: ret698 %a = or i32 %y, 64699 %b = lshr i32 %x, %a700 %c = sub i32 0, %y701 %d = or i32 %c, 32702 %e = shl i32 %x, %d703 %f = or i32 %b, %e704 ret i32 %f705}706 707define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {708; RV32I-LABEL: rotl_64_mask:709; RV32I: # %bb.0:710; RV32I-NEXT: addi a5, a2, -32711; RV32I-NEXT: sll a4, a0, a2712; RV32I-NEXT: bltz a5, .LBB10_2713; RV32I-NEXT: # %bb.1:714; RV32I-NEXT: mv a3, a4715; RV32I-NEXT: j .LBB10_3716; RV32I-NEXT: .LBB10_2:717; RV32I-NEXT: sll a3, a1, a2718; RV32I-NEXT: not a6, a2719; RV32I-NEXT: srli a7, a0, 1720; RV32I-NEXT: srl a6, a7, a6721; RV32I-NEXT: or a3, a3, a6722; RV32I-NEXT: .LBB10_3:723; RV32I-NEXT: srai t0, a5, 31724; RV32I-NEXT: neg a5, a2725; RV32I-NEXT: andi a7, a5, 63726; RV32I-NEXT: addi a6, a7, -32727; RV32I-NEXT: and a2, t0, a4728; RV32I-NEXT: bltz a6, .LBB10_5729; RV32I-NEXT: # %bb.4:730; RV32I-NEXT: srl a0, a1, a7731; RV32I-NEXT: j .LBB10_6732; RV32I-NEXT: .LBB10_5:733; RV32I-NEXT: srl a0, a0, a5734; RV32I-NEXT: not a4, a7735; RV32I-NEXT: slli a7, a1, 1736; RV32I-NEXT: sll a4, a7, a4737; RV32I-NEXT: or a0, a0, a4738; RV32I-NEXT: .LBB10_6:739; RV32I-NEXT: srl a1, a1, a5740; RV32I-NEXT: srai a4, a6, 31741; RV32I-NEXT: and a1, a4, a1742; RV32I-NEXT: or a1, a3, a1743; RV32I-NEXT: or a0, a2, a0744; RV32I-NEXT: ret745;746; RV64I-LABEL: rotl_64_mask:747; RV64I: # %bb.0:748; RV64I-NEXT: neg a2, a1749; RV64I-NEXT: sll a1, a0, a1750; RV64I-NEXT: srl a0, a0, a2751; RV64I-NEXT: or a0, a1, a0752; RV64I-NEXT: ret753;754; RV32ZBB-LABEL: rotl_64_mask:755; RV32ZBB: # %bb.0:756; RV32ZBB-NEXT: addi a5, a2, -32757; RV32ZBB-NEXT: sll a4, a0, a2758; RV32ZBB-NEXT: bltz a5, .LBB10_2759; RV32ZBB-NEXT: # %bb.1:760; RV32ZBB-NEXT: mv a3, a4761; RV32ZBB-NEXT: j .LBB10_3762; RV32ZBB-NEXT: .LBB10_2:763; RV32ZBB-NEXT: sll a3, a1, a2764; RV32ZBB-NEXT: not a6, a2765; RV32ZBB-NEXT: srli a7, a0, 1766; RV32ZBB-NEXT: srl a6, a7, a6767; RV32ZBB-NEXT: or a3, a3, a6768; RV32ZBB-NEXT: .LBB10_3:769; RV32ZBB-NEXT: srai t0, a5, 31770; RV32ZBB-NEXT: neg a5, a2771; RV32ZBB-NEXT: andi a7, a5, 63772; RV32ZBB-NEXT: addi a6, a7, -32773; RV32ZBB-NEXT: and a2, t0, a4774; RV32ZBB-NEXT: bltz a6, .LBB10_5775; RV32ZBB-NEXT: # %bb.4:776; RV32ZBB-NEXT: srl a0, a1, a7777; RV32ZBB-NEXT: j .LBB10_6778; RV32ZBB-NEXT: .LBB10_5:779; RV32ZBB-NEXT: srl a0, a0, a5780; RV32ZBB-NEXT: not a4, a7781; RV32ZBB-NEXT: slli a7, a1, 1782; RV32ZBB-NEXT: sll a4, a7, a4783; RV32ZBB-NEXT: or a0, a0, a4784; RV32ZBB-NEXT: .LBB10_6:785; RV32ZBB-NEXT: srl a1, a1, a5786; RV32ZBB-NEXT: srai a4, a6, 31787; RV32ZBB-NEXT: and a1, a4, a1788; RV32ZBB-NEXT: or a1, a3, a1789; RV32ZBB-NEXT: or a0, a2, a0790; RV32ZBB-NEXT: ret791;792; RV64ZBB-LABEL: rotl_64_mask:793; RV64ZBB: # %bb.0:794; RV64ZBB-NEXT: rol a0, a0, a1795; RV64ZBB-NEXT: ret796;797; RV32XTHEADBB-LABEL: rotl_64_mask:798; RV32XTHEADBB: # %bb.0:799; RV32XTHEADBB-NEXT: addi a5, a2, -32800; RV32XTHEADBB-NEXT: sll a4, a0, a2801; RV32XTHEADBB-NEXT: bltz a5, .LBB10_2802; RV32XTHEADBB-NEXT: # %bb.1:803; RV32XTHEADBB-NEXT: mv a3, a4804; RV32XTHEADBB-NEXT: j .LBB10_3805; RV32XTHEADBB-NEXT: .LBB10_2:806; RV32XTHEADBB-NEXT: sll a3, a1, a2807; RV32XTHEADBB-NEXT: not a6, a2808; RV32XTHEADBB-NEXT: srli a7, a0, 1809; RV32XTHEADBB-NEXT: srl a6, a7, a6810; RV32XTHEADBB-NEXT: or a3, a3, a6811; RV32XTHEADBB-NEXT: .LBB10_3:812; RV32XTHEADBB-NEXT: srai t0, a5, 31813; RV32XTHEADBB-NEXT: neg a5, a2814; RV32XTHEADBB-NEXT: andi a7, a5, 63815; RV32XTHEADBB-NEXT: addi a6, a7, -32816; RV32XTHEADBB-NEXT: and a2, t0, a4817; RV32XTHEADBB-NEXT: bltz a6, .LBB10_5818; RV32XTHEADBB-NEXT: # %bb.4:819; RV32XTHEADBB-NEXT: srl a0, a1, a7820; RV32XTHEADBB-NEXT: j .LBB10_6821; RV32XTHEADBB-NEXT: .LBB10_5:822; RV32XTHEADBB-NEXT: srl a0, a0, a5823; RV32XTHEADBB-NEXT: not a4, a7824; RV32XTHEADBB-NEXT: slli a7, a1, 1825; RV32XTHEADBB-NEXT: sll a4, a7, a4826; RV32XTHEADBB-NEXT: or a0, a0, a4827; RV32XTHEADBB-NEXT: .LBB10_6:828; RV32XTHEADBB-NEXT: srl a1, a1, a5829; RV32XTHEADBB-NEXT: srai a4, a6, 31830; RV32XTHEADBB-NEXT: and a1, a4, a1831; RV32XTHEADBB-NEXT: or a1, a3, a1832; RV32XTHEADBB-NEXT: or a0, a2, a0833; RV32XTHEADBB-NEXT: ret834;835; RV64XTHEADBB-LABEL: rotl_64_mask:836; RV64XTHEADBB: # %bb.0:837; RV64XTHEADBB-NEXT: sll a2, a0, a1838; RV64XTHEADBB-NEXT: neg a1, a1839; RV64XTHEADBB-NEXT: srl a0, a0, a1840; RV64XTHEADBB-NEXT: or a0, a2, a0841; RV64XTHEADBB-NEXT: ret842 %z = sub i64 0, %y843 %and = and i64 %z, 63844 %b = shl i64 %x, %y845 %c = lshr i64 %x, %and846 %d = or i64 %b, %c847 ret i64 %d848}849 850define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {851; RV32I-LABEL: rotl_64_mask_and_127_and_63:852; RV32I: # %bb.0:853; RV32I-NEXT: andi a3, a2, 127854; RV32I-NEXT: addi a4, a3, -32855; RV32I-NEXT: bltz a4, .LBB11_2856; RV32I-NEXT: # %bb.1:857; RV32I-NEXT: sll a3, a0, a3858; RV32I-NEXT: j .LBB11_3859; RV32I-NEXT: .LBB11_2:860; RV32I-NEXT: sll a5, a1, a2861; RV32I-NEXT: srli a6, a0, 1862; RV32I-NEXT: not a3, a3863; RV32I-NEXT: srl a3, a6, a3864; RV32I-NEXT: or a3, a5, a3865; RV32I-NEXT: .LBB11_3:866; RV32I-NEXT: sll a7, a0, a2867; RV32I-NEXT: srai t0, a4, 31868; RV32I-NEXT: neg a4, a2869; RV32I-NEXT: andi a6, a4, 63870; RV32I-NEXT: addi a5, a6, -32871; RV32I-NEXT: and a2, t0, a7872; RV32I-NEXT: bltz a5, .LBB11_5873; RV32I-NEXT: # %bb.4:874; RV32I-NEXT: srl a0, a1, a6875; RV32I-NEXT: j .LBB11_6876; RV32I-NEXT: .LBB11_5:877; RV32I-NEXT: srl a0, a0, a4878; RV32I-NEXT: not a6, a6879; RV32I-NEXT: slli a7, a1, 1880; RV32I-NEXT: sll a6, a7, a6881; RV32I-NEXT: or a0, a0, a6882; RV32I-NEXT: .LBB11_6:883; RV32I-NEXT: srl a1, a1, a4884; RV32I-NEXT: srai a5, a5, 31885; RV32I-NEXT: and a1, a5, a1886; RV32I-NEXT: or a1, a3, a1887; RV32I-NEXT: or a0, a2, a0888; RV32I-NEXT: ret889;890; RV64I-LABEL: rotl_64_mask_and_127_and_63:891; RV64I: # %bb.0:892; RV64I-NEXT: sll a2, a0, a1893; RV64I-NEXT: neg a1, a1894; RV64I-NEXT: srl a0, a0, a1895; RV64I-NEXT: or a0, a2, a0896; RV64I-NEXT: ret897;898; RV32ZBB-LABEL: rotl_64_mask_and_127_and_63:899; RV32ZBB: # %bb.0:900; RV32ZBB-NEXT: andi a3, a2, 127901; RV32ZBB-NEXT: addi a4, a3, -32902; RV32ZBB-NEXT: bltz a4, .LBB11_2903; RV32ZBB-NEXT: # %bb.1:904; RV32ZBB-NEXT: sll a3, a0, a3905; RV32ZBB-NEXT: j .LBB11_3906; RV32ZBB-NEXT: .LBB11_2:907; RV32ZBB-NEXT: sll a5, a1, a2908; RV32ZBB-NEXT: srli a6, a0, 1909; RV32ZBB-NEXT: not a3, a3910; RV32ZBB-NEXT: srl a3, a6, a3911; RV32ZBB-NEXT: or a3, a5, a3912; RV32ZBB-NEXT: .LBB11_3:913; RV32ZBB-NEXT: sll a7, a0, a2914; RV32ZBB-NEXT: srai t0, a4, 31915; RV32ZBB-NEXT: neg a4, a2916; RV32ZBB-NEXT: andi a6, a4, 63917; RV32ZBB-NEXT: addi a5, a6, -32918; RV32ZBB-NEXT: and a2, t0, a7919; RV32ZBB-NEXT: bltz a5, .LBB11_5920; RV32ZBB-NEXT: # %bb.4:921; RV32ZBB-NEXT: srl a0, a1, a6922; RV32ZBB-NEXT: j .LBB11_6923; RV32ZBB-NEXT: .LBB11_5:924; RV32ZBB-NEXT: srl a0, a0, a4925; RV32ZBB-NEXT: not a6, a6926; RV32ZBB-NEXT: slli a7, a1, 1927; RV32ZBB-NEXT: sll a6, a7, a6928; RV32ZBB-NEXT: or a0, a0, a6929; RV32ZBB-NEXT: .LBB11_6:930; RV32ZBB-NEXT: srl a1, a1, a4931; RV32ZBB-NEXT: srai a5, a5, 31932; RV32ZBB-NEXT: and a1, a5, a1933; RV32ZBB-NEXT: or a1, a3, a1934; RV32ZBB-NEXT: or a0, a2, a0935; RV32ZBB-NEXT: ret936;937; RV64ZBB-LABEL: rotl_64_mask_and_127_and_63:938; RV64ZBB: # %bb.0:939; RV64ZBB-NEXT: rol a0, a0, a1940; RV64ZBB-NEXT: ret941;942; RV32XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:943; RV32XTHEADBB: # %bb.0:944; RV32XTHEADBB-NEXT: andi a3, a2, 127945; RV32XTHEADBB-NEXT: addi a4, a3, -32946; RV32XTHEADBB-NEXT: bltz a4, .LBB11_2947; RV32XTHEADBB-NEXT: # %bb.1:948; RV32XTHEADBB-NEXT: sll a3, a0, a3949; RV32XTHEADBB-NEXT: j .LBB11_3950; RV32XTHEADBB-NEXT: .LBB11_2:951; RV32XTHEADBB-NEXT: sll a5, a1, a2952; RV32XTHEADBB-NEXT: srli a6, a0, 1953; RV32XTHEADBB-NEXT: not a3, a3954; RV32XTHEADBB-NEXT: srl a3, a6, a3955; RV32XTHEADBB-NEXT: or a3, a5, a3956; RV32XTHEADBB-NEXT: .LBB11_3:957; RV32XTHEADBB-NEXT: sll a7, a0, a2958; RV32XTHEADBB-NEXT: srai t0, a4, 31959; RV32XTHEADBB-NEXT: neg a4, a2960; RV32XTHEADBB-NEXT: andi a6, a4, 63961; RV32XTHEADBB-NEXT: addi a5, a6, -32962; RV32XTHEADBB-NEXT: and a2, t0, a7963; RV32XTHEADBB-NEXT: bltz a5, .LBB11_5964; RV32XTHEADBB-NEXT: # %bb.4:965; RV32XTHEADBB-NEXT: srl a0, a1, a6966; RV32XTHEADBB-NEXT: j .LBB11_6967; RV32XTHEADBB-NEXT: .LBB11_5:968; RV32XTHEADBB-NEXT: srl a0, a0, a4969; RV32XTHEADBB-NEXT: not a6, a6970; RV32XTHEADBB-NEXT: slli a7, a1, 1971; RV32XTHEADBB-NEXT: sll a6, a7, a6972; RV32XTHEADBB-NEXT: or a0, a0, a6973; RV32XTHEADBB-NEXT: .LBB11_6:974; RV32XTHEADBB-NEXT: srl a1, a1, a4975; RV32XTHEADBB-NEXT: srai a5, a5, 31976; RV32XTHEADBB-NEXT: and a1, a5, a1977; RV32XTHEADBB-NEXT: or a1, a3, a1978; RV32XTHEADBB-NEXT: or a0, a2, a0979; RV32XTHEADBB-NEXT: ret980;981; RV64XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:982; RV64XTHEADBB: # %bb.0:983; RV64XTHEADBB-NEXT: sll a2, a0, a1984; RV64XTHEADBB-NEXT: neg a1, a1985; RV64XTHEADBB-NEXT: srl a0, a0, a1986; RV64XTHEADBB-NEXT: or a0, a2, a0987; RV64XTHEADBB-NEXT: ret988 %a = and i64 %y, 127989 %b = shl i64 %x, %a990 %c = sub i64 0, %y991 %d = and i64 %c, 63992 %e = lshr i64 %x, %d993 %f = or i64 %b, %e994 ret i64 %f995}996 997define i64 @rotl_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {998; RV32I-LABEL: rotl_64_mask_or_128_or_64:999; RV32I: # %bb.0:1000; RV32I-NEXT: li a0, 01001; RV32I-NEXT: li a1, 01002; RV32I-NEXT: ret1003;1004; RV64I-LABEL: rotl_64_mask_or_128_or_64:1005; RV64I: # %bb.0:1006; RV64I-NEXT: li a0, 01007; RV64I-NEXT: ret1008;1009; RV32ZBB-LABEL: rotl_64_mask_or_128_or_64:1010; RV32ZBB: # %bb.0:1011; RV32ZBB-NEXT: li a0, 01012; RV32ZBB-NEXT: li a1, 01013; RV32ZBB-NEXT: ret1014;1015; RV64ZBB-LABEL: rotl_64_mask_or_128_or_64:1016; RV64ZBB: # %bb.0:1017; RV64ZBB-NEXT: rol a0, a0, a11018; RV64ZBB-NEXT: ret1019;1020; RV32XTHEADBB-LABEL: rotl_64_mask_or_128_or_64:1021; RV32XTHEADBB: # %bb.0:1022; RV32XTHEADBB-NEXT: li a0, 01023; RV32XTHEADBB-NEXT: li a1, 01024; RV32XTHEADBB-NEXT: ret1025;1026; RV64XTHEADBB-LABEL: rotl_64_mask_or_128_or_64:1027; RV64XTHEADBB: # %bb.0:1028; RV64XTHEADBB-NEXT: sll a2, a0, a11029; RV64XTHEADBB-NEXT: neg a1, a11030; RV64XTHEADBB-NEXT: srl a0, a0, a11031; RV64XTHEADBB-NEXT: or a0, a2, a01032; RV64XTHEADBB-NEXT: ret1033 %a = or i64 %y, 1281034 %b = shl i64 %x, %a1035 %c = sub i64 0, %y1036 %d = or i64 %c, 641037 %e = lshr i64 %x, %d1038 %f = or i64 %b, %e1039 ret i64 %f1040}1041 1042define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {1043; RV32I-LABEL: rotr_64_mask:1044; RV32I: # %bb.0:1045; RV32I-NEXT: addi a5, a2, -321046; RV32I-NEXT: srl a4, a1, a21047; RV32I-NEXT: bltz a5, .LBB13_21048; RV32I-NEXT: # %bb.1:1049; RV32I-NEXT: mv a3, a41050; RV32I-NEXT: j .LBB13_31051; RV32I-NEXT: .LBB13_2:1052; RV32I-NEXT: srl a3, a0, a21053; RV32I-NEXT: not a6, a21054; RV32I-NEXT: slli a7, a1, 11055; RV32I-NEXT: sll a6, a7, a61056; RV32I-NEXT: or a3, a3, a61057; RV32I-NEXT: .LBB13_3:1058; RV32I-NEXT: srai t0, a5, 311059; RV32I-NEXT: neg a5, a21060; RV32I-NEXT: andi a7, a5, 631061; RV32I-NEXT: addi a6, a7, -321062; RV32I-NEXT: and a2, t0, a41063; RV32I-NEXT: bltz a6, .LBB13_51064; RV32I-NEXT: # %bb.4:1065; RV32I-NEXT: sll a1, a0, a71066; RV32I-NEXT: j .LBB13_61067; RV32I-NEXT: .LBB13_5:1068; RV32I-NEXT: sll a1, a1, a51069; RV32I-NEXT: not a4, a71070; RV32I-NEXT: srli a7, a0, 11071; RV32I-NEXT: srl a4, a7, a41072; RV32I-NEXT: or a1, a1, a41073; RV32I-NEXT: .LBB13_6:1074; RV32I-NEXT: sll a0, a0, a51075; RV32I-NEXT: srai a4, a6, 311076; RV32I-NEXT: and a0, a4, a01077; RV32I-NEXT: or a0, a3, a01078; RV32I-NEXT: or a1, a2, a11079; RV32I-NEXT: ret1080;1081; RV64I-LABEL: rotr_64_mask:1082; RV64I: # %bb.0:1083; RV64I-NEXT: neg a2, a11084; RV64I-NEXT: srl a1, a0, a11085; RV64I-NEXT: sll a0, a0, a21086; RV64I-NEXT: or a0, a1, a01087; RV64I-NEXT: ret1088;1089; RV32ZBB-LABEL: rotr_64_mask:1090; RV32ZBB: # %bb.0:1091; RV32ZBB-NEXT: addi a5, a2, -321092; RV32ZBB-NEXT: srl a4, a1, a21093; RV32ZBB-NEXT: bltz a5, .LBB13_21094; RV32ZBB-NEXT: # %bb.1:1095; RV32ZBB-NEXT: mv a3, a41096; RV32ZBB-NEXT: j .LBB13_31097; RV32ZBB-NEXT: .LBB13_2:1098; RV32ZBB-NEXT: srl a3, a0, a21099; RV32ZBB-NEXT: not a6, a21100; RV32ZBB-NEXT: slli a7, a1, 11101; RV32ZBB-NEXT: sll a6, a7, a61102; RV32ZBB-NEXT: or a3, a3, a61103; RV32ZBB-NEXT: .LBB13_3:1104; RV32ZBB-NEXT: srai t0, a5, 311105; RV32ZBB-NEXT: neg a5, a21106; RV32ZBB-NEXT: andi a7, a5, 631107; RV32ZBB-NEXT: addi a6, a7, -321108; RV32ZBB-NEXT: and a2, t0, a41109; RV32ZBB-NEXT: bltz a6, .LBB13_51110; RV32ZBB-NEXT: # %bb.4:1111; RV32ZBB-NEXT: sll a1, a0, a71112; RV32ZBB-NEXT: j .LBB13_61113; RV32ZBB-NEXT: .LBB13_5:1114; RV32ZBB-NEXT: sll a1, a1, a51115; RV32ZBB-NEXT: not a4, a71116; RV32ZBB-NEXT: srli a7, a0, 11117; RV32ZBB-NEXT: srl a4, a7, a41118; RV32ZBB-NEXT: or a1, a1, a41119; RV32ZBB-NEXT: .LBB13_6:1120; RV32ZBB-NEXT: sll a0, a0, a51121; RV32ZBB-NEXT: srai a4, a6, 311122; RV32ZBB-NEXT: and a0, a4, a01123; RV32ZBB-NEXT: or a0, a3, a01124; RV32ZBB-NEXT: or a1, a2, a11125; RV32ZBB-NEXT: ret1126;1127; RV64ZBB-LABEL: rotr_64_mask:1128; RV64ZBB: # %bb.0:1129; RV64ZBB-NEXT: ror a0, a0, a11130; RV64ZBB-NEXT: ret1131;1132; RV32XTHEADBB-LABEL: rotr_64_mask:1133; RV32XTHEADBB: # %bb.0:1134; RV32XTHEADBB-NEXT: addi a5, a2, -321135; RV32XTHEADBB-NEXT: srl a4, a1, a21136; RV32XTHEADBB-NEXT: bltz a5, .LBB13_21137; RV32XTHEADBB-NEXT: # %bb.1:1138; RV32XTHEADBB-NEXT: mv a3, a41139; RV32XTHEADBB-NEXT: j .LBB13_31140; RV32XTHEADBB-NEXT: .LBB13_2:1141; RV32XTHEADBB-NEXT: srl a3, a0, a21142; RV32XTHEADBB-NEXT: not a6, a21143; RV32XTHEADBB-NEXT: slli a7, a1, 11144; RV32XTHEADBB-NEXT: sll a6, a7, a61145; RV32XTHEADBB-NEXT: or a3, a3, a61146; RV32XTHEADBB-NEXT: .LBB13_3:1147; RV32XTHEADBB-NEXT: srai t0, a5, 311148; RV32XTHEADBB-NEXT: neg a5, a21149; RV32XTHEADBB-NEXT: andi a7, a5, 631150; RV32XTHEADBB-NEXT: addi a6, a7, -321151; RV32XTHEADBB-NEXT: and a2, t0, a41152; RV32XTHEADBB-NEXT: bltz a6, .LBB13_51153; RV32XTHEADBB-NEXT: # %bb.4:1154; RV32XTHEADBB-NEXT: sll a1, a0, a71155; RV32XTHEADBB-NEXT: j .LBB13_61156; RV32XTHEADBB-NEXT: .LBB13_5:1157; RV32XTHEADBB-NEXT: sll a1, a1, a51158; RV32XTHEADBB-NEXT: not a4, a71159; RV32XTHEADBB-NEXT: srli a7, a0, 11160; RV32XTHEADBB-NEXT: srl a4, a7, a41161; RV32XTHEADBB-NEXT: or a1, a1, a41162; RV32XTHEADBB-NEXT: .LBB13_6:1163; RV32XTHEADBB-NEXT: sll a0, a0, a51164; RV32XTHEADBB-NEXT: srai a4, a6, 311165; RV32XTHEADBB-NEXT: and a0, a4, a01166; RV32XTHEADBB-NEXT: or a0, a3, a01167; RV32XTHEADBB-NEXT: or a1, a2, a11168; RV32XTHEADBB-NEXT: ret1169;1170; RV64XTHEADBB-LABEL: rotr_64_mask:1171; RV64XTHEADBB: # %bb.0:1172; RV64XTHEADBB-NEXT: srl a2, a0, a11173; RV64XTHEADBB-NEXT: neg a1, a11174; RV64XTHEADBB-NEXT: sll a0, a0, a11175; RV64XTHEADBB-NEXT: or a0, a2, a01176; RV64XTHEADBB-NEXT: ret1177 %z = sub i64 0, %y1178 %and = and i64 %z, 631179 %b = lshr i64 %x, %y1180 %c = shl i64 %x, %and1181 %d = or i64 %b, %c1182 ret i64 %d1183}1184 1185define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {1186; RV32I-LABEL: rotr_64_mask_and_127_and_63:1187; RV32I: # %bb.0:1188; RV32I-NEXT: andi a3, a2, 1271189; RV32I-NEXT: addi a4, a3, -321190; RV32I-NEXT: bltz a4, .LBB14_21191; RV32I-NEXT: # %bb.1:1192; RV32I-NEXT: srl a3, a1, a31193; RV32I-NEXT: j .LBB14_31194; RV32I-NEXT: .LBB14_2:1195; RV32I-NEXT: srl a5, a0, a21196; RV32I-NEXT: slli a6, a1, 11197; RV32I-NEXT: not a3, a31198; RV32I-NEXT: sll a3, a6, a31199; RV32I-NEXT: or a3, a5, a31200; RV32I-NEXT: .LBB14_3:1201; RV32I-NEXT: srl a7, a1, a21202; RV32I-NEXT: srai t0, a4, 311203; RV32I-NEXT: neg a4, a21204; RV32I-NEXT: andi a6, a4, 631205; RV32I-NEXT: addi a5, a6, -321206; RV32I-NEXT: and a2, t0, a71207; RV32I-NEXT: bltz a5, .LBB14_51208; RV32I-NEXT: # %bb.4:1209; RV32I-NEXT: sll a1, a0, a61210; RV32I-NEXT: j .LBB14_61211; RV32I-NEXT: .LBB14_5:1212; RV32I-NEXT: sll a1, a1, a41213; RV32I-NEXT: not a6, a61214; RV32I-NEXT: srli a7, a0, 11215; RV32I-NEXT: srl a6, a7, a61216; RV32I-NEXT: or a1, a1, a61217; RV32I-NEXT: .LBB14_6:1218; RV32I-NEXT: sll a0, a0, a41219; RV32I-NEXT: srai a5, a5, 311220; RV32I-NEXT: and a0, a5, a01221; RV32I-NEXT: or a0, a3, a01222; RV32I-NEXT: or a1, a2, a11223; RV32I-NEXT: ret1224;1225; RV64I-LABEL: rotr_64_mask_and_127_and_63:1226; RV64I: # %bb.0:1227; RV64I-NEXT: srl a2, a0, a11228; RV64I-NEXT: neg a1, a11229; RV64I-NEXT: sll a0, a0, a11230; RV64I-NEXT: or a0, a2, a01231; RV64I-NEXT: ret1232;1233; RV32ZBB-LABEL: rotr_64_mask_and_127_and_63:1234; RV32ZBB: # %bb.0:1235; RV32ZBB-NEXT: andi a3, a2, 1271236; RV32ZBB-NEXT: addi a4, a3, -321237; RV32ZBB-NEXT: bltz a4, .LBB14_21238; RV32ZBB-NEXT: # %bb.1:1239; RV32ZBB-NEXT: srl a3, a1, a31240; RV32ZBB-NEXT: j .LBB14_31241; RV32ZBB-NEXT: .LBB14_2:1242; RV32ZBB-NEXT: srl a5, a0, a21243; RV32ZBB-NEXT: slli a6, a1, 11244; RV32ZBB-NEXT: not a3, a31245; RV32ZBB-NEXT: sll a3, a6, a31246; RV32ZBB-NEXT: or a3, a5, a31247; RV32ZBB-NEXT: .LBB14_3:1248; RV32ZBB-NEXT: srl a7, a1, a21249; RV32ZBB-NEXT: srai t0, a4, 311250; RV32ZBB-NEXT: neg a4, a21251; RV32ZBB-NEXT: andi a6, a4, 631252; RV32ZBB-NEXT: addi a5, a6, -321253; RV32ZBB-NEXT: and a2, t0, a71254; RV32ZBB-NEXT: bltz a5, .LBB14_51255; RV32ZBB-NEXT: # %bb.4:1256; RV32ZBB-NEXT: sll a1, a0, a61257; RV32ZBB-NEXT: j .LBB14_61258; RV32ZBB-NEXT: .LBB14_5:1259; RV32ZBB-NEXT: sll a1, a1, a41260; RV32ZBB-NEXT: not a6, a61261; RV32ZBB-NEXT: srli a7, a0, 11262; RV32ZBB-NEXT: srl a6, a7, a61263; RV32ZBB-NEXT: or a1, a1, a61264; RV32ZBB-NEXT: .LBB14_6:1265; RV32ZBB-NEXT: sll a0, a0, a41266; RV32ZBB-NEXT: srai a5, a5, 311267; RV32ZBB-NEXT: and a0, a5, a01268; RV32ZBB-NEXT: or a0, a3, a01269; RV32ZBB-NEXT: or a1, a2, a11270; RV32ZBB-NEXT: ret1271;1272; RV64ZBB-LABEL: rotr_64_mask_and_127_and_63:1273; RV64ZBB: # %bb.0:1274; RV64ZBB-NEXT: ror a0, a0, a11275; RV64ZBB-NEXT: ret1276;1277; RV32XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:1278; RV32XTHEADBB: # %bb.0:1279; RV32XTHEADBB-NEXT: andi a3, a2, 1271280; RV32XTHEADBB-NEXT: addi a4, a3, -321281; RV32XTHEADBB-NEXT: bltz a4, .LBB14_21282; RV32XTHEADBB-NEXT: # %bb.1:1283; RV32XTHEADBB-NEXT: srl a3, a1, a31284; RV32XTHEADBB-NEXT: j .LBB14_31285; RV32XTHEADBB-NEXT: .LBB14_2:1286; RV32XTHEADBB-NEXT: srl a5, a0, a21287; RV32XTHEADBB-NEXT: slli a6, a1, 11288; RV32XTHEADBB-NEXT: not a3, a31289; RV32XTHEADBB-NEXT: sll a3, a6, a31290; RV32XTHEADBB-NEXT: or a3, a5, a31291; RV32XTHEADBB-NEXT: .LBB14_3:1292; RV32XTHEADBB-NEXT: srl a7, a1, a21293; RV32XTHEADBB-NEXT: srai t0, a4, 311294; RV32XTHEADBB-NEXT: neg a4, a21295; RV32XTHEADBB-NEXT: andi a6, a4, 631296; RV32XTHEADBB-NEXT: addi a5, a6, -321297; RV32XTHEADBB-NEXT: and a2, t0, a71298; RV32XTHEADBB-NEXT: bltz a5, .LBB14_51299; RV32XTHEADBB-NEXT: # %bb.4:1300; RV32XTHEADBB-NEXT: sll a1, a0, a61301; RV32XTHEADBB-NEXT: j .LBB14_61302; RV32XTHEADBB-NEXT: .LBB14_5:1303; RV32XTHEADBB-NEXT: sll a1, a1, a41304; RV32XTHEADBB-NEXT: not a6, a61305; RV32XTHEADBB-NEXT: srli a7, a0, 11306; RV32XTHEADBB-NEXT: srl a6, a7, a61307; RV32XTHEADBB-NEXT: or a1, a1, a61308; RV32XTHEADBB-NEXT: .LBB14_6:1309; RV32XTHEADBB-NEXT: sll a0, a0, a41310; RV32XTHEADBB-NEXT: srai a5, a5, 311311; RV32XTHEADBB-NEXT: and a0, a5, a01312; RV32XTHEADBB-NEXT: or a0, a3, a01313; RV32XTHEADBB-NEXT: or a1, a2, a11314; RV32XTHEADBB-NEXT: ret1315;1316; RV64XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:1317; RV64XTHEADBB: # %bb.0:1318; RV64XTHEADBB-NEXT: srl a2, a0, a11319; RV64XTHEADBB-NEXT: neg a1, a11320; RV64XTHEADBB-NEXT: sll a0, a0, a11321; RV64XTHEADBB-NEXT: or a0, a2, a01322; RV64XTHEADBB-NEXT: ret1323 %a = and i64 %y, 1271324 %b = lshr i64 %x, %a1325 %c = sub i64 0, %y1326 %d = and i64 %c, 631327 %e = shl i64 %x, %d1328 %f = or i64 %b, %e1329 ret i64 %f1330}1331 1332define i64 @rotr_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {1333; RV32I-LABEL: rotr_64_mask_or_128_or_64:1334; RV32I: # %bb.0:1335; RV32I-NEXT: li a0, 01336; RV32I-NEXT: li a1, 01337; RV32I-NEXT: ret1338;1339; RV64I-LABEL: rotr_64_mask_or_128_or_64:1340; RV64I: # %bb.0:1341; RV64I-NEXT: li a0, 01342; RV64I-NEXT: ret1343;1344; RV32ZBB-LABEL: rotr_64_mask_or_128_or_64:1345; RV32ZBB: # %bb.0:1346; RV32ZBB-NEXT: li a0, 01347; RV32ZBB-NEXT: li a1, 01348; RV32ZBB-NEXT: ret1349;1350; RV64ZBB-LABEL: rotr_64_mask_or_128_or_64:1351; RV64ZBB: # %bb.0:1352; RV64ZBB-NEXT: ror a0, a0, a11353; RV64ZBB-NEXT: ret1354;1355; RV32XTHEADBB-LABEL: rotr_64_mask_or_128_or_64:1356; RV32XTHEADBB: # %bb.0:1357; RV32XTHEADBB-NEXT: li a0, 01358; RV32XTHEADBB-NEXT: li a1, 01359; RV32XTHEADBB-NEXT: ret1360;1361; RV64XTHEADBB-LABEL: rotr_64_mask_or_128_or_64:1362; RV64XTHEADBB: # %bb.0:1363; RV64XTHEADBB-NEXT: srl a2, a0, a11364; RV64XTHEADBB-NEXT: neg a1, a11365; RV64XTHEADBB-NEXT: sll a0, a0, a11366; RV64XTHEADBB-NEXT: or a0, a2, a01367; RV64XTHEADBB-NEXT: ret1368 %a = or i64 %y, 1281369 %b = lshr i64 %x, %a1370 %c = sub i64 0, %y1371 %d = or i64 %c, 641372 %e = shl i64 %x, %d1373 %f = or i64 %b, %e1374 ret i64 %f1375}1376 1377; Test that we're able to remove a mask on the rotate amount that has more than1378; one use.1379define signext i32 @rotl_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {1380; RV32I-LABEL: rotl_32_mask_shared:1381; RV32I: # %bb.0:1382; RV32I-NEXT: sll a3, a0, a21383; RV32I-NEXT: neg a4, a21384; RV32I-NEXT: srl a0, a0, a41385; RV32I-NEXT: or a0, a3, a01386; RV32I-NEXT: sll a1, a1, a21387; RV32I-NEXT: add a0, a0, a11388; RV32I-NEXT: ret1389;1390; RV64I-LABEL: rotl_32_mask_shared:1391; RV64I: # %bb.0:1392; RV64I-NEXT: sllw a3, a0, a21393; RV64I-NEXT: neg a4, a21394; RV64I-NEXT: srlw a0, a0, a41395; RV64I-NEXT: or a0, a3, a01396; RV64I-NEXT: sllw a1, a1, a21397; RV64I-NEXT: addw a0, a0, a11398; RV64I-NEXT: ret1399;1400; RV32ZBB-LABEL: rotl_32_mask_shared:1401; RV32ZBB: # %bb.0:1402; RV32ZBB-NEXT: rol a0, a0, a21403; RV32ZBB-NEXT: sll a1, a1, a21404; RV32ZBB-NEXT: add a0, a0, a11405; RV32ZBB-NEXT: ret1406;1407; RV64ZBB-LABEL: rotl_32_mask_shared:1408; RV64ZBB: # %bb.0:1409; RV64ZBB-NEXT: rolw a0, a0, a21410; RV64ZBB-NEXT: sllw a1, a1, a21411; RV64ZBB-NEXT: addw a0, a0, a11412; RV64ZBB-NEXT: ret1413;1414; RV32XTHEADBB-LABEL: rotl_32_mask_shared:1415; RV32XTHEADBB: # %bb.0:1416; RV32XTHEADBB-NEXT: sll a3, a0, a21417; RV32XTHEADBB-NEXT: neg a4, a21418; RV32XTHEADBB-NEXT: srl a0, a0, a41419; RV32XTHEADBB-NEXT: or a0, a3, a01420; RV32XTHEADBB-NEXT: sll a1, a1, a21421; RV32XTHEADBB-NEXT: add a0, a0, a11422; RV32XTHEADBB-NEXT: ret1423;1424; RV64XTHEADBB-LABEL: rotl_32_mask_shared:1425; RV64XTHEADBB: # %bb.0:1426; RV64XTHEADBB-NEXT: sllw a3, a0, a21427; RV64XTHEADBB-NEXT: neg a4, a21428; RV64XTHEADBB-NEXT: srlw a0, a0, a41429; RV64XTHEADBB-NEXT: or a0, a3, a01430; RV64XTHEADBB-NEXT: sllw a1, a1, a21431; RV64XTHEADBB-NEXT: addw a0, a0, a11432; RV64XTHEADBB-NEXT: ret1433 %maskedamt = and i32 %amt, 311434 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %maskedamt)1435 %2 = shl i32 %b, %maskedamt1436 %3 = add i32 %1, %21437 ret i32 %31438}1439 1440define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 signext %amt) nounwind {1441; RV32I-LABEL: rotl_64_mask_shared:1442; RV32I: # %bb.0:1443; RV32I-NEXT: slli a5, a4, 261444; RV32I-NEXT: srli t0, a5, 311445; RV32I-NEXT: mv a6, a01446; RV32I-NEXT: bnez t0, .LBB17_21447; RV32I-NEXT: # %bb.1:1448; RV32I-NEXT: mv a6, a11449; RV32I-NEXT: .LBB17_2:1450; RV32I-NEXT: andi a5, a4, 631451; RV32I-NEXT: sll a7, a6, a41452; RV32I-NEXT: bnez t0, .LBB17_41453; RV32I-NEXT: # %bb.3:1454; RV32I-NEXT: mv a1, a01455; RV32I-NEXT: .LBB17_4:1456; RV32I-NEXT: srli a0, a1, 11457; RV32I-NEXT: not t0, a41458; RV32I-NEXT: sll t1, a1, a41459; RV32I-NEXT: srli a1, a6, 11460; RV32I-NEXT: srl a6, a0, t01461; RV32I-NEXT: srl t0, a1, t01462; RV32I-NEXT: addi a0, a5, -321463; RV32I-NEXT: or a1, a7, a61464; RV32I-NEXT: or a6, t1, t01465; RV32I-NEXT: bltz a0, .LBB17_61466; RV32I-NEXT: # %bb.5:1467; RV32I-NEXT: sll a3, a2, a51468; RV32I-NEXT: j .LBB17_71469; RV32I-NEXT: .LBB17_6:1470; RV32I-NEXT: sll a3, a3, a41471; RV32I-NEXT: srli a7, a2, 11472; RV32I-NEXT: not a5, a51473; RV32I-NEXT: srl a5, a7, a51474; RV32I-NEXT: or a3, a3, a51475; RV32I-NEXT: .LBB17_7:1476; RV32I-NEXT: sll a2, a2, a41477; RV32I-NEXT: srai a0, a0, 311478; RV32I-NEXT: and a0, a0, a21479; RV32I-NEXT: add a0, a6, a01480; RV32I-NEXT: sltu a2, a0, a61481; RV32I-NEXT: add a1, a1, a31482; RV32I-NEXT: add a1, a1, a21483; RV32I-NEXT: ret1484;1485; RV64I-LABEL: rotl_64_mask_shared:1486; RV64I: # %bb.0:1487; RV64I-NEXT: sll a3, a0, a21488; RV64I-NEXT: neg a4, a21489; RV64I-NEXT: srl a0, a0, a41490; RV64I-NEXT: or a0, a3, a01491; RV64I-NEXT: sll a1, a1, a21492; RV64I-NEXT: add a0, a0, a11493; RV64I-NEXT: ret1494;1495; RV32ZBB-LABEL: rotl_64_mask_shared:1496; RV32ZBB: # %bb.0:1497; RV32ZBB-NEXT: slli a5, a4, 261498; RV32ZBB-NEXT: srli t0, a5, 311499; RV32ZBB-NEXT: mv a6, a01500; RV32ZBB-NEXT: bnez t0, .LBB17_21501; RV32ZBB-NEXT: # %bb.1:1502; RV32ZBB-NEXT: mv a6, a11503; RV32ZBB-NEXT: .LBB17_2:1504; RV32ZBB-NEXT: andi a5, a4, 631505; RV32ZBB-NEXT: sll a7, a6, a41506; RV32ZBB-NEXT: bnez t0, .LBB17_41507; RV32ZBB-NEXT: # %bb.3:1508; RV32ZBB-NEXT: mv a1, a01509; RV32ZBB-NEXT: .LBB17_4:1510; RV32ZBB-NEXT: srli a0, a1, 11511; RV32ZBB-NEXT: not t0, a41512; RV32ZBB-NEXT: sll t1, a1, a41513; RV32ZBB-NEXT: srli a1, a6, 11514; RV32ZBB-NEXT: srl a6, a0, t01515; RV32ZBB-NEXT: srl t0, a1, t01516; RV32ZBB-NEXT: addi a0, a5, -321517; RV32ZBB-NEXT: or a1, a7, a61518; RV32ZBB-NEXT: or a6, t1, t01519; RV32ZBB-NEXT: bltz a0, .LBB17_61520; RV32ZBB-NEXT: # %bb.5:1521; RV32ZBB-NEXT: sll a3, a2, a51522; RV32ZBB-NEXT: j .LBB17_71523; RV32ZBB-NEXT: .LBB17_6:1524; RV32ZBB-NEXT: sll a3, a3, a41525; RV32ZBB-NEXT: srli a7, a2, 11526; RV32ZBB-NEXT: not a5, a51527; RV32ZBB-NEXT: srl a5, a7, a51528; RV32ZBB-NEXT: or a3, a3, a51529; RV32ZBB-NEXT: .LBB17_7:1530; RV32ZBB-NEXT: sll a2, a2, a41531; RV32ZBB-NEXT: srai a0, a0, 311532; RV32ZBB-NEXT: and a0, a0, a21533; RV32ZBB-NEXT: add a0, a6, a01534; RV32ZBB-NEXT: sltu a2, a0, a61535; RV32ZBB-NEXT: add a1, a1, a31536; RV32ZBB-NEXT: add a1, a1, a21537; RV32ZBB-NEXT: ret1538;1539; RV64ZBB-LABEL: rotl_64_mask_shared:1540; RV64ZBB: # %bb.0:1541; RV64ZBB-NEXT: rol a0, a0, a21542; RV64ZBB-NEXT: sll a1, a1, a21543; RV64ZBB-NEXT: add a0, a0, a11544; RV64ZBB-NEXT: ret1545;1546; RV32XTHEADBB-LABEL: rotl_64_mask_shared:1547; RV32XTHEADBB: # %bb.0:1548; RV32XTHEADBB-NEXT: th.extu t0, a4, 5, 51549; RV32XTHEADBB-NEXT: mv a6, a01550; RV32XTHEADBB-NEXT: bnez t0, .LBB17_21551; RV32XTHEADBB-NEXT: # %bb.1:1552; RV32XTHEADBB-NEXT: mv a6, a11553; RV32XTHEADBB-NEXT: .LBB17_2:1554; RV32XTHEADBB-NEXT: andi a5, a4, 631555; RV32XTHEADBB-NEXT: sll a7, a6, a41556; RV32XTHEADBB-NEXT: bnez t0, .LBB17_41557; RV32XTHEADBB-NEXT: # %bb.3:1558; RV32XTHEADBB-NEXT: mv a1, a01559; RV32XTHEADBB-NEXT: .LBB17_4:1560; RV32XTHEADBB-NEXT: srli a0, a1, 11561; RV32XTHEADBB-NEXT: not t0, a41562; RV32XTHEADBB-NEXT: sll t1, a1, a41563; RV32XTHEADBB-NEXT: srli a1, a6, 11564; RV32XTHEADBB-NEXT: srl a6, a0, t01565; RV32XTHEADBB-NEXT: srl t0, a1, t01566; RV32XTHEADBB-NEXT: addi a0, a5, -321567; RV32XTHEADBB-NEXT: or a1, a7, a61568; RV32XTHEADBB-NEXT: or a6, t1, t01569; RV32XTHEADBB-NEXT: bltz a0, .LBB17_61570; RV32XTHEADBB-NEXT: # %bb.5:1571; RV32XTHEADBB-NEXT: sll a3, a2, a51572; RV32XTHEADBB-NEXT: j .LBB17_71573; RV32XTHEADBB-NEXT: .LBB17_6:1574; RV32XTHEADBB-NEXT: sll a3, a3, a41575; RV32XTHEADBB-NEXT: srli a7, a2, 11576; RV32XTHEADBB-NEXT: not a5, a51577; RV32XTHEADBB-NEXT: srl a5, a7, a51578; RV32XTHEADBB-NEXT: or a3, a3, a51579; RV32XTHEADBB-NEXT: .LBB17_7:1580; RV32XTHEADBB-NEXT: sll a2, a2, a41581; RV32XTHEADBB-NEXT: srai a0, a0, 311582; RV32XTHEADBB-NEXT: and a0, a0, a21583; RV32XTHEADBB-NEXT: add a0, a6, a01584; RV32XTHEADBB-NEXT: sltu a2, a0, a61585; RV32XTHEADBB-NEXT: add a1, a1, a31586; RV32XTHEADBB-NEXT: add a1, a1, a21587; RV32XTHEADBB-NEXT: ret1588;1589; RV64XTHEADBB-LABEL: rotl_64_mask_shared:1590; RV64XTHEADBB: # %bb.0:1591; RV64XTHEADBB-NEXT: sll a3, a0, a21592; RV64XTHEADBB-NEXT: neg a4, a21593; RV64XTHEADBB-NEXT: srl a0, a0, a41594; RV64XTHEADBB-NEXT: or a0, a3, a01595; RV64XTHEADBB-NEXT: sll a1, a1, a21596; RV64XTHEADBB-NEXT: add a0, a0, a11597; RV64XTHEADBB-NEXT: ret1598 %maskedamt = and i64 %amt, 631599 %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %maskedamt)1600 %2 = shl i64 %b, %maskedamt1601 %3 = add i64 %1, %21602 ret i64 %31603}1604 1605define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {1606; RV32I-LABEL: rotr_32_mask_shared:1607; RV32I: # %bb.0:1608; RV32I-NEXT: srl a3, a0, a21609; RV32I-NEXT: neg a4, a21610; RV32I-NEXT: sll a0, a0, a41611; RV32I-NEXT: or a0, a3, a01612; RV32I-NEXT: sll a1, a1, a21613; RV32I-NEXT: add a0, a0, a11614; RV32I-NEXT: ret1615;1616; RV64I-LABEL: rotr_32_mask_shared:1617; RV64I: # %bb.0:1618; RV64I-NEXT: srlw a3, a0, a21619; RV64I-NEXT: neg a4, a21620; RV64I-NEXT: sllw a0, a0, a41621; RV64I-NEXT: or a0, a3, a01622; RV64I-NEXT: sllw a1, a1, a21623; RV64I-NEXT: addw a0, a0, a11624; RV64I-NEXT: ret1625;1626; RV32ZBB-LABEL: rotr_32_mask_shared:1627; RV32ZBB: # %bb.0:1628; RV32ZBB-NEXT: ror a0, a0, a21629; RV32ZBB-NEXT: sll a1, a1, a21630; RV32ZBB-NEXT: add a0, a0, a11631; RV32ZBB-NEXT: ret1632;1633; RV64ZBB-LABEL: rotr_32_mask_shared:1634; RV64ZBB: # %bb.0:1635; RV64ZBB-NEXT: rorw a0, a0, a21636; RV64ZBB-NEXT: sllw a1, a1, a21637; RV64ZBB-NEXT: addw a0, a0, a11638; RV64ZBB-NEXT: ret1639;1640; RV32XTHEADBB-LABEL: rotr_32_mask_shared:1641; RV32XTHEADBB: # %bb.0:1642; RV32XTHEADBB-NEXT: srl a3, a0, a21643; RV32XTHEADBB-NEXT: neg a4, a21644; RV32XTHEADBB-NEXT: sll a0, a0, a41645; RV32XTHEADBB-NEXT: or a0, a3, a01646; RV32XTHEADBB-NEXT: sll a1, a1, a21647; RV32XTHEADBB-NEXT: add a0, a0, a11648; RV32XTHEADBB-NEXT: ret1649;1650; RV64XTHEADBB-LABEL: rotr_32_mask_shared:1651; RV64XTHEADBB: # %bb.0:1652; RV64XTHEADBB-NEXT: srlw a3, a0, a21653; RV64XTHEADBB-NEXT: neg a4, a21654; RV64XTHEADBB-NEXT: sllw a0, a0, a41655; RV64XTHEADBB-NEXT: or a0, a3, a01656; RV64XTHEADBB-NEXT: sllw a1, a1, a21657; RV64XTHEADBB-NEXT: addw a0, a0, a11658; RV64XTHEADBB-NEXT: ret1659 %maskedamt = and i32 %amt, 311660 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %maskedamt)1661 %2 = shl i32 %b, %maskedamt1662 %3 = add i32 %1, %21663 ret i32 %31664}1665 1666define signext i64 @rotr_64_mask_shared(i64 signext %a, i64 signext %b, i64 signext %amt) nounwind {1667; RV32I-LABEL: rotr_64_mask_shared:1668; RV32I: # %bb.0:1669; RV32I-NEXT: andi t0, a4, 321670; RV32I-NEXT: mv a6, a11671; RV32I-NEXT: beqz t0, .LBB19_21672; RV32I-NEXT: # %bb.1:1673; RV32I-NEXT: mv a6, a01674; RV32I-NEXT: .LBB19_2:1675; RV32I-NEXT: andi a5, a4, 631676; RV32I-NEXT: srl a7, a6, a41677; RV32I-NEXT: beqz t0, .LBB19_41678; RV32I-NEXT: # %bb.3:1679; RV32I-NEXT: mv a0, a11680; RV32I-NEXT: .LBB19_4:1681; RV32I-NEXT: slli a1, a0, 11682; RV32I-NEXT: not t0, a41683; RV32I-NEXT: srl t1, a0, a41684; RV32I-NEXT: slli a6, a6, 11685; RV32I-NEXT: sll a1, a1, t01686; RV32I-NEXT: sll a6, a6, t01687; RV32I-NEXT: addi a0, a5, -321688; RV32I-NEXT: or a1, a1, a71689; RV32I-NEXT: or a6, a6, t11690; RV32I-NEXT: bltz a0, .LBB19_61691; RV32I-NEXT: # %bb.5:1692; RV32I-NEXT: sll a3, a2, a51693; RV32I-NEXT: j .LBB19_71694; RV32I-NEXT: .LBB19_6:1695; RV32I-NEXT: sll a3, a3, a41696; RV32I-NEXT: srli a7, a2, 11697; RV32I-NEXT: not a5, a51698; RV32I-NEXT: srl a5, a7, a51699; RV32I-NEXT: or a3, a3, a51700; RV32I-NEXT: .LBB19_7:1701; RV32I-NEXT: sll a2, a2, a41702; RV32I-NEXT: srai a0, a0, 311703; RV32I-NEXT: and a0, a0, a21704; RV32I-NEXT: add a0, a6, a01705; RV32I-NEXT: sltu a2, a0, a61706; RV32I-NEXT: add a1, a1, a31707; RV32I-NEXT: add a1, a1, a21708; RV32I-NEXT: ret1709;1710; RV64I-LABEL: rotr_64_mask_shared:1711; RV64I: # %bb.0:1712; RV64I-NEXT: srl a3, a0, a21713; RV64I-NEXT: neg a4, a21714; RV64I-NEXT: sll a0, a0, a41715; RV64I-NEXT: or a0, a3, a01716; RV64I-NEXT: sll a1, a1, a21717; RV64I-NEXT: add a0, a0, a11718; RV64I-NEXT: ret1719;1720; RV32ZBB-LABEL: rotr_64_mask_shared:1721; RV32ZBB: # %bb.0:1722; RV32ZBB-NEXT: andi t0, a4, 321723; RV32ZBB-NEXT: mv a6, a11724; RV32ZBB-NEXT: beqz t0, .LBB19_21725; RV32ZBB-NEXT: # %bb.1:1726; RV32ZBB-NEXT: mv a6, a01727; RV32ZBB-NEXT: .LBB19_2:1728; RV32ZBB-NEXT: andi a5, a4, 631729; RV32ZBB-NEXT: srl a7, a6, a41730; RV32ZBB-NEXT: beqz t0, .LBB19_41731; RV32ZBB-NEXT: # %bb.3:1732; RV32ZBB-NEXT: mv a0, a11733; RV32ZBB-NEXT: .LBB19_4:1734; RV32ZBB-NEXT: slli a1, a0, 11735; RV32ZBB-NEXT: not t0, a41736; RV32ZBB-NEXT: srl t1, a0, a41737; RV32ZBB-NEXT: slli a6, a6, 11738; RV32ZBB-NEXT: sll a1, a1, t01739; RV32ZBB-NEXT: sll a6, a6, t01740; RV32ZBB-NEXT: addi a0, a5, -321741; RV32ZBB-NEXT: or a1, a1, a71742; RV32ZBB-NEXT: or a6, a6, t11743; RV32ZBB-NEXT: bltz a0, .LBB19_61744; RV32ZBB-NEXT: # %bb.5:1745; RV32ZBB-NEXT: sll a3, a2, a51746; RV32ZBB-NEXT: j .LBB19_71747; RV32ZBB-NEXT: .LBB19_6:1748; RV32ZBB-NEXT: sll a3, a3, a41749; RV32ZBB-NEXT: srli a7, a2, 11750; RV32ZBB-NEXT: not a5, a51751; RV32ZBB-NEXT: srl a5, a7, a51752; RV32ZBB-NEXT: or a3, a3, a51753; RV32ZBB-NEXT: .LBB19_7:1754; RV32ZBB-NEXT: sll a2, a2, a41755; RV32ZBB-NEXT: srai a0, a0, 311756; RV32ZBB-NEXT: and a0, a0, a21757; RV32ZBB-NEXT: add a0, a6, a01758; RV32ZBB-NEXT: sltu a2, a0, a61759; RV32ZBB-NEXT: add a1, a1, a31760; RV32ZBB-NEXT: add a1, a1, a21761; RV32ZBB-NEXT: ret1762;1763; RV64ZBB-LABEL: rotr_64_mask_shared:1764; RV64ZBB: # %bb.0:1765; RV64ZBB-NEXT: ror a0, a0, a21766; RV64ZBB-NEXT: sll a1, a1, a21767; RV64ZBB-NEXT: add a0, a0, a11768; RV64ZBB-NEXT: ret1769;1770; RV32XTHEADBB-LABEL: rotr_64_mask_shared:1771; RV32XTHEADBB: # %bb.0:1772; RV32XTHEADBB-NEXT: andi t0, a4, 321773; RV32XTHEADBB-NEXT: mv a6, a11774; RV32XTHEADBB-NEXT: beqz t0, .LBB19_21775; RV32XTHEADBB-NEXT: # %bb.1:1776; RV32XTHEADBB-NEXT: mv a6, a01777; RV32XTHEADBB-NEXT: .LBB19_2:1778; RV32XTHEADBB-NEXT: andi a5, a4, 631779; RV32XTHEADBB-NEXT: srl a7, a6, a41780; RV32XTHEADBB-NEXT: beqz t0, .LBB19_41781; RV32XTHEADBB-NEXT: # %bb.3:1782; RV32XTHEADBB-NEXT: mv a0, a11783; RV32XTHEADBB-NEXT: .LBB19_4:1784; RV32XTHEADBB-NEXT: slli a1, a0, 11785; RV32XTHEADBB-NEXT: not t0, a41786; RV32XTHEADBB-NEXT: srl t1, a0, a41787; RV32XTHEADBB-NEXT: slli a6, a6, 11788; RV32XTHEADBB-NEXT: sll a1, a1, t01789; RV32XTHEADBB-NEXT: sll a6, a6, t01790; RV32XTHEADBB-NEXT: addi a0, a5, -321791; RV32XTHEADBB-NEXT: or a1, a1, a71792; RV32XTHEADBB-NEXT: or a6, a6, t11793; RV32XTHEADBB-NEXT: bltz a0, .LBB19_61794; RV32XTHEADBB-NEXT: # %bb.5:1795; RV32XTHEADBB-NEXT: sll a3, a2, a51796; RV32XTHEADBB-NEXT: j .LBB19_71797; RV32XTHEADBB-NEXT: .LBB19_6:1798; RV32XTHEADBB-NEXT: sll a3, a3, a41799; RV32XTHEADBB-NEXT: srli a7, a2, 11800; RV32XTHEADBB-NEXT: not a5, a51801; RV32XTHEADBB-NEXT: srl a5, a7, a51802; RV32XTHEADBB-NEXT: or a3, a3, a51803; RV32XTHEADBB-NEXT: .LBB19_7:1804; RV32XTHEADBB-NEXT: sll a2, a2, a41805; RV32XTHEADBB-NEXT: srai a0, a0, 311806; RV32XTHEADBB-NEXT: and a0, a0, a21807; RV32XTHEADBB-NEXT: add a0, a6, a01808; RV32XTHEADBB-NEXT: sltu a2, a0, a61809; RV32XTHEADBB-NEXT: add a1, a1, a31810; RV32XTHEADBB-NEXT: add a1, a1, a21811; RV32XTHEADBB-NEXT: ret1812;1813; RV64XTHEADBB-LABEL: rotr_64_mask_shared:1814; RV64XTHEADBB: # %bb.0:1815; RV64XTHEADBB-NEXT: srl a3, a0, a21816; RV64XTHEADBB-NEXT: neg a4, a21817; RV64XTHEADBB-NEXT: sll a0, a0, a41818; RV64XTHEADBB-NEXT: or a0, a3, a01819; RV64XTHEADBB-NEXT: sll a1, a1, a21820; RV64XTHEADBB-NEXT: add a0, a0, a11821; RV64XTHEADBB-NEXT: ret1822 %maskedamt = and i64 %amt, 631823 %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %maskedamt)1824 %2 = shl i64 %b, %maskedamt1825 %3 = add i64 %1, %21826 ret i64 %31827}1828 1829define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {1830; RV32I-LABEL: rotl_32_mask_multiple:1831; RV32I: # %bb.0:1832; RV32I-NEXT: sll a3, a0, a21833; RV32I-NEXT: neg a4, a21834; RV32I-NEXT: sll a2, a1, a21835; RV32I-NEXT: srl a0, a0, a41836; RV32I-NEXT: srl a1, a1, a41837; RV32I-NEXT: or a0, a3, a01838; RV32I-NEXT: or a1, a2, a11839; RV32I-NEXT: add a0, a0, a11840; RV32I-NEXT: ret1841;1842; RV64I-LABEL: rotl_32_mask_multiple:1843; RV64I: # %bb.0:1844; RV64I-NEXT: sllw a3, a0, a21845; RV64I-NEXT: neg a4, a21846; RV64I-NEXT: sllw a2, a1, a21847; RV64I-NEXT: srlw a0, a0, a41848; RV64I-NEXT: srlw a1, a1, a41849; RV64I-NEXT: or a0, a3, a01850; RV64I-NEXT: or a1, a2, a11851; RV64I-NEXT: addw a0, a0, a11852; RV64I-NEXT: ret1853;1854; RV32ZBB-LABEL: rotl_32_mask_multiple:1855; RV32ZBB: # %bb.0:1856; RV32ZBB-NEXT: rol a0, a0, a21857; RV32ZBB-NEXT: rol a1, a1, a21858; RV32ZBB-NEXT: add a0, a0, a11859; RV32ZBB-NEXT: ret1860;1861; RV64ZBB-LABEL: rotl_32_mask_multiple:1862; RV64ZBB: # %bb.0:1863; RV64ZBB-NEXT: rolw a0, a0, a21864; RV64ZBB-NEXT: rolw a1, a1, a21865; RV64ZBB-NEXT: addw a0, a0, a11866; RV64ZBB-NEXT: ret1867;1868; RV32XTHEADBB-LABEL: rotl_32_mask_multiple:1869; RV32XTHEADBB: # %bb.0:1870; RV32XTHEADBB-NEXT: sll a3, a0, a21871; RV32XTHEADBB-NEXT: neg a4, a21872; RV32XTHEADBB-NEXT: sll a2, a1, a21873; RV32XTHEADBB-NEXT: srl a0, a0, a41874; RV32XTHEADBB-NEXT: srl a1, a1, a41875; RV32XTHEADBB-NEXT: or a0, a3, a01876; RV32XTHEADBB-NEXT: or a1, a2, a11877; RV32XTHEADBB-NEXT: add a0, a0, a11878; RV32XTHEADBB-NEXT: ret1879;1880; RV64XTHEADBB-LABEL: rotl_32_mask_multiple:1881; RV64XTHEADBB: # %bb.0:1882; RV64XTHEADBB-NEXT: sllw a3, a0, a21883; RV64XTHEADBB-NEXT: neg a4, a21884; RV64XTHEADBB-NEXT: sllw a2, a1, a21885; RV64XTHEADBB-NEXT: srlw a0, a0, a41886; RV64XTHEADBB-NEXT: srlw a1, a1, a41887; RV64XTHEADBB-NEXT: or a0, a3, a01888; RV64XTHEADBB-NEXT: or a1, a2, a11889; RV64XTHEADBB-NEXT: addw a0, a0, a11890; RV64XTHEADBB-NEXT: ret1891 %maskedamt = and i32 %amt, 311892 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %maskedamt)1893 %2 = tail call i32 @llvm.fshl.i32(i32 %b, i32 %b, i32 %maskedamt)1894 %3 = add i32 %1, %21895 ret i32 %31896}1897 1898define i64 @rotl_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {1899; RV32I-LABEL: rotl_64_mask_multiple:1900; RV32I: # %bb.0:1901; RV32I-NEXT: slli a5, a4, 261902; RV32I-NEXT: srli a5, a5, 311903; RV32I-NEXT: mv a6, a11904; RV32I-NEXT: bnez a5, .LBB21_21905; RV32I-NEXT: # %bb.1:1906; RV32I-NEXT: mv a6, a01907; RV32I-NEXT: .LBB21_2:1908; RV32I-NEXT: bnez a5, .LBB21_41909; RV32I-NEXT: # %bb.3:1910; RV32I-NEXT: mv a0, a11911; RV32I-NEXT: .LBB21_4:1912; RV32I-NEXT: sll a7, a6, a41913; RV32I-NEXT: srli t1, a0, 11914; RV32I-NEXT: not a1, a41915; RV32I-NEXT: sll t0, a0, a41916; RV32I-NEXT: srli a0, a6, 11917; RV32I-NEXT: srl a6, t1, a11918; RV32I-NEXT: srl t1, a0, a11919; RV32I-NEXT: mv a0, a31920; RV32I-NEXT: bnez a5, .LBB21_61921; RV32I-NEXT: # %bb.5:1922; RV32I-NEXT: mv a0, a21923; RV32I-NEXT: .LBB21_6:1924; RV32I-NEXT: or a6, a7, a61925; RV32I-NEXT: or a7, t0, t11926; RV32I-NEXT: sll t0, a0, a41927; RV32I-NEXT: bnez a5, .LBB21_81928; RV32I-NEXT: # %bb.7:1929; RV32I-NEXT: mv a2, a31930; RV32I-NEXT: .LBB21_8:1931; RV32I-NEXT: srli a3, a2, 11932; RV32I-NEXT: sll a2, a2, a41933; RV32I-NEXT: srli a0, a0, 11934; RV32I-NEXT: srl a3, a3, a11935; RV32I-NEXT: srl a0, a0, a11936; RV32I-NEXT: or a1, t0, a31937; RV32I-NEXT: or a0, a2, a01938; RV32I-NEXT: add a7, a7, a01939; RV32I-NEXT: add a0, a6, a11940; RV32I-NEXT: sltu a1, a0, a61941; RV32I-NEXT: add a1, a7, a11942; RV32I-NEXT: ret1943;1944; RV64I-LABEL: rotl_64_mask_multiple:1945; RV64I: # %bb.0:1946; RV64I-NEXT: sll a3, a0, a21947; RV64I-NEXT: neg a4, a21948; RV64I-NEXT: sll a2, a1, a21949; RV64I-NEXT: srl a0, a0, a41950; RV64I-NEXT: srl a1, a1, a41951; RV64I-NEXT: or a0, a3, a01952; RV64I-NEXT: or a1, a2, a11953; RV64I-NEXT: add a0, a0, a11954; RV64I-NEXT: ret1955;1956; RV32ZBB-LABEL: rotl_64_mask_multiple:1957; RV32ZBB: # %bb.0:1958; RV32ZBB-NEXT: slli a5, a4, 261959; RV32ZBB-NEXT: srli a5, a5, 311960; RV32ZBB-NEXT: mv a6, a11961; RV32ZBB-NEXT: bnez a5, .LBB21_21962; RV32ZBB-NEXT: # %bb.1:1963; RV32ZBB-NEXT: mv a6, a01964; RV32ZBB-NEXT: .LBB21_2:1965; RV32ZBB-NEXT: bnez a5, .LBB21_41966; RV32ZBB-NEXT: # %bb.3:1967; RV32ZBB-NEXT: mv a0, a11968; RV32ZBB-NEXT: .LBB21_4:1969; RV32ZBB-NEXT: sll a7, a6, a41970; RV32ZBB-NEXT: srli t1, a0, 11971; RV32ZBB-NEXT: not a1, a41972; RV32ZBB-NEXT: sll t0, a0, a41973; RV32ZBB-NEXT: srli a0, a6, 11974; RV32ZBB-NEXT: srl a6, t1, a11975; RV32ZBB-NEXT: srl t1, a0, a11976; RV32ZBB-NEXT: mv a0, a31977; RV32ZBB-NEXT: bnez a5, .LBB21_61978; RV32ZBB-NEXT: # %bb.5:1979; RV32ZBB-NEXT: mv a0, a21980; RV32ZBB-NEXT: .LBB21_6:1981; RV32ZBB-NEXT: or a6, a7, a61982; RV32ZBB-NEXT: or a7, t0, t11983; RV32ZBB-NEXT: sll t0, a0, a41984; RV32ZBB-NEXT: bnez a5, .LBB21_81985; RV32ZBB-NEXT: # %bb.7:1986; RV32ZBB-NEXT: mv a2, a31987; RV32ZBB-NEXT: .LBB21_8:1988; RV32ZBB-NEXT: srli a3, a2, 11989; RV32ZBB-NEXT: sll a2, a2, a41990; RV32ZBB-NEXT: srli a0, a0, 11991; RV32ZBB-NEXT: srl a3, a3, a11992; RV32ZBB-NEXT: srl a0, a0, a11993; RV32ZBB-NEXT: or a1, t0, a31994; RV32ZBB-NEXT: or a0, a2, a01995; RV32ZBB-NEXT: add a7, a7, a01996; RV32ZBB-NEXT: add a0, a6, a11997; RV32ZBB-NEXT: sltu a1, a0, a61998; RV32ZBB-NEXT: add a1, a7, a11999; RV32ZBB-NEXT: ret2000;2001; RV64ZBB-LABEL: rotl_64_mask_multiple:2002; RV64ZBB: # %bb.0:2003; RV64ZBB-NEXT: rol a0, a0, a22004; RV64ZBB-NEXT: rol a1, a1, a22005; RV64ZBB-NEXT: add a0, a0, a12006; RV64ZBB-NEXT: ret2007;2008; RV32XTHEADBB-LABEL: rotl_64_mask_multiple:2009; RV32XTHEADBB: # %bb.0:2010; RV32XTHEADBB-NEXT: th.extu a5, a4, 5, 52011; RV32XTHEADBB-NEXT: mv a6, a12012; RV32XTHEADBB-NEXT: bnez a5, .LBB21_22013; RV32XTHEADBB-NEXT: # %bb.1:2014; RV32XTHEADBB-NEXT: mv a6, a02015; RV32XTHEADBB-NEXT: .LBB21_2:2016; RV32XTHEADBB-NEXT: bnez a5, .LBB21_42017; RV32XTHEADBB-NEXT: # %bb.3:2018; RV32XTHEADBB-NEXT: mv a0, a12019; RV32XTHEADBB-NEXT: .LBB21_4:2020; RV32XTHEADBB-NEXT: sll a7, a6, a42021; RV32XTHEADBB-NEXT: srli t1, a0, 12022; RV32XTHEADBB-NEXT: not a1, a42023; RV32XTHEADBB-NEXT: sll t0, a0, a42024; RV32XTHEADBB-NEXT: srli a0, a6, 12025; RV32XTHEADBB-NEXT: srl a6, t1, a12026; RV32XTHEADBB-NEXT: srl t1, a0, a12027; RV32XTHEADBB-NEXT: mv a0, a32028; RV32XTHEADBB-NEXT: bnez a5, .LBB21_62029; RV32XTHEADBB-NEXT: # %bb.5:2030; RV32XTHEADBB-NEXT: mv a0, a22031; RV32XTHEADBB-NEXT: .LBB21_6:2032; RV32XTHEADBB-NEXT: or a6, a7, a62033; RV32XTHEADBB-NEXT: or a7, t0, t12034; RV32XTHEADBB-NEXT: sll t0, a0, a42035; RV32XTHEADBB-NEXT: bnez a5, .LBB21_82036; RV32XTHEADBB-NEXT: # %bb.7:2037; RV32XTHEADBB-NEXT: mv a2, a32038; RV32XTHEADBB-NEXT: .LBB21_8:2039; RV32XTHEADBB-NEXT: srli a3, a2, 12040; RV32XTHEADBB-NEXT: sll a2, a2, a42041; RV32XTHEADBB-NEXT: srli a0, a0, 12042; RV32XTHEADBB-NEXT: srl a3, a3, a12043; RV32XTHEADBB-NEXT: srl a0, a0, a12044; RV32XTHEADBB-NEXT: or a1, t0, a32045; RV32XTHEADBB-NEXT: or a0, a2, a02046; RV32XTHEADBB-NEXT: add a7, a7, a02047; RV32XTHEADBB-NEXT: add a0, a6, a12048; RV32XTHEADBB-NEXT: sltu a1, a0, a62049; RV32XTHEADBB-NEXT: add a1, a7, a12050; RV32XTHEADBB-NEXT: ret2051;2052; RV64XTHEADBB-LABEL: rotl_64_mask_multiple:2053; RV64XTHEADBB: # %bb.0:2054; RV64XTHEADBB-NEXT: sll a3, a0, a22055; RV64XTHEADBB-NEXT: neg a4, a22056; RV64XTHEADBB-NEXT: sll a2, a1, a22057; RV64XTHEADBB-NEXT: srl a0, a0, a42058; RV64XTHEADBB-NEXT: srl a1, a1, a42059; RV64XTHEADBB-NEXT: or a0, a3, a02060; RV64XTHEADBB-NEXT: or a1, a2, a12061; RV64XTHEADBB-NEXT: add a0, a0, a12062; RV64XTHEADBB-NEXT: ret2063 %maskedamt = and i64 %amt, 632064 %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %maskedamt)2065 %2 = tail call i64 @llvm.fshl.i64(i64 %b, i64 %b, i64 %maskedamt)2066 %3 = add i64 %1, %22067 ret i64 %32068}2069 2070define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {2071; RV32I-LABEL: rotr_32_mask_multiple:2072; RV32I: # %bb.0:2073; RV32I-NEXT: srl a3, a0, a22074; RV32I-NEXT: neg a4, a22075; RV32I-NEXT: srl a2, a1, a22076; RV32I-NEXT: sll a0, a0, a42077; RV32I-NEXT: sll a1, a1, a42078; RV32I-NEXT: or a0, a3, a02079; RV32I-NEXT: or a1, a2, a12080; RV32I-NEXT: add a0, a0, a12081; RV32I-NEXT: ret2082;2083; RV64I-LABEL: rotr_32_mask_multiple:2084; RV64I: # %bb.0:2085; RV64I-NEXT: srlw a3, a0, a22086; RV64I-NEXT: neg a4, a22087; RV64I-NEXT: srlw a2, a1, a22088; RV64I-NEXT: sllw a0, a0, a42089; RV64I-NEXT: sllw a1, a1, a42090; RV64I-NEXT: or a0, a3, a02091; RV64I-NEXT: or a1, a2, a12092; RV64I-NEXT: addw a0, a0, a12093; RV64I-NEXT: ret2094;2095; RV32ZBB-LABEL: rotr_32_mask_multiple:2096; RV32ZBB: # %bb.0:2097; RV32ZBB-NEXT: ror a0, a0, a22098; RV32ZBB-NEXT: ror a1, a1, a22099; RV32ZBB-NEXT: add a0, a0, a12100; RV32ZBB-NEXT: ret2101;2102; RV64ZBB-LABEL: rotr_32_mask_multiple:2103; RV64ZBB: # %bb.0:2104; RV64ZBB-NEXT: rorw a0, a0, a22105; RV64ZBB-NEXT: rorw a1, a1, a22106; RV64ZBB-NEXT: addw a0, a0, a12107; RV64ZBB-NEXT: ret2108;2109; RV32XTHEADBB-LABEL: rotr_32_mask_multiple:2110; RV32XTHEADBB: # %bb.0:2111; RV32XTHEADBB-NEXT: srl a3, a0, a22112; RV32XTHEADBB-NEXT: neg a4, a22113; RV32XTHEADBB-NEXT: srl a2, a1, a22114; RV32XTHEADBB-NEXT: sll a0, a0, a42115; RV32XTHEADBB-NEXT: sll a1, a1, a42116; RV32XTHEADBB-NEXT: or a0, a3, a02117; RV32XTHEADBB-NEXT: or a1, a2, a12118; RV32XTHEADBB-NEXT: add a0, a0, a12119; RV32XTHEADBB-NEXT: ret2120;2121; RV64XTHEADBB-LABEL: rotr_32_mask_multiple:2122; RV64XTHEADBB: # %bb.0:2123; RV64XTHEADBB-NEXT: srlw a3, a0, a22124; RV64XTHEADBB-NEXT: neg a4, a22125; RV64XTHEADBB-NEXT: srlw a2, a1, a22126; RV64XTHEADBB-NEXT: sllw a0, a0, a42127; RV64XTHEADBB-NEXT: sllw a1, a1, a42128; RV64XTHEADBB-NEXT: or a0, a3, a02129; RV64XTHEADBB-NEXT: or a1, a2, a12130; RV64XTHEADBB-NEXT: addw a0, a0, a12131; RV64XTHEADBB-NEXT: ret2132 %maskedamt = and i32 %amt, 312133 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %maskedamt)2134 %2 = tail call i32 @llvm.fshr.i32(i32 %b, i32 %b, i32 %maskedamt)2135 %3 = add i32 %1, %22136 ret i32 %32137}2138 2139define i64 @rotr_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {2140; RV32I-LABEL: rotr_64_mask_multiple:2141; RV32I: # %bb.0:2142; RV32I-NEXT: andi a5, a4, 322143; RV32I-NEXT: mv a6, a02144; RV32I-NEXT: beqz a5, .LBB23_22145; RV32I-NEXT: # %bb.1:2146; RV32I-NEXT: mv a6, a12147; RV32I-NEXT: .LBB23_2:2148; RV32I-NEXT: beqz a5, .LBB23_42149; RV32I-NEXT: # %bb.3:2150; RV32I-NEXT: mv a1, a02151; RV32I-NEXT: .LBB23_4:2152; RV32I-NEXT: srl a7, a6, a42153; RV32I-NEXT: slli t1, a1, 12154; RV32I-NEXT: not a0, a42155; RV32I-NEXT: srl t0, a1, a42156; RV32I-NEXT: slli a6, a6, 12157; RV32I-NEXT: sll a1, t1, a02158; RV32I-NEXT: sll t1, a6, a02159; RV32I-NEXT: mv a6, a22160; RV32I-NEXT: beqz a5, .LBB23_62161; RV32I-NEXT: # %bb.5:2162; RV32I-NEXT: mv a6, a32163; RV32I-NEXT: .LBB23_6:2164; RV32I-NEXT: or a1, a1, a72165; RV32I-NEXT: or a7, t1, t02166; RV32I-NEXT: srl t0, a6, a42167; RV32I-NEXT: beqz a5, .LBB23_82168; RV32I-NEXT: # %bb.7:2169; RV32I-NEXT: mv a3, a22170; RV32I-NEXT: .LBB23_8:2171; RV32I-NEXT: slli a2, a3, 12172; RV32I-NEXT: srl a3, a3, a42173; RV32I-NEXT: slli a6, a6, 12174; RV32I-NEXT: sll a2, a2, a02175; RV32I-NEXT: sll a0, a6, a02176; RV32I-NEXT: or a2, a2, t02177; RV32I-NEXT: or a0, a0, a32178; RV32I-NEXT: add a7, a7, a02179; RV32I-NEXT: add a0, a1, a22180; RV32I-NEXT: sltu a1, a0, a12181; RV32I-NEXT: add a1, a7, a12182; RV32I-NEXT: ret2183;2184; RV64I-LABEL: rotr_64_mask_multiple:2185; RV64I: # %bb.0:2186; RV64I-NEXT: srl a3, a0, a22187; RV64I-NEXT: neg a4, a22188; RV64I-NEXT: srl a2, a1, a22189; RV64I-NEXT: sll a0, a0, a42190; RV64I-NEXT: sll a1, a1, a42191; RV64I-NEXT: or a0, a3, a02192; RV64I-NEXT: or a1, a2, a12193; RV64I-NEXT: add a0, a0, a12194; RV64I-NEXT: ret2195;2196; RV32ZBB-LABEL: rotr_64_mask_multiple:2197; RV32ZBB: # %bb.0:2198; RV32ZBB-NEXT: andi a5, a4, 322199; RV32ZBB-NEXT: mv a6, a02200; RV32ZBB-NEXT: beqz a5, .LBB23_22201; RV32ZBB-NEXT: # %bb.1:2202; RV32ZBB-NEXT: mv a6, a12203; RV32ZBB-NEXT: .LBB23_2:2204; RV32ZBB-NEXT: beqz a5, .LBB23_42205; RV32ZBB-NEXT: # %bb.3:2206; RV32ZBB-NEXT: mv a1, a02207; RV32ZBB-NEXT: .LBB23_4:2208; RV32ZBB-NEXT: srl a7, a6, a42209; RV32ZBB-NEXT: slli t1, a1, 12210; RV32ZBB-NEXT: not a0, a42211; RV32ZBB-NEXT: srl t0, a1, a42212; RV32ZBB-NEXT: slli a6, a6, 12213; RV32ZBB-NEXT: sll a1, t1, a02214; RV32ZBB-NEXT: sll t1, a6, a02215; RV32ZBB-NEXT: mv a6, a22216; RV32ZBB-NEXT: beqz a5, .LBB23_62217; RV32ZBB-NEXT: # %bb.5:2218; RV32ZBB-NEXT: mv a6, a32219; RV32ZBB-NEXT: .LBB23_6:2220; RV32ZBB-NEXT: or a1, a1, a72221; RV32ZBB-NEXT: or a7, t1, t02222; RV32ZBB-NEXT: srl t0, a6, a42223; RV32ZBB-NEXT: beqz a5, .LBB23_82224; RV32ZBB-NEXT: # %bb.7:2225; RV32ZBB-NEXT: mv a3, a22226; RV32ZBB-NEXT: .LBB23_8:2227; RV32ZBB-NEXT: slli a2, a3, 12228; RV32ZBB-NEXT: srl a3, a3, a42229; RV32ZBB-NEXT: slli a6, a6, 12230; RV32ZBB-NEXT: sll a2, a2, a02231; RV32ZBB-NEXT: sll a0, a6, a02232; RV32ZBB-NEXT: or a2, a2, t02233; RV32ZBB-NEXT: or a0, a0, a32234; RV32ZBB-NEXT: add a7, a7, a02235; RV32ZBB-NEXT: add a0, a1, a22236; RV32ZBB-NEXT: sltu a1, a0, a12237; RV32ZBB-NEXT: add a1, a7, a12238; RV32ZBB-NEXT: ret2239;2240; RV64ZBB-LABEL: rotr_64_mask_multiple:2241; RV64ZBB: # %bb.0:2242; RV64ZBB-NEXT: ror a0, a0, a22243; RV64ZBB-NEXT: ror a1, a1, a22244; RV64ZBB-NEXT: add a0, a0, a12245; RV64ZBB-NEXT: ret2246;2247; RV32XTHEADBB-LABEL: rotr_64_mask_multiple:2248; RV32XTHEADBB: # %bb.0:2249; RV32XTHEADBB-NEXT: andi a5, a4, 322250; RV32XTHEADBB-NEXT: mv a6, a02251; RV32XTHEADBB-NEXT: beqz a5, .LBB23_22252; RV32XTHEADBB-NEXT: # %bb.1:2253; RV32XTHEADBB-NEXT: mv a6, a12254; RV32XTHEADBB-NEXT: .LBB23_2:2255; RV32XTHEADBB-NEXT: beqz a5, .LBB23_42256; RV32XTHEADBB-NEXT: # %bb.3:2257; RV32XTHEADBB-NEXT: mv a1, a02258; RV32XTHEADBB-NEXT: .LBB23_4:2259; RV32XTHEADBB-NEXT: srl a7, a6, a42260; RV32XTHEADBB-NEXT: slli t1, a1, 12261; RV32XTHEADBB-NEXT: not a0, a42262; RV32XTHEADBB-NEXT: srl t0, a1, a42263; RV32XTHEADBB-NEXT: slli a6, a6, 12264; RV32XTHEADBB-NEXT: sll a1, t1, a02265; RV32XTHEADBB-NEXT: sll t1, a6, a02266; RV32XTHEADBB-NEXT: mv a6, a22267; RV32XTHEADBB-NEXT: beqz a5, .LBB23_62268; RV32XTHEADBB-NEXT: # %bb.5:2269; RV32XTHEADBB-NEXT: mv a6, a32270; RV32XTHEADBB-NEXT: .LBB23_6:2271; RV32XTHEADBB-NEXT: or a1, a1, a72272; RV32XTHEADBB-NEXT: or a7, t1, t02273; RV32XTHEADBB-NEXT: srl t0, a6, a42274; RV32XTHEADBB-NEXT: beqz a5, .LBB23_82275; RV32XTHEADBB-NEXT: # %bb.7:2276; RV32XTHEADBB-NEXT: mv a3, a22277; RV32XTHEADBB-NEXT: .LBB23_8:2278; RV32XTHEADBB-NEXT: slli a2, a3, 12279; RV32XTHEADBB-NEXT: srl a3, a3, a42280; RV32XTHEADBB-NEXT: slli a6, a6, 12281; RV32XTHEADBB-NEXT: sll a2, a2, a02282; RV32XTHEADBB-NEXT: sll a0, a6, a02283; RV32XTHEADBB-NEXT: or a2, a2, t02284; RV32XTHEADBB-NEXT: or a0, a0, a32285; RV32XTHEADBB-NEXT: add a7, a7, a02286; RV32XTHEADBB-NEXT: add a0, a1, a22287; RV32XTHEADBB-NEXT: sltu a1, a0, a12288; RV32XTHEADBB-NEXT: add a1, a7, a12289; RV32XTHEADBB-NEXT: ret2290;2291; RV64XTHEADBB-LABEL: rotr_64_mask_multiple:2292; RV64XTHEADBB: # %bb.0:2293; RV64XTHEADBB-NEXT: srl a3, a0, a22294; RV64XTHEADBB-NEXT: neg a4, a22295; RV64XTHEADBB-NEXT: srl a2, a1, a22296; RV64XTHEADBB-NEXT: sll a0, a0, a42297; RV64XTHEADBB-NEXT: sll a1, a1, a42298; RV64XTHEADBB-NEXT: or a0, a3, a02299; RV64XTHEADBB-NEXT: or a1, a2, a12300; RV64XTHEADBB-NEXT: add a0, a0, a12301; RV64XTHEADBB-NEXT: ret2302 %maskedamt = and i64 %amt, 632303 %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %maskedamt)2304 %2 = tail call i64 @llvm.fshr.i64(i64 %b, i64 %b, i64 %maskedamt)2305 %3 = add i64 %1, %22306 ret i64 %32307}2308 2309define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind {2310; RV32I-LABEL: rotl_64_zext:2311; RV32I: # %bb.0:2312; RV32I-NEXT: neg a4, a22313; RV32I-NEXT: addi a6, a2, -322314; RV32I-NEXT: sll a5, a0, a22315; RV32I-NEXT: bltz a6, .LBB24_22316; RV32I-NEXT: # %bb.1:2317; RV32I-NEXT: mv a3, a52318; RV32I-NEXT: j .LBB24_32319; RV32I-NEXT: .LBB24_2:2320; RV32I-NEXT: sll a3, a1, a22321; RV32I-NEXT: not a7, a22322; RV32I-NEXT: srli t0, a0, 12323; RV32I-NEXT: srl a7, t0, a72324; RV32I-NEXT: or a3, a3, a72325; RV32I-NEXT: .LBB24_3:2326; RV32I-NEXT: srai a6, a6, 312327; RV32I-NEXT: li a7, 322328; RV32I-NEXT: and a5, a6, a52329; RV32I-NEXT: sub a6, a7, a22330; RV32I-NEXT: srl a7, a1, a42331; RV32I-NEXT: bltz a6, .LBB24_52332; RV32I-NEXT: # %bb.4:2333; RV32I-NEXT: mv a0, a72334; RV32I-NEXT: j .LBB24_62335; RV32I-NEXT: .LBB24_5:2336; RV32I-NEXT: li t0, 642337; RV32I-NEXT: srl a0, a0, a42338; RV32I-NEXT: sub a2, t0, a22339; RV32I-NEXT: not a2, a22340; RV32I-NEXT: slli a1, a1, 12341; RV32I-NEXT: sll a1, a1, a22342; RV32I-NEXT: or a0, a0, a12343; RV32I-NEXT: .LBB24_6:2344; RV32I-NEXT: srai a1, a6, 312345; RV32I-NEXT: and a1, a1, a72346; RV32I-NEXT: or a1, a3, a12347; RV32I-NEXT: or a0, a5, a02348; RV32I-NEXT: ret2349;2350; RV64I-LABEL: rotl_64_zext:2351; RV64I: # %bb.0:2352; RV64I-NEXT: neg a2, a12353; RV64I-NEXT: sll a1, a0, a12354; RV64I-NEXT: srl a0, a0, a22355; RV64I-NEXT: or a0, a1, a02356; RV64I-NEXT: ret2357;2358; RV32ZBB-LABEL: rotl_64_zext:2359; RV32ZBB: # %bb.0:2360; RV32ZBB-NEXT: neg a4, a22361; RV32ZBB-NEXT: addi a6, a2, -322362; RV32ZBB-NEXT: sll a5, a0, a22363; RV32ZBB-NEXT: bltz a6, .LBB24_22364; RV32ZBB-NEXT: # %bb.1:2365; RV32ZBB-NEXT: mv a3, a52366; RV32ZBB-NEXT: j .LBB24_32367; RV32ZBB-NEXT: .LBB24_2:2368; RV32ZBB-NEXT: sll a3, a1, a22369; RV32ZBB-NEXT: not a7, a22370; RV32ZBB-NEXT: srli t0, a0, 12371; RV32ZBB-NEXT: srl a7, t0, a72372; RV32ZBB-NEXT: or a3, a3, a72373; RV32ZBB-NEXT: .LBB24_3:2374; RV32ZBB-NEXT: srai a6, a6, 312375; RV32ZBB-NEXT: li a7, 322376; RV32ZBB-NEXT: and a5, a6, a52377; RV32ZBB-NEXT: sub a6, a7, a22378; RV32ZBB-NEXT: srl a7, a1, a42379; RV32ZBB-NEXT: bltz a6, .LBB24_52380; RV32ZBB-NEXT: # %bb.4:2381; RV32ZBB-NEXT: mv a0, a72382; RV32ZBB-NEXT: j .LBB24_62383; RV32ZBB-NEXT: .LBB24_5:2384; RV32ZBB-NEXT: li t0, 642385; RV32ZBB-NEXT: srl a0, a0, a42386; RV32ZBB-NEXT: sub a2, t0, a22387; RV32ZBB-NEXT: not a2, a22388; RV32ZBB-NEXT: slli a1, a1, 12389; RV32ZBB-NEXT: sll a1, a1, a22390; RV32ZBB-NEXT: or a0, a0, a12391; RV32ZBB-NEXT: .LBB24_6:2392; RV32ZBB-NEXT: srai a1, a6, 312393; RV32ZBB-NEXT: and a1, a1, a72394; RV32ZBB-NEXT: or a1, a3, a12395; RV32ZBB-NEXT: or a0, a5, a02396; RV32ZBB-NEXT: ret2397;2398; RV64ZBB-LABEL: rotl_64_zext:2399; RV64ZBB: # %bb.0:2400; RV64ZBB-NEXT: rol a0, a0, a12401; RV64ZBB-NEXT: ret2402;2403; RV32XTHEADBB-LABEL: rotl_64_zext:2404; RV32XTHEADBB: # %bb.0:2405; RV32XTHEADBB-NEXT: neg a4, a22406; RV32XTHEADBB-NEXT: addi a6, a2, -322407; RV32XTHEADBB-NEXT: sll a5, a0, a22408; RV32XTHEADBB-NEXT: bltz a6, .LBB24_22409; RV32XTHEADBB-NEXT: # %bb.1:2410; RV32XTHEADBB-NEXT: mv a3, a52411; RV32XTHEADBB-NEXT: j .LBB24_32412; RV32XTHEADBB-NEXT: .LBB24_2:2413; RV32XTHEADBB-NEXT: sll a3, a1, a22414; RV32XTHEADBB-NEXT: not a7, a22415; RV32XTHEADBB-NEXT: srli t0, a0, 12416; RV32XTHEADBB-NEXT: srl a7, t0, a72417; RV32XTHEADBB-NEXT: or a3, a3, a72418; RV32XTHEADBB-NEXT: .LBB24_3:2419; RV32XTHEADBB-NEXT: srai a6, a6, 312420; RV32XTHEADBB-NEXT: li a7, 322421; RV32XTHEADBB-NEXT: and a5, a6, a52422; RV32XTHEADBB-NEXT: sub a6, a7, a22423; RV32XTHEADBB-NEXT: srl a7, a1, a42424; RV32XTHEADBB-NEXT: bltz a6, .LBB24_52425; RV32XTHEADBB-NEXT: # %bb.4:2426; RV32XTHEADBB-NEXT: mv a0, a72427; RV32XTHEADBB-NEXT: j .LBB24_62428; RV32XTHEADBB-NEXT: .LBB24_5:2429; RV32XTHEADBB-NEXT: li t0, 642430; RV32XTHEADBB-NEXT: srl a0, a0, a42431; RV32XTHEADBB-NEXT: sub a2, t0, a22432; RV32XTHEADBB-NEXT: not a2, a22433; RV32XTHEADBB-NEXT: slli a1, a1, 12434; RV32XTHEADBB-NEXT: sll a1, a1, a22435; RV32XTHEADBB-NEXT: or a0, a0, a12436; RV32XTHEADBB-NEXT: .LBB24_6:2437; RV32XTHEADBB-NEXT: srai a1, a6, 312438; RV32XTHEADBB-NEXT: and a1, a1, a72439; RV32XTHEADBB-NEXT: or a1, a3, a12440; RV32XTHEADBB-NEXT: or a0, a5, a02441; RV32XTHEADBB-NEXT: ret2442;2443; RV64XTHEADBB-LABEL: rotl_64_zext:2444; RV64XTHEADBB: # %bb.0:2445; RV64XTHEADBB-NEXT: sll a2, a0, a12446; RV64XTHEADBB-NEXT: neg a1, a12447; RV64XTHEADBB-NEXT: srl a0, a0, a12448; RV64XTHEADBB-NEXT: or a0, a2, a02449; RV64XTHEADBB-NEXT: ret2450 %z = sub i32 64, %y2451 %zext = zext i32 %z to i642452 %zexty = zext i32 %y to i642453 %b = shl i64 %x, %zexty2454 %c = lshr i64 %x, %zext2455 %d = or i64 %b, %c2456 ret i64 %d2457}2458 2459define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind {2460; RV32I-LABEL: rotr_64_zext:2461; RV32I: # %bb.0:2462; RV32I-NEXT: neg a4, a22463; RV32I-NEXT: addi a6, a2, -322464; RV32I-NEXT: srl a5, a1, a22465; RV32I-NEXT: bltz a6, .LBB25_22466; RV32I-NEXT: # %bb.1:2467; RV32I-NEXT: mv a3, a52468; RV32I-NEXT: j .LBB25_32469; RV32I-NEXT: .LBB25_2:2470; RV32I-NEXT: srl a3, a0, a22471; RV32I-NEXT: not a7, a22472; RV32I-NEXT: slli t0, a1, 12473; RV32I-NEXT: sll a7, t0, a72474; RV32I-NEXT: or a3, a3, a72475; RV32I-NEXT: .LBB25_3:2476; RV32I-NEXT: srai a6, a6, 312477; RV32I-NEXT: li a7, 322478; RV32I-NEXT: and a5, a6, a52479; RV32I-NEXT: sub a6, a7, a22480; RV32I-NEXT: sll a7, a0, a42481; RV32I-NEXT: bltz a6, .LBB25_52482; RV32I-NEXT: # %bb.4:2483; RV32I-NEXT: mv a1, a72484; RV32I-NEXT: j .LBB25_62485; RV32I-NEXT: .LBB25_5:2486; RV32I-NEXT: li t0, 642487; RV32I-NEXT: sll a1, a1, a42488; RV32I-NEXT: sub a2, t0, a22489; RV32I-NEXT: not a2, a22490; RV32I-NEXT: srli a0, a0, 12491; RV32I-NEXT: srl a0, a0, a22492; RV32I-NEXT: or a1, a1, a02493; RV32I-NEXT: .LBB25_6:2494; RV32I-NEXT: srai a0, a6, 312495; RV32I-NEXT: and a0, a0, a72496; RV32I-NEXT: or a0, a3, a02497; RV32I-NEXT: or a1, a5, a12498; RV32I-NEXT: ret2499;2500; RV64I-LABEL: rotr_64_zext:2501; RV64I: # %bb.0:2502; RV64I-NEXT: neg a2, a12503; RV64I-NEXT: srl a1, a0, a12504; RV64I-NEXT: sll a0, a0, a22505; RV64I-NEXT: or a0, a1, a02506; RV64I-NEXT: ret2507;2508; RV32ZBB-LABEL: rotr_64_zext:2509; RV32ZBB: # %bb.0:2510; RV32ZBB-NEXT: neg a4, a22511; RV32ZBB-NEXT: addi a6, a2, -322512; RV32ZBB-NEXT: srl a5, a1, a22513; RV32ZBB-NEXT: bltz a6, .LBB25_22514; RV32ZBB-NEXT: # %bb.1:2515; RV32ZBB-NEXT: mv a3, a52516; RV32ZBB-NEXT: j .LBB25_32517; RV32ZBB-NEXT: .LBB25_2:2518; RV32ZBB-NEXT: srl a3, a0, a22519; RV32ZBB-NEXT: not a7, a22520; RV32ZBB-NEXT: slli t0, a1, 12521; RV32ZBB-NEXT: sll a7, t0, a72522; RV32ZBB-NEXT: or a3, a3, a72523; RV32ZBB-NEXT: .LBB25_3:2524; RV32ZBB-NEXT: srai a6, a6, 312525; RV32ZBB-NEXT: li a7, 322526; RV32ZBB-NEXT: and a5, a6, a52527; RV32ZBB-NEXT: sub a6, a7, a22528; RV32ZBB-NEXT: sll a7, a0, a42529; RV32ZBB-NEXT: bltz a6, .LBB25_52530; RV32ZBB-NEXT: # %bb.4:2531; RV32ZBB-NEXT: mv a1, a72532; RV32ZBB-NEXT: j .LBB25_62533; RV32ZBB-NEXT: .LBB25_5:2534; RV32ZBB-NEXT: li t0, 642535; RV32ZBB-NEXT: sll a1, a1, a42536; RV32ZBB-NEXT: sub a2, t0, a22537; RV32ZBB-NEXT: not a2, a22538; RV32ZBB-NEXT: srli a0, a0, 12539; RV32ZBB-NEXT: srl a0, a0, a22540; RV32ZBB-NEXT: or a1, a1, a02541; RV32ZBB-NEXT: .LBB25_6:2542; RV32ZBB-NEXT: srai a0, a6, 312543; RV32ZBB-NEXT: and a0, a0, a72544; RV32ZBB-NEXT: or a0, a3, a02545; RV32ZBB-NEXT: or a1, a5, a12546; RV32ZBB-NEXT: ret2547;2548; RV64ZBB-LABEL: rotr_64_zext:2549; RV64ZBB: # %bb.0:2550; RV64ZBB-NEXT: ror a0, a0, a12551; RV64ZBB-NEXT: ret2552;2553; RV32XTHEADBB-LABEL: rotr_64_zext:2554; RV32XTHEADBB: # %bb.0:2555; RV32XTHEADBB-NEXT: neg a4, a22556; RV32XTHEADBB-NEXT: addi a6, a2, -322557; RV32XTHEADBB-NEXT: srl a5, a1, a22558; RV32XTHEADBB-NEXT: bltz a6, .LBB25_22559; RV32XTHEADBB-NEXT: # %bb.1:2560; RV32XTHEADBB-NEXT: mv a3, a52561; RV32XTHEADBB-NEXT: j .LBB25_32562; RV32XTHEADBB-NEXT: .LBB25_2:2563; RV32XTHEADBB-NEXT: srl a3, a0, a22564; RV32XTHEADBB-NEXT: not a7, a22565; RV32XTHEADBB-NEXT: slli t0, a1, 12566; RV32XTHEADBB-NEXT: sll a7, t0, a72567; RV32XTHEADBB-NEXT: or a3, a3, a72568; RV32XTHEADBB-NEXT: .LBB25_3:2569; RV32XTHEADBB-NEXT: srai a6, a6, 312570; RV32XTHEADBB-NEXT: li a7, 322571; RV32XTHEADBB-NEXT: and a5, a6, a52572; RV32XTHEADBB-NEXT: sub a6, a7, a22573; RV32XTHEADBB-NEXT: sll a7, a0, a42574; RV32XTHEADBB-NEXT: bltz a6, .LBB25_52575; RV32XTHEADBB-NEXT: # %bb.4:2576; RV32XTHEADBB-NEXT: mv a1, a72577; RV32XTHEADBB-NEXT: j .LBB25_62578; RV32XTHEADBB-NEXT: .LBB25_5:2579; RV32XTHEADBB-NEXT: li t0, 642580; RV32XTHEADBB-NEXT: sll a1, a1, a42581; RV32XTHEADBB-NEXT: sub a2, t0, a22582; RV32XTHEADBB-NEXT: not a2, a22583; RV32XTHEADBB-NEXT: srli a0, a0, 12584; RV32XTHEADBB-NEXT: srl a0, a0, a22585; RV32XTHEADBB-NEXT: or a1, a1, a02586; RV32XTHEADBB-NEXT: .LBB25_6:2587; RV32XTHEADBB-NEXT: srai a0, a6, 312588; RV32XTHEADBB-NEXT: and a0, a0, a72589; RV32XTHEADBB-NEXT: or a0, a3, a02590; RV32XTHEADBB-NEXT: or a1, a5, a12591; RV32XTHEADBB-NEXT: ret2592;2593; RV64XTHEADBB-LABEL: rotr_64_zext:2594; RV64XTHEADBB: # %bb.0:2595; RV64XTHEADBB-NEXT: srl a2, a0, a12596; RV64XTHEADBB-NEXT: neg a1, a12597; RV64XTHEADBB-NEXT: sll a0, a0, a12598; RV64XTHEADBB-NEXT: or a0, a2, a02599; RV64XTHEADBB-NEXT: ret2600 %z = sub i32 64, %y2601 %zext = zext i32 %z to i642602 %zexty = zext i32 %y to i642603 %b = lshr i64 %x, %zexty2604 %c = shl i64 %x, %zext2605 %d = or i64 %b, %c2606 ret i64 %d2607}2608